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Edge Detector

1- Rising Edge Detect ( "0" to "1" transition)

We will design a edge detector module that detect the rising edge of any input signal and produce a pulse as a

output

Block diagram of edge detector

VHDL CODE

library IEEE ;use IEEE.STD_L !I"_##$% . ≪

entity edge_detector is 'ort ( cl) * in STD_L !I" ; signal_in * in STD_L !I"; output * out STD_L !I" +;end edge_detector;

architecture ,eha-ioral of edge_detector is signal signal_d *STD_L !I";begin process (cl)+ begin if cl) /#/ and cl)/ e-ent then signal_d0 signal_in; end if; end process;

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output0 ( not signal_d+ and signal_in;end ,eha-ioral;

&fter we simulate the pro1ect with 2odelsim 3 we4ll get the result gi-en below*

1- alling Edge Detect ( "1" to "0" transition)

We will design a edge detector module that detect the falling edge of any input signal and produce a pulse as aoutput.

Block diagram of Edge detector

VHDL CODE

library IEEE ;use IEEE.STD_L !I"_##$% . ≪

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entity edge_detector is 'ort ( cl) * in STD_L !I" ; signal_in * in STD_L !I"; output * out STD_L !I" +;end edge_detector;

architecture ,eha-ioral of edge_detector is signal signal_d *STD_L !I";begin process (cl)+ begin if cl) /#/ and cl)/ e-ent then signal_d0 signal_in; end if; end process; output0 ( not signal_in+ and signal_d ;

end ,eha-ioral;

&fter we simulate the pro1ect with 2odelsim 3 we4ll get the result gi-en below*