ECEN474/704: (Analog) VLSI Circuit Design Spring 2018 · 2020. 10. 30. · Example: Folded-Cascode...
Transcript of ECEN474/704: (Analog) VLSI Circuit Design Spring 2018 · 2020. 10. 30. · Example: Folded-Cascode...
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Sam PalermoAnalog & Mixed-Signal Center
Texas A&M University
Lecture 13: Folded Cascode & Two Stage Miller OTA
ECEN474/704: (Analog) VLSI Circuit Design Spring 2018
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Announcements
• Exam dates reminder• Exam 2 is on Apr. 10• Exam 3 is on May 3 (3PM-5PM)
• Project description is posted on website
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Agenda
• Single-Stage Cascode OTA
• Folded Cascode OTA
• Two Stage Miller OTA
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Simple OTA
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M1 M2Vi+ Vi-
VDD
VSS
Rbias
Itail
M5 M6
M3 M4
CL
Vo
621 || oomoutmv rrgRGA Gain DC
• Gain is limited by single-transistor output resistance
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Single-Stage Cascode OTA
• Gain is larger by a gmro factor• Output swing range is limited
due to large compliance voltage of cascode current source load
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6864241 || oomoommoutmv rrgrrggRGA Gain DC[Razavi]
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Single-Stage Cascode OTA Unity Gain Feedback Voltage Range
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!!! a than Less Range Input) (&Output
conditionsat M2 into plugging and As
saturation M2by set V Maximum
saturationM4by set V Minimum
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24242
4
2
out
4
out
TH
THGSTH
THGSbTHGSbTHxout
xGSxb
THxout
THbout
VVVV
VVVVVVVVVVVVVVVV
VVV
• Cascode configuration constrains output & unity-gain swing
[Razavi]
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Folded Cascode Circuits
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• “Folding” about the cascode node will increase input and output swing range
PMOS Input & NMOS Cascode
NMOS Input & PMOS Cascode
[Razavi]
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Folded Cascode OTA
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[Razavi]
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Folded Cascode OTA Unity Gain Feedback Voltage Range
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• With proper (high-value) choice of Vb2, a decent output and input swing range can be achieved
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2 ||
GSDSATIoutDSATNDSATNCout
THPbout
VVVVVV
VVVMP
Tail
OR saturation sourcecurrent tailor cascode NMOSoutput byset V Minimum
saturation byset V Maximum
out
out
MP
MNC
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TAMU-ELEN-474 2009 Jose Silva-Martinez
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Folded-Cascode OTA: gm, rout and poles?
VB1 and VB2 must keep M1
- M5 in saturation region
VB2 > Vsat,4 + VGS3
VB1 < VDD - Vsat,5 – VSG2
Notice that ID5 biases both M2 and M1
43351221 ; dsmdsdsdsmdsoutmm rgrrrgrrgG
(for M4 sat)
(for M5 sat)
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TAMU-ELEN-474 2009 Jose Silva-Martinez
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Example: Folded-Cascode OPAMP
Find the gain and the phase from input to output and from input to node 2.
The low frequency gain is 77 dB and the unity gain frequency is around 80 MHz.The behavior of the gain from the input to node 2 is interesting: above the dominant pole.
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1
oo
m
ggg
2
1
m
m
gg
Loutoo
mz Crgg
g 1
51
22
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TAMU-Elen-474 Jose Silva-Martinez-08
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FOLDED-CASCODE OTAFrequency response:
Can be approximated as having 4 poles associated
with nodes Vout, VX/W, VZ, and VY
The poles at Vy and Vz are associated to
N-type transistors higher frequencies
mnc
Z
mn
Y
mp
PC
out
outoutmV
gsC
gsC
gsC
gsCRgsA
1
1
1
1
1
1
1
11
vin-
2ID1
M1
MP
vout
VB2
VB1vin+
2ID1
VB2iOUT1
2ID1
VDD
-VSSMN
VB3
MN
VB1
VWVX
VY
VZ
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TAMU-Elen-474 Jose Silva-Martinez-08
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Output referred noiseM1 produces an output current given by
Each transistor M2 generates a differential output current
Similarly, for each transistor M5
At low and medium frequencies, noise contribution of the cascode transistors can be neglected (M3 and M4)
Vn4
ro5
i04
M405
4n4n
054m
4m04 r
vv
rg1g
i
For cascode transistors
1n1m01 vgi
2n2m02 vgi
5n5m05 vgi
vin-
2ID1
M1
M2
vout
VB2
VB1vin+
2ID1
VB2iOUT1
2ID1
VDD
-VSSMN
VB3
MN
VB1
VWVX
VY
VZM4
M5
M3
iout2 = 2(ieq12 + ieq22 + ieqn2 )
meq kTgi 382 Remember
mnmmout gggkTfi
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316
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TAMU-Elen-474 Jose Silva-Martinez-08
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Noise level for the folded-cascode OTA
Let’s find the input rms noise
Low-noise is associated with large gm1 and relatively small gm2 and gm5
BW m
m
m
m
mnoise dfg
ggg
gkTv 2
1
52
1
2
1
13
16
1
5
1
2
1
18
m
m
m
m
mnoise g
gggBW
gkTv
Or for a dominant (single) pole system with NBW = (/2)BW
vin-
2ID1
M1
M2
vout
VB2
VB1vin+
2ID1
VB2iOUT1
2ID1
VDD
-VSSM5
VB3
M5
VB1
VWVX
VY
VZ
Noise of diff pair Noise Factor (due to other transistors)
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212
22 13
161
mmnmm
m
outin
ggggkT
Gfi
fv
Considering thermal noise only
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Multi-Stage Amplifiers
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• Single-stage amplifiers typically have to trade-off gain and swing range
• Multi-stage amplifiers allow for higher gain without sacrificing swing range
• The major challenge with multi-stage amplifiers is achieving adequate phase margin to insure stability in a feedback configuration
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Two Stage Miller OTA
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42
2818
78
7842
82
78
8
42
221
1
oo
mmvmm
ooout
outmVDC
oooo
mm
oo
m
oo
mvvVDC
ggggAgG
ggR
RGAgggg
gggg
ggg
gAAA
Gain DC
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Two-Stage Miller OTA – Frequency Response
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• Stage 1 is a differential amplifier with an active load
• Stage 2 is a common-source amplifier with a large miller capacitor
• Using a Thevenin equivalent for Stage 1, we can use the common-source equations from Lecture 8
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Two-Stage Miller OTA – Frequency Response
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• The amplifier should be designed to yield one dominant pole, so we use the dominant pole approximation equations
872421
8
21
22812
28122811
and where
1
11
1esCapacitancTransistorNeglecting
OOoutOOout
L
m
LCoutout
LCoutCoutmoutp
CoutmoutLCoutCoutmoutp
rrRrrRCg
CCRRCCRCRgR
CRgRCCRCRgR
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Jose Silva-Martinez -19- Texas A&M University
ELEN-474
VSS
M1 M1
01i 01i
-vd
01iM2 M2
02iM3
012i
vd
R1 C1RL CL
-v0
VDD
2
1
1
1
21
2
1
11
3
1
1
tantan180arg_
,min*
p
u
p
u
ppVDC
L
Lp
p
L
mmVDC
inmPhase
AGBWCgCg
gg
ggA
valid?) system, poledominant (if
(LHP)
(LHP)
Main equations
p1 p2 GBW
AVDCPhase Margin < 45 degrees
Phase
u
21
11pp
VDC
ssAsA
Frequency Response – No Compensation
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TAMU-Elen-474 Jose Silva-Martinez-08
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VSS
M1 M1
01i 01i
-vd
01iM2 M2
02iM3
012i
vd
R1 C1 CMRL CL
-v0
VDD
Phase compensation Pole splitting techniques!!
p1 p2
GBW
AVDCAfter compensation Phase Margin > 45 degrees Bandwidth is reduced!!!
p1’
p2’u
2
1
1
1
11
1
32
31
11
3
1
1
tantan180arg_
*
pp
M
mpVDC
L
mp
ML
mp
L
mmVDC
WGBWGBinmPhase
CgAWGB
CCg
CggC
ggg
ggA
(LHP)
(LHP)
Frequency Response – Miller Compensation (Ignoring z)
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TAMU-Elen-474 Jose Silva-Martinez-08
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ZEROpp
M
mpVDC
L
mp
ML
mp
L
mmVDC
WGBWGBWGBinmPhase
CgAWGB
CCg
CggC
ggg
ggA
1
2
1
1
1
11
1
32
31
11
3
1
1
tantantan180arg_
*
(LHP)
(LHP)
VSS
M1 M1
01i 01i
-vd
01iM2 M2
02iM3
012i
vd
R1 C1 CMRL CL
-v0
VDD
Parasitic (bad) RHP zero!!
p1 p2
GBW
AVDCAfter compensation Phase Margin > 45 degrees Bandwidth is reduced!!!
p1’
GBW’ZERO
(RHP) M
mZERO C
g 3
p2’
21
11
1
pp
zVDC
ss
sAsA
Frequency Response – Miller Compensation (Considering z)
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TAMU-Elen-474 Jose Silva-Martinez-08
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VSS
M1 M1
01i 01i
-vd
01iM2 M2
02iM3
012i
vd
R1 C1 CMRL CL
-v0
VDD
ZERO
u1
2p
u1
1p
u1 tan'
tan'
tan180inargm_Phase
Parasitic (bad) RHP zero!! Can be catastrophic if close or below wu!
p1 p2
GBW
AVDC After compensation Phase Margin > 45 degrees Bandwidth is reduced!!!
p1’
GBW’ZERO
M
3mZERO C
g
p2’
p1 p2
GBW
AVDC
After compensation Phase Margin
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TAMU-Elen-474 Jose Silva-Martinez-08
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VSS
M1 M1
01i 01i
-vd
01iM2 M2
02iM3
012i
vd
R1 C1 CMRL CL
-v0
VDD
M4VBIB1
IB2
Adding a series resistance
RZ
321
111
1
ppp
zVDC
sss
sAsA
13
1CRZ
p
MZm
z
CRg
3
11
(Generally high frequency & can be ignored)
p2
Z
Z
cancel can
LFP to RHP from zero pushes
infinity to zero RHP the pushes
)(initially frequencyhigher a to RHP push will R zero-Nonmargin phase improve to R design Can
Mm
MLZ
mZ
mZ
CgCCCR
gR
gR
3
1
3
3
1
1
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Two Stage Miller OTA Noise
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2
42
82
784
22
22
2
42
84
2
42
8278
2
22381
PSD Voltage Noise Referred-Input
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8
PSDCurrent NoiseReferred-Output
oo
mm
mmm
mm
oi
oo
mm
oo
mmmm
o
gggg
ggggkT
Gfi
fv
gggg
ggggggkT
fi
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Next Time
• OpAmp Feedback & Stability• Common-Mode Feedback Techniques
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