ECE745_syllabus_2014

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ECE 745 : ASIC Verification Course Overview & Policies Instructor: Dr. Meeta Yadav Dr. Yadav Office Hours: Friday 5:00 pm (email for phone number) E-mails: {myadav}@ncsu.edu Website www.courses.ncsu.edu/ece745/ C. Spear, “System Verilog for Verification” (Kluwer), 2006 or most recent. Prerequisite: ECE 520 ASIC Design or equivalent. Course Goal: 1. To prepare the student to be an entry-level industrial standard cell ASIC verification engineer. 2. To give the student an understanding of issues and tools related to ASIC verification, with a focus on the methodologies supported by the SystemVerilog language. 1. Students will be able to verify a complex digital functional block, finding most of the contained bugs, using 2. Students will demonstrate an understanding of the basic methodologies used in ASIC Verification and their implementation using SystemVerilog. Grade Breakdown Labs 30% Midterm 1 15% Midterm 2 20% Project 35% The tutorials are learning exercises and have to be done individually. All tests are open book/open-notes. The audit requirement is to complete the project to a B standard or better or finish the labs. Please note that it is easy to detect cheating in a project like this. Though

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Transcript of ECE745_syllabus_2014

Page 1: ECE745_syllabus_2014

ECE 745 : ASIC Verification Course Overview & Policies Instructor: Dr. Meeta Yadav Dr. Yadav Office Hours: Friday 5:00 pm (email for phone number) E-mails: {myadav}@ncsu.edu Website www.courses.ncsu.edu/ece745/ C. Spear, “System Verilog for Verification” (Kluwer), 2006 or most recent. Prerequisite: ECE 520 ASIC Design or equivalent. Course Goal: 1. To prepare the student to be an entry-level industrial standard cell ASIC verification engineer. 2. To give the student an understanding of issues and tools related to ASIC verification, with a focus on the methodologies supported by the SystemVerilog language. 1. Students will be able to verify a complex digital functional block, finding most of the contained bugs, using 2. Students will demonstrate an understanding of the basic methodologies used in ASIC Verification and their implementation using SystemVerilog. Grade Breakdown Labs 30% Midterm 1 15% Midterm 2 20% Project 35% The tutorials are learning exercises and have to be done individually. All tests are open book/open-notes. The audit requirement is to complete the project to a B standard or better or finish the labs. Please note that it is easy to detect cheating in a project like this. Though

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collaboration (sharing ideas and concepts) is encouraged, sharing of code is Reasonable accommodations will be made for students with verifiable disabilities. In order to take advantage of available accommodations, students must register with Disability Services for Students at 1900 Student Health Center, Campus Box 7509, 515-7653. http://www.ncsu.edu/provost/offices/affirm_action/dss/ For more information on NC State's policy on working with students with disabilities, please see http://www.ncsu.edu/provost/hat/current/appendix/appen_k.html All the provisions of the code of academic integrity (www.ncsu.edu/provost/academic_policies/integrit/reg.htm ) apply to this course. In addition, it is my understanding and expectation that your signature on any test or assignment means that you neither gave nor received unauthorized aid. Online class evaluations will be available for students to complete during the last two weeks of class (November 26-December 9). Students will receive an email message directing them to a website where they can login using their Unity ID and complete evaluations. All evaluations are confidential; instructors will never know how any one student responded to any question, and students will never know the ratings for any particular instructors evaluation. In addition, please feel free to provide anonymous feedback during semester using Wolfware.