ECE665- Computer Algorithms Optimal Layout of CMOS Functional Arrays T akao Uehara William M....

ECE665- Computer AlgorithmsOptimal Layout of CMOS Optimal Layout of CMOS

Functional ArraysFunctional ArraysTakao Uehara

William M. VanCleemput

Presented By : Gregory Holder University of Massachusetts

Amherst (Spring2004)

May 13,2004 Optimal layout of CMOS Functional Arrays

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Outline:Outline:Weinberger methodologyOptimized approach (Sorry Weinberger!)Graph-theoretical algorithmHeuristicsConclusionReferences


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Weinberger methodologyWeinberger methodology• Also called “Weingberger approach”

[weinberger67] this method a (structured approach) was traditionally used in the 1980s where the data wires are routed in parallel to the supply rails and perpendicular to the diffusion areas.

• This technique was most efficient for bit sliced datapaths, because of the “over the cell wiring”.

• Figure 1 on the next slide shows this technique.


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Weignberger approachWeignberger approach• A more efficient

technique has been introduced called the “standard-cell technique”, where signals are now routed vertically and polysilicon can serve for both Nmos and Pmos devices. This has given been the focus of using the

Euler Approach.

Figure1Figure1• Weinberger (using a

single metal layer m1)


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Optimized approach (Euler Optimized approach (Euler Path)Path)• The Euler path technique

has been used in what is called the “standard cell technique”, which results in a dense layout for CMOS gates and one polysilicon strip that can serve as the input to both NMOS and PMOS devices.

• Our main aim is to have a single strip of diffusion in both NMOS and PMOS devices. This depends on the “ordering” of the inputs. How do we determine the best order?

Figure 2Figure 2


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Two Versions of C Two Versions of C •• (A + B) (A + B)11(Observe the input order)


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Graph the theoretical approachGraph the theoretical approach• To reduce the size of an array and an uninterrupted

diffusion strip we need to find this “Euler path” talked about previously. This is defined as the path through all nodes or vertices (source and drain signals) such that each edge( transistor gate inputs) is only visited exactly once. (vertices maybe visited more than once).

• Euler paths are not unique.• Euler paths must be consistent (same ordering in

both PUN (pull up network) and PDN (pull down network).

• Can Run in linear time3.


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Consistent Euler PathConsistent Euler Path11

j

VDDX

X

i

GND

AB

C

A B C

PUN

PDNC

A B

X = C • (A + B)

B

AC

i

j

ABC


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The General AlgorithmThe General Algorithm 1. Enumerate all possible

decompositions to find the minimum number of Euler paths that cover the graph.

2. Chain by means of diffusion area according to the order of edges in Euler path.

3. If more than 2 edges are necessary to cover the graph model, then provide a separation area between each pair of chains.

• Therefore for the previous consistent Euler path for the logic structure we achieve the optimal layout below.

Figure 3Figure 3


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Heuristic AlgorithmHeuristic Algorithm(of course life not being so easy)Theorem:

1) The following example and any circuit will have a single Euler path if the number of inputs to every AND/OR element is odd. Inaddition,

2) There exist a graph model such that the sequence of edges on an Euler path corresponding to the vertical order of the inputs on a planar representation of the logic diagram.

The Heuristic Algorithm1) To every gate with an even

number of inputs add a “pseudo” input.

2) The “pseudo” input does not contribute to separation area. But this input is added so that there is a minimal combination between “pseudo” and real inputs.

3) Construct the graph model according to the vertical order of inputs on logic diagram.

4) Chain together the gates by means of diffusion areas as indicated by the sequence of edges on the Euler path. A “pseudo" input gives a separation between diffusions.

5) Delete “Pesudo” edges in parallel and contacting “pseudo” edges in series with other edges for final circuit.


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ExampleExample We consider the following

logic Circuit (a and b), the derivedEuler Path (c) and the corresponding Layout. For ourEuler path the PUN- and

thePDN -----.


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Heuristic WorksHeuristic WorksWe apply our Heuristicapproach to the previousexample and we obtain thefollowing sequence(p1,2,3,1,4,5,p2) where weremove the “pseudo” inputsto get the same layoutpreviously shown in slide11. (Note we choose thecombination with theminimum interlaced with realinputs) hence circuit (b).


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AnalysisAnalysis 1. It must be noted that theheuristic algorithm may not always give the optimal layout but if the resulting sequence. However, if noseparation areas areobtained then this isthe optimal solution.

2. The heuristic gives excellentresults for circuits which do not have a Euler path. This is Illustrated in the four-bit carry look-ahead adder3 circuitshown in this slide.


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Analysis (continued)Analysis (continued)Here in (b) we see the

final Euler Path interpretation the corresponding circuit diagram (c) and the a

final layout.


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ConclusionConclusion• This Presentation has given a brief incite

into optimizing the layout of complex CMOS gates. Using the Euler path approach and a heuristic algorithm. The results show that by use of this approach we can optimize considerably on area in our layout. Further work can be done to simulate the “real” gain of this method in terms of power and performance of a particular design.


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ReferencesReferences 1. Digital integrated circuits 2nd edition2. Uehara, T. and Vancleemput, W. M

“optimal layout of CMOS Functional Arrays”.

3. Robert Sedgewick “Algorithms in C third edition”.

4. Forbes, B. E. “Silicon-on Sapphire Technology Produces High-Speed Single- Chip Processor, “Hewlett-Packard Journal, April 1977,pp 2-8.


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Thanks To ALLThanks To ALL

ECE665- Computer Algorithms Optimal Layout of CMOS Functional Arrays T akao Uehara William M....

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