ECE606: Solid State Devices Lecture 23 MOSFET I-V ...ee606/downloads/... · ECE606: Solid State...

Klimeck – ECE606 Fall 2012 – notes adopted from Alam

ECE606: Solid State DevicesLecture 23

MOSFET I-V CharacteristicsMOSFET non-idealities

Gerhard [email protected]


Outline

2

1) Square law/ simplified bulk charge theory2) Velocity saturation in simplified theory3) Few comments about bulk charge theory, small

transistors 4) Flat band voltage - What is it and how to measure it?5) Threshold voltage shift due to trapped charges6) Conclusion

Ref: Sec. 16.4 of SDF Chapter 18, SDF


Post-Threshold MOS Current (VG>Vth)

3

( )0

= − ∫DSV

D effch

iQI VVW

dL

µ

1) Square Law

2) Bulk Charge

3) Simplified Bulk Charge

4) “Exact” (Pao-Sah or Pierret-Shields)

[ ]) )( = − − −i G G TC V VQ mVV

[ ]) )( = − − −G Ti GC V VV VQ

( )2 22( )

+ = − − − − −

Si A BG Gi FB B

O

Qq N V

C V V VVC

ε φψ

Formula overview –derivation to follow


2ψ B

Effect of Gate Bias

4

P

S G D

B

VGS

n+ n+

Gated doped or p-MOS with adjacent n+ regiona) gate biased at flat-bandb) gate biased in inversion

A. Grove, Physics of Semiconductor Devices, 1967.

WDM

VGS > VT

WD

VBI

y

No source-drain bias


The Effect of Drain Bias

Alam ECE-606 S09 5

2D band diagram for an n-MOSFET

a) device

b) equilibrium (flat band)

c) equilibrium (ψS > 0)

d) non-equilibrium with VG and VD >0 applied

SM. Sze, Physics of Semiconductor Devices, 1981 and Pao and Sah.

FNDepletion very different in source and drain side Gate voltage must ensure channel formation=> LARGE


Effect of a Reverse Bias at Drain

6

ψ S = 2ψ B + VRVBI + VR

WDM

VGS > VT VR( )

WD

VRVR

Gated doped or p-MOS with adjacent, reverse-biased n+ regiona) gate biased at flat-bandb) gate biased in depletionc) gate biased in inversion

A. Grove, Physics of Semiconductor Devices, 1967.

VR


Inversion Charge in the Channel

7

P

S G

B

n+ n+ ( )

( ( 0)( ) )i ox G th

TA T

Q C V V V

q VVN W W

= − − −+ − =

VG=0VD=0

VVB

VG=0VD>0

VD

VB

VG>0VD>0

D

Channel - Drain)Band diagrams (Gate –

Channel - Drain)

Body potential = constant, n+ region potential lowered

Due to drain bias, additional gate voltage (as compared to threshold in MOSCAP) is now needed to invert the channel throughout its

length


Inversion Charge at one point in Channel

8

VGVD

VBVG

( )* 2( )A

th Fox

Tq W VNV V

Cφ= + −2

( 0)A Tth F

ox

Wq

C

VNV φ= =−

( )* ( ( 0))T TAth th

ox

qNV V

W WVV

V

C

=−= + −

*( )i ox G thQ C V V= − −

V

Threshold voltage in the presence of drain

bias


Approximations for Inversion Charge

9

( )( ) ( ) ( 0)i O G th A T TQ C V V V qN W V W V= − − − + − =

( ) ( )2 2( ) 22 = − − − + −

+O G th S o A S oB A BC V V V q N q NVφ φκ ε κ ε

( )i ox G thQ C V V V≈ − − −

( )i ox G thQ C V VmV≈ − − −

Approximations:

Square law approximation …

Simplified bulk charge approximation …


The MOSFET

10

P

S G D

B

n+ n+

VS = 0 VD > 0

Fn = Fp = EF

Fn = Fp − qVD

Fn increasingly negative from source to drain(reverse bias increases from source to drain)


Elements of Square-law Theory

11

VG VD>00

y

GCA : Ey << Ex

[ ]( ) ( )i ox G thQ y C V V mV y= − − −

VG V VG

Voltage and hence inversion charge vary spatially


Charge along the channel ….

p

n

( )− −= C nE FCn N e β ( )−= V pE F

Cp N e β


Charge along the channel …

( )− −= C nE FCn N e β ( )−= V pE F

Cp N e β

VG VD>00

VD


Depletion into the channel ….

NA

n

( )− −= C nE FCn N e β ( )−= V pE F

Cp N e β

VG

WT(VD=0) WT(VD)

VD


Depletion into the channel …

VG VD>00

Depletion


Another view of Channel Potential

16

FP

FNFN

FPFP

FN

EC

EFEV

N+ N+P-doped

Source Drain

x

x


Square Law Theory

17

VG VD>00

VD

Q

V1, 1,

1, 0

( )D

ii

i N i N

V

Dox G th

i N

J dyQ dV

Jdy C V V mV dV

µ

µ

= =

=

=

= − −

∑ ∑

∑ ∫

1 1 1 1

1

2 2 2 2

2

3 3 3 3

3

4 4 4 4

4

dVJ Q Q

dy

dVJ Q Q

dy

dVJ Q Q

dy

dVJ Q Q

dy

µ µ

µ µ

µ µ

µ µ

= =

= =

= =

= =

E

E

E

E

( )2

2ox D

D G th Dch

C VJ V V V m

L

µ = − −

Q1Q2 Q3 Q4


Square Law or Simplified Bulk Charge Theory

18

( )2

2o

D G Tch

W CI V V

mL

µ= −ID

VDS

VGS

( )D o G T D

WI C V V V

Lµ= −

VDSAT = VGS − VT( )/ m

( )2

2ox D

D G th Dch

C VI W V V V m

L

µ = − −

( )2

2ox D

D G th Dch

C VJ V V V m

L

µ = − −

( ) ( )*,0= = − − ⇒ = −D

G th D D sat G th

dIV V mV V V V m

dV

Region of validity for the expression for currents

Unphysical, since current does not decrease with increase in

Vd


Why square law? And why does it become invalid

19

( )2

2o

D G Tch

W CI V V

mL

µ= −

ID

VDS

VGS

VDSAT = VGS − VT( )/ m

( )i ox G thQ C V V mV≈ − − −

VG VD>00

Q

This situation doesn’t arise since electrons travelling from left to right are swept into the drain under the effect of the reverse bias applied


Linear Region (Low VDS)

20

ID

VDS small

VGS

( )D o G T Dch

DS

CH

WI C V V V

L

V

R

µ= −

=

Actual

SubthresholdConduction

VT

Mobility degradation at high VGS

Slope gives mobility

Intercept gives VT

Can get VT also from C-V

( )2

2ox D

D G th D

ch

C VI W V V V m

L

µ = − −


Outline

21





Velocity vs. Field Characteristic (electrons)

Electric field V/cm --->

velo

city

cm

/s -

-->

107

104

υ = υ sat

1/ 221 ( )

−= +

d

c

µυ E

E E

1 ( )

−=+d

c

µυ E

E E

, =d sat cυ µEυ = µE

22

Velocity saturates at high fields because of scattering

This expression can be used to re-derive the expression for current since since mobility is now, in principle, a function of distance


Recap - derivation for MOSFET current

23

VG VD>00

1 1 1 1 1 1

1

2 2 2 2 2 2

2

3 3 3 3 3 3

3

4 4 4 4 4 4

4

dVJ Q Q

dy

dVJ Q Q

dy

dVJ Q Q

dy

dVJ Q Q

dy

µ µ

µ µ

µ µ

µ µ

= =

= =

= =

= =

E

E

E

E1, 1,( )= =

⇒ =∑ ∑ii

i N i N

J dyQ dV

yµ


Velocity Saturation

24

VD

Q

V

υ vsat

1, 00

( )

1=

= − −

+

∑ ∫DV

D ox G thi N

c

dyJ C V V mV dV

µE

E

( )2

0

2ox D

D G th DD

chc

C mVJ V V V

VL

µ = − −

+E

( )2

0 0 2

11

+ = − −

∫chL

D Dox G th D

c

J mVdy C V V V

dV

dyµ E

( )2

0 0 2

+ = − −

∫ ∫ch DSL

D

V

Dox G t D

chD

mVC

Jd VJ V V

EVdy

VG VD>00


Significance of the new expression

25

( )2

0

2ox D

D G th DD

chc

C mVJ V V V

VL

µ = − −

+E

• At very small channel lengths and high drain biases, the current expression becomes independent of the channel length

• In the linear region in the I-Vd characteristics, you have a resistance that doesn’t depend on the length of the channel


Calculating VDSAT

dID

dVDS

= 0

( )2

2

= − −

+

D o ox DG th D

Dch

c

I C VV V V m

VW L

µ

E

VDSAT

=2 V

G−V

th( ) / m

1+ 1+ 2µo

VG

−Vth( ) mυ

satL

ch

26

Take log on both sides and then set the derivative to zero ….

<V

GS−V

T( )m


Velocity Saturation in short channel devices

( )= −D ox sat G TI WC V VυID

VDS

VGS

( )2

,

,0, , 2

= − −

+

D satoxD sat G th D sat

cD sat

Ch

mVCJ V V

LV

Vµ

E

27

This expression can be derived by plugging in the value of Vd,sat for the short channel regime


‘Linear Law’ Expression at the limit of L --> 0

( )( )0

2 /

1 1 2

−=

+ + −G th

DSAT

G th sat ch

V V mV

V V m Lµ υ

( )= −DSAT ox sat G thI W C V Vυ

( ) 02→ −DSAT sat ch G thV L V V mυ µ

( ) ( )( )

0

0

1 2 1

1 2 1

+ − −= −

+ − +G th sat ch

DSAT ox sat G th

G th sat ch

V V m LI W C V V

V V m L

µ υυ

µ υ

Complete velocity saturation

Current independent of L

28


‘Signature’ of Velocity Saturation

29

ID

VDS

VGS

( )−=D sa G ht toxI W C V Vυ

ID

VDS

VGS

( )0

2

2

−=D ox

ch

G thWI C

V V

L mµ

Can pull out oxide thickness from experimental curves… How?


ID and (VGS - VT): In practice …..

30

ID

VDS

VGS

( )( ) ~= −D D DD G thI V V V Vα

1< α < 2

Long channelComplete velocity saturation


Outline

31





Approximations for Inversion Charge

( )( ) ( ) ( 0)i O G th A T TQ C V V V qN W V W V= − − − + − =

( ) ( )( ) 2 2 2 2O G th S o A B S o A BC V V V q N V q Nκ ε φ κ ε φ= − − − + + −

( )i ox G thQ C V V V≈ − − −

( )i ox G thQ C V V mV≈ − − −

Approximations:

Square law approximation …

Simplified bulk charge approximation …

32

One could substitute the expression for Qi above explicitly instead of using m to simplify the equation, resulting in a more complete bulk charge expression


Complete Bulk-charge Theory

01,0 0

[.........( ) .]=

= − − +∑ ∫ ∫D DV

DO G th

i N

VJ

dy C V V V dV dVµ

( )3 / 22

0 4 31 1

3 2 42

+ − +

= − − −

A T D DF

O F

ox DD G th D

ch F

C VJ V V V

L

qN W V V

Cφ

φµ

φ

00 0 0

[...... . .]( ) . .= − − +∫ ∫ ∫ch D DL V

DO G th

VJ

dy C V V V dV dVµ

(Eq. 17.28 in SDF) …. Explicit dependence on bulk doping

33

Additional V dependent terms abstracted into m previously


Velocity Overshoot

0.0 10 0

5.0 10 6

1.0 10 7

1.5 10 7

2.0 10 7

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0 0.5 1 1.5

Ave

rage

vel

ocity

(cm

/s)

Kin

etic

ene

rgy

per

elec

tron

(eV

)

Position (µm)

103 V/cm 103 V/cm105 V/cm

υ ≠ µn E( )E

υsat

34

Valid for bulk semiconductors, not valid at top of the barrier


Velocity Overshoot in a MOSFET

35


Intermediate Summary

1) Velocity saturation is an important consideration for short

channel transistors (e.g., VD=1V, Lch=20nm). Therefore,

α ~ 1 for most modern transistors.

2) Bulk charge theory explains why MOSFET current

depends on substrate (bulk) doping. In the simplified bulk

charge theory, doping dependence is encapsulated in m.

3) Additional considerations of velocity overshoot could

complicate calculation of current.

4) Good news is that for very short channel transistors,

electrons travel from source to drain without scattering. A

considerably simpler ‘Lundstrom theory of MOSFET’

applies. 36


Outline

37


transistors 4) Flat band voltage - What is it and how to measure

it?5) Threshold voltage shift due to trapped charges6) Conclusion


,

( )IT sM M Fth th ideal

O OMS

O

QQ QV V

C C C

φγφ= + − − −

( )( ) ~= −D D DD G thI V V V Vα

1< α < 2


(1) Idealized MOS Capacitor

38

Substrate (p)yχs

Φm

χi

EC

EVEF

p semiconductormetal insulator

Vacuum level

,( )= −i ox G th idealQ C V V

Recall that

,

2=

= −s F

Bth ideal s

ox

QV

C ψ φ

ψ

In the idealized MOS capacitor, the Fermi Levels in metal and semiconductor align perfectly so that at zero applied bias, the energy bands are flat


Potential, Field, Charges

39

χs

Φm

χiV

E

Vbi=0 ρ

x

x

x

No built in potential, fields or charges at zero applied bias in the idealized MOS structure


Real MOS Capacitor with ΦΦΦΦM < ΦΦΦΦS

40

ΦM = qφm χS

ΦS

qψ S > 0

EC

EV

EF

EVAC

EC

EV

EF

Note the difference

Do we need to apply less or more VG to invert the channel ?

In reality, the metal and semiconductor Fermi Levels are never aligned perfectly � when you

bring them together there is charge transfer from the bulk of the semiconductor to the

surface so that we have alignment


Physical Interpretation of Flatband Voltage

41

ψS = 0 flat band

EC

EV

EF

0FB ms biV Vφ= = − <

VG = VFB < 0

EC

EV

EF

VG = 0

Vbi = −φms > 0+ −

The Flatband Voltage is the voltage applied to the gate that gives zero-band bending in the MOS structure. Applying this voltage nullifies the effect of the built-in potential. This voltage needs to be

incorporated into the idealized MOS analysis while calculating threshold voltage


How to Calculate Built-in or Flat-band Voltage

42

χs

Φm

Vacuum level

EV

EF

EC

( )= + − ∆ −

=

Φ

≡bi g p

FB MS

s MqV E

qV φ

χ qVbi

( )i ox G thQ C V V= −

Therefore,

2

= − −

Bth F

oxFB

QV

CVφ

The presence of a flatband voltage lowers or raises the threshold voltage of a MOS structure. Engineering question � Is it desirable to have a metal having a work function greater or less

than the electron affinity+(Ec-Ef) in the semiconductor?


Measure of Flat-band shift from C-V Characteristics

43

C/Cox

VG

Ideal Vth

Actual Vth

The transition point between accumulation and depletion in a non-ideal MOS structure is shifted to the left when the metal work function is smaller that the electron affinity +(Ec-Ef). At zero applied bias the semiconductor is already depleted so that a very small positive bias inverts the channel. The flatband voltage is the amount of voltage required to shift the

curve such that the transition point is at zero bias.


Outline

44




,

( )= + − −− M M F IT st

o

h th ideal M

x

S

ox ox

Q QV

CCV

C

Q φγφ


(2) Idealized MOS Capacitor

45

χsΦm

χi

EC

EV

EF

p semiconductormetal insulator

Vacuum level

,( )= −i ox G th idealQ C V V

Recall that

,

2=

= −s F

Bth ideal s

ox

QV

C ψ φ

ψ

Substrate (p)y

Qox

=0


Distributed Trapped charge in the Oxide

46

EC

EV

EF

Ox

0x

= − −F Mth S

oM

x ox

Q QV

C Cψ γ

0

( )OX

M ox xQ dxρ= ∫

0

0

0

00

0

( )

( )

≡ =∫

∫

ox

ox

x

MM

x

x dxx

xxx dx

xρ

ργ

In the absence of charges in the oxide, the field is constant (dV/dx = constant). The presence of a charge distribution inside the oxide changes the field inside the oxide and effectively traps field lines comping from the gate. As a result, depending on the polarity of charges in the oxie, the threshold voltage is modified.

xm represents the centroid of the charge distribution – one can think of this as replacing the entire distribution with a

delta charge at this point


An Intuitive View

47

Ideal charge-free oxide

-E

0

Bulk charge

-E

0

-E

Interface charge

0

Reduced gate charge


Gate Voltage and Oxide Charge

48

VG

=Vox

+ψs

2

20

( )− = =ox o

o

xx o

x

d V d

dx d

x

x κρ

εE

0 0( )

0( )

( ') 'x x

oxox

oxx x

x dxd

ρκ ε

=∫ ∫E

E

E

−dV

ox

dx=E

ox(x

0) −E

ox(x ) =E

ox(x

0) −

ρox

(x ')dx '

κox

ε00

x

∫

Vox

=κ

S

κox

x0E

S(x

0) − dx

0

x0

∫ρ

ox(x ')dx '

κox

ε00

x0

∫

=κ

S

κox

x0E

S(x

0) −

x ρox

(x )dx

κox

ε00

x0

∫

-E

0

Kirchoff’s Law – balancing voltages

Known from boundary conditions in semiconductor

and continuity of E


Gate Voltage and Oxide Charge

49

0

0 00 0

(

( 2 )

1( 2 ) )) (

= = + ∆

= = + − ∫

th s F ox

x

Sos F xS

ox o

V V

x x x dxC x

x

ψ φ

κψ φκ

ρE

0

0

0

0

0

00

( )( )

x

Sox S

ox

x

o

o xx dxV x

xx

xκ ε

κκ

ρ∆ = −

∫E

0

0 00 0

( () )1= − ∫

oox

x

SS

ox x

x x x dxx

xCκ

ρκE

0

,0 0

,

( )1= −

= −

∫ o

x

th ideal

ox

Mth ideal

ox

x

M

V x dxC x

QV

C

xρ

γ


Interpretation for Bulk Charge

50

0

1,0

1,

0

1

0

( ) ( )

(

1

)

= −

= −

−∫x

th th idealo

th id

o

o

x

Meal

V V x x x dx

Q x

xC x

xV

x C

ρ δ

C/Cox

VG

Ideal VT

New VT


Interpretation for Interface Charge

51

0

*

0 0

*

( ) ( )1

ox o

x

th th

o

Fth

o

V V x dxC x

V

x x

C

x

Q

ρ δ= −

= −

−∫

C/Cox

VG

Ideal VT

New VT


Time-dependent shift of Trapped Charge

52

E

0

, 10 0

1,

0

1( ) ( ( ))

( ) ( )

= − × −

= − ×

∫x

th th ideal oxox

oxth ideal

ox

V V xQ x x x t dxC x

x t Q xV

x C

δ

Sodium related bias temperature instability (BTI) issue

C/Cox

VG

Ideal VT


Bias Temperature Instability (Experiment)

53

----------

+++++

+++++

M O S

(-) biases

0 xo

0.1xo

x

ρio

n

M O S----------

+++

++

+++++

(+) biases

x

0 xo

ρio

n

0.9xo


Conclusion

54

1) Non-ideal threshold characteristics are important

consideration of MOSFET design.

2) The non-idealities arise from differences in gate and

substrate work function, trapped charges, interface

states.

3) Although nonindeal effects often arise from transistor

degradation, there are many cases where these

effects can be used to enhance desirable

characteristics.

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