Ece590 April 2010
-
Upload
cayangbucuk -
Category
Documents
-
view
218 -
download
0
Transcript of Ece590 April 2010
-
8/12/2019 Ece590 April 2010
1/13
CONFIDENT IAL EE/APR 2010/ECE590/KJE609/416
UNIVERSITI TEKNOLOGI MARAFINAL EXAMINATION
COURSECOURSE CODEEXAMINATIONTIME
: ELECTRONICS AND MICROPROCESSOR S: ECE590/KJE609/416: APR IL 2010: 3 HOURS
INSTRUCTIONS TO CANDIDATES1 . This que stion paper consists of five (5) questions.2. Answer ALL questions in the Answe r Booklet. Start each answer on a new page.3. Do not bring any mate rial into the exam ination room unless permission is given by theinvigilator.4. Please check to make sure that this examination pack consists of :
i) the Question Paperii) a six - page Appe ndix (MC68000 CPU instruction set)iii) an Ans we r Booklet - p rovided by the Faculty
DONOTTURNTHISPAGEUNTILYOURE TOLD TODO SOThis examination paper consists of 7 printed pages Hak Cipta Universit i Teknologi MARA C O N FI D E N TI AL
-
8/12/2019 Ece590 April 2010
2/13
CONFIDENTIAL 2 EE/APR 2010/ECE590/KJE609/416
QUESTION 1a) Refer to the circuit in Fig ureQ a. If the diode is made of Germ anium, calculate:
i) the current\1.i i) the power dissipated in the 4.7kQ and 1.5kQ resistors.iii) the outpu t voltag e, V0.State any assumption(s) made.
1 5 V -
AA/V4.7kQ
V01.5kCL
b)Figure Q1a
Refer to the circuit in Figure Q1b.(8 marks)
i) Calculate the secondary root mean square voltage, V2rms-ii) Sketch the waveform of output voltage, V0. Hence calculate the averagevoltage,iii) If a 500 uF capa citor is conn ected in parallel with the load, sketch the newwaveform of V0. H ence calculate the ripple voltage, V r.State any assumption(s) made.
220 V 1rms50 Hz 6 TransformerTurn ratio10:1 * i 2rms 3 1.5k -o+Figure Q1b
Hak Cipta Universiti Teknologi MARA
(12 marks)CONFIDENTIAL
-
8/12/2019 Ece590 April 2010
3/13
CONFIDENTIAL 3 EE/APR 2010/ECE590/KJE609/416
QUESTION 2FigureQ2showsanemitter stabilized bias circuit.
a)
b)
+o
Vin 1oFigureQ2
ReferringtoFigure Q2,determine the following:i)ii)iii)iv)v)vi)
base current,lBcollector current,l cem itter current,lEbase voltage,VBVCEvoltage dropatRE i, VRE1 (10 marks)ReferringtoFigure Q2andgivenVBE=0.7V perform ACanalysisbydrawingthe ACequivalent circuit and determine thefollowing:) rei) input impeda nce,Zini i) output impeda nce,Z0v) voltagegain,Avv) currentgain,AjUse r0=oforyour analysis. (10 marks)
Hak Cipta Unive rsi t i Tek nolo gi MARA CONFIDENTIAL
-
8/12/2019 Ece590 April 2010
4/13
CONFIDENTIAL 4 EE/APR 2010/ECE590/KJE609/416
QUESTION 3
a) Referring to Figure Q3a, a bipolar junction transistor (BJT) is used to switch a motoron and off in response to switch Si closing and opening. The BJT is specified with(3=100.i) Calculate the base current for both on and off condition.ii) Calculate the voltage between collector and emitter terminal when switchedon.i ii) Calculate the power dissipated in the load and the BJT whe n switched on.
RLi 5kcr
5 VV^wvr
RB5.6kQ20V
Figure Q3a
b) Convert the following numb ers into the required number system .i) 73.03125 1 0to binary num bering system,ii) 777.7 1 6to decimal numbering system,iii) 1 01 01 . 01 12to decimal numbering system.
(12 marks)
(8 marks)
Hak Cipta Universiti Teknologi MARA CONFIDENTIAL
-
8/12/2019 Ece590 April 2010
5/13
CONFIDENTIAL EE/APR 2010/ECE590/KJE609/416
QUESTION 4a) Briefly explain the function of a decoder and a multiplexer.
(4 marks)b) Obtain the Boolean expression of A and B for the combinational logic circuit inFigure Q4 b below.
W -x- J>Y
^ >
\ >
A
o- BFigure Q4b
(6 marks)c) Construct the Karnaugh map for function F(x,y,z) = 1 (1 ,4,5,6). W rite the algebraic
expression for the minimized function. Hence, draw the circuit diagram thatimplements the func tion with logic gates.(10 marks)
QUESTION 5a) With reference to MC 68000 processor, briefly describe the difference betweenaddress register a nd data register in terms of data size and func tion.
(4 marks)b) Indicate the change s in the associated register(s) and mem ory location(s) afterexecuting each of the following instructions. Use the initial values given inTable Q5b , for each operation.
Hak Cipta Universi t i Teknologi MARA CONFIDENTIAL
-
8/12/2019 Ece590 April 2010
6/13
CONFIDENTIAL 6 EE/APR 2010/ECE590/KJE609/416
Table Q5b
ComponentsData reg isters: D1D2D3Address registers: A1A3Memory locations: $2000$2001$2002$2003$2004$2005$2006$2007
Contents$2342A1B3$000000B3$0010FFF5
$2002$2006$A9$F2$43$54$D6$E5$C3$98
i) ROL.W 4, D1ii) AND .B $33, D3iii) MO VE.W (A3), D3iv) SUB.B (A1), D2(6 marks)
c) Figure Q5c shows the MC68230 Pl/T connection to LED and switches. Draw theflowchart and write a MC68000 CPU assembly language program that will turn ONLED1 , when switch SW 1 is pressed and turn ON LED2 when switch SW2 ispressed.Otherwise, both LEDs will be turnedOFF.
Hak Cipta Universiti Teknologi MARA CONFIDENTIAL
-
8/12/2019 Ece590 April 2010
7/13
CONFIDENTIAL EE/APR 2010/ECE590/KJE609/416
+5V
Figure Q5c (10 marks)
END OF QUESTION PAPER
Hak Cipta Universiti Teknologi MARA CONFIDENTIAL
-
8/12/2019 Ece590 April 2010
8/13
CONFIDENTIAL APPENDIX (1) EE/APR 201 0/ECE590/KJE609/416
M o t o r o l a MC 68000 CPU I n s t r u c t i o n S e t
codesInstruction DescriptionCABCD
ADD
ADDAADDIADDQADDX
AND0ANDI0ASL
ASR
BCHG
BCLRBSETBSR
BTST
CHKUCLR0CMPCMPA
Add BCD with extend
ADD binary
ADD binary to AnADD ImmediateADD3 bit immediateADD extended
Bit-wise AND
Bit-wise AND with ImmediateArithmetic Shift Left
Arithmetic Shift RightConditional Branch
Test a Bit and CHanGe
Test a Bit and CLeaRTest a Bit and SETBranch to SubRoutine
Bit TeST
CHecK Dn Against BoundsCLeaRCoMPareCoMPare Address
AssemblerSyntax
Dx, Dy
D a t aS i z e
-(Ax) ,-(Ay)Dn,,Dn,An#x,
#,Dy,Dx
-(Ay),-(Ax),DnDn,#,
#,DyDx,Dy
BWL
-WLBWLBWLBWL
BWL
BWLBWL
Bcc.S Bcc.W Dn,#,
BSR.S BSR.W
Dn,#,,Dn
,Dn,An
BWLBW-
B-L
B-LB-LBW-
B-L
- W -
BWLBWL-WL
C o n d i t i o nX N Z V
U U
-k k
k -k -k
k
* 0
-k -k -k k
k -k k k
- U U- 0 1 0_ * * *_ * * *
Hak Cipta Universi t i Teknologi MARA C O N F I D E N T I A L
-
8/12/2019 Ece590 April 2010
9/13
CONFIDENTIAL APPENDIX (2) EE/APR 2010/ECE590/KJE609/416
CMPICMPMDBccDIVS0DIVU0EOR0EORI0EXGEXT0ILLEGALJMPJSRLEALINKLSL
LSR*MOVE0MOVEIMOVEI
CoMPare ImmediateCoMPare MemoryLooping InstructionDivide SignedDivide UnsignedExclusive ORExclusive OR ImmediateExchange any two registersSign EXTendILLEGAL-Instruction ExceptionJuMP to Affective AddressJump to SubRoutineLoad Effective AddressAllocate Stack FrameLogical Shift Left
Logical Shift RightBetween Effective AddressesTo CCRTo SR
#, BWL{Ay)+,(Ax)+ BWL
DBcc Dn, -W-,Dn -W-,Dn -W-Dn, BWL
#, BWL
-k k k
* *
* k *
* * 0* * 0
Rx,RyDn
on ILLEGAL
,AnAn,#
Dx,Dy#,Dy
; ,,CCR,SR
L-WL
L
BWL
BWLBWL-w--W-
------*
- *
-II
*-----*
r
II
~-~~-k
**II
0-----0
00II
MOVE From SRMOVE USP to/from Address Register
MOVEA MOVE AddressMOVEM MOVE Multiple
MOVEP MOVE Peripheral
MOVEQ MOVE8 bitimmediate0 Hak Cipta Universi t i Teknologi MARA
SR, -W-USP,An --LAn,USP,An -WL
, -WL,
Dn,x(An) -WLx(An),Dn#,Dn L - * * 0
C O N F I D E N T I A L
-
8/12/2019 Ece590 April 2010
10/13
CONFIDENTIAL APPENDIX (3) EE/APR 2010/ECE590/KJE609/41 6MULS0MULU0NBCD*NEGNEGXk
NOPNOT0OR0ORI0PEARESETROL
RORROXL*ROXRRTEIRTRIRTSSBCD
SecSTOPISUB
MULtiply SignedMULtiply UnsignedNegate BCDNEGateNEGate with extendNo OPerationForm one's complementBit-wise OR
Bit-wise OR with ImmediatePush-Effective AddressRESET all external devicesROtate Left
Rotate RightROtate Left with extendROtate Right with extendReTurn from ExceptionReTurn and RestoreReTurn from SubroutineSubtract BCD with extend
Set to -1 if True, 0 if FalseEnable & wait for interruptsSUBtract binary
SUBA SUBtract binary from AnSUBI SUBtract ImmediateSUBQ SUBtract3 bit immediateSUBX SUBtract extended
Hak Cipta Universiti Teknologi MARA
,Dn,DnNOP
,DnDn,,RESET
#,DyDx,Dy
-W--w-B BWLBWL
BWLBWL
BWL L
BWL
BWLBWLBWL
RTERTRRTS
Dx,Dy-(Ax),-(Ay)
#Dn,,Dn,An#x,
,Dy,Dx
B ~
B
BWL
-WLBWLBWLBWL
_ * * Q
- 0U U
k k -k -k
o- 0
_ 0
- * * 0
- * * 0* * o* * * QI I I II I I I
* u * u
I I I I* * * *
k -k k k
k -k k
k k k
CONFIDENTIAL
-
8/12/2019 Ece590 April 2010
11/13
CONFIDENTIAL APPENDIX (4) EE/APR 2010/ECE590/KJE609/416
SWAP0TAS0TRAPTRAPVTST0UNLK
SWAP words of Dn
Test & Set MSB & Set N/Z-bitsExecute TRAP ExceptionTRAPV Exception if V-bit SetTeST for negative or zeroDeallocate Stack Frame
-(Ay),-(Ax)Dn
#
TRAPVAn
BWL
* Q* * 0
Symbol Meaning* Set according to result of operationNot affected0 Cleared1 Set -U Outcome (state after operation) undefinedI Set by immediate data
Effective Address Operand Immediate data Assembler label TRAP instruction Exception vector (0-15) MOVEM instruction register specification list LINK instruction negative displacement... Same as previous instruction
Addressing Modes SyntaxData Register Direct DnAddress Register Direct AnAddress Register Indirect (An)Address Register Indirect with Post-Increment (An)+Address Register Indirect with Pre-Decrement -(An)Address Register Indirect with Displacement w(An)Address Register Indirect with Index b(An,Rx)Absolute Short wAbsolute Long 1Program Counter with Displacement w(PC)Program Counter with Index b(PC,Rx)Immediate #xStatus Register SRCondition Code Register , CCRLegendDnAnbw1
Data RegisterAddress Register08-bit constant16-bit constant32-bit constant
n i s 0 - 7 )n i s 0 - 7 )
Hak Cipta Un iversiti Teknologi MARA C O N F I D E N T I A L
-
8/12/2019 Ece590 April 2010
12/13
CONFIDENTIAL AP PE ND IX 1 5) EE/ APR 2010/ECE590/KJE609/416
x 8-, 16-, 32-bit constantRx Index Register Specification, one of:Dn.W Low 16 bits of Data RegisterDn.L All 32 bits of Data RegisterAn.W Low 16 bits of Address RegisterAn.L All 32 bits of Address Register
Condition Codes for Bcc, DBcc and Sec Instructions,Condition Codes set after CMP D0,D1 Instruction.
RelationshipDl < DODl DODl >= DOEqual
UnsignedCS - Carry Bit SetLS - Lower or SameEQ - Equal (Z-bit Set)NE - Not Equal (Z-bit Clear)HI - Higher thanCC - Carry Bit Clear
SignedLT - Less ThanLE - Less than or EqualEQ - Equal (Z-bit Set)NE - Not Equal (Z-bitGT - Greater ThanGE - Greater than or
(Overflow)PL - PLus (N-bit Clear)VC - V-bit Clear (No Overflow)RA - BRanch Always
MI - Minus (N-bit Set)VS - V-bit Set
DBcc Only
Sec Only
F - Never Terminate (DBRA is an alternate to DBF)T - Always Terminate
SF - Never SetST - Always Set
Partial MC68000 Pl/T registersRegisterPort General Control RegisterPort A Data Direction RegisterPort B Data Direction RegisterPort C Data Direction Register
Port A Control RegisterPort B Control RegisterPort A Data RegisterPort B Data R egisterPort C Data Register
AbbreviationPGCRPADDRPBDDRPCDDRPACRPBCRPADRPBDRPCDR
The PGCR Control format
Hak Cipta Un ivers i t i Tekno log i MA RA CONFIDENTIAL
-
8/12/2019 Ece590 April 2010
13/13
CONFIDENTIAL APPENDIX (6) EE/APR 2010/ECE590/KJE609/41 6b 5 b 4 b 3 b 2
M O D E H 3 4 H 1 2 H 4 H 3 H 2 H 1
OO : M o d e O i j >U n i d i r e c t i o n a l8 b i ts0 1 : M o d e 1 i = >U n i d i r e c t i o n a l1 6 b i t s1 0 : M o d e 2 iB i d i r e c t i o n a l8 b i t s1 1 : M o d e 3 iB i d i r e c t i o n a l1 6 b i t s
( P o r t s a n d b i t si n d i v i d u a l l yp r o g r a m m a b l e )( P o r t s A a n d Ba r e t o g e t h e ri n p u t o r o u t p u t )( B a c h p o r t i n p u tf o r r e a d a n d o u t p u tf o r w r i t e )
( P o r t s A a n d B a r et o g e t h e r i n p u t f o r r e a da n d o u t p u t f o r w r i t e )
O : L o w a c t i v e1 : H i g h a c t i v eO: D i s a b l e H 3 4 / H 1 21 : E n a b l e H 3 4 / H 1 2
The PACR Contro l form atb 6 b O
S U B M O D E H 2 C O N T R O L H 2I N T
I TO O : S u b m o d e OD o u b l e - b u f f e r e di n p u t0 1 : S u b m o d e 1D o u b l e - b u f f e r e do u t p u t1 X : B i t I / O
O X X : H 2 i n p u t1 0 0 : H 2 o u t p u tn e g a t e d1 0 1 : H 2 o u t p u ta s s e r t e d1 1 0 : H 2 h a n d s h a k e
m o d e
H 1s v oS p e c i f i e sH 1 s t a t u s
O : H 1 i n t e r r u p t a n dD I V l / \ r e q u e s td i s a b l e d1 : E n a b l eO : H 2 i n t e r r u p t d i s a b l e1 : H 2 i n t e r r u p t e n a b l e
1 1 - 1 : H 2 p u l s em o d e
Hak Cipta Universiti Teknologi MAR A CONFIDENTIAL