-ECE533F - Power Electronics

Test

Lecturer - O. Trescases

Date - Wednesday, Oct. 26, 2011

Duration: 90 minutes

1. Answers should be written in pen. Warning: answers written in pencil are acceptable but

may be considered ineligible for remarking.

2. The marks for each question are indicated within brackets [ ]. Show your work: answers

without justification will not receive full marks! Write your numerical answers in the

boxes.

3. Use back side of sheets if necessary. Extra sheets are also provided at the end.

4. Aids: calculator only. (Any calculators including programmable are allowed).

5. Unless otherwise stated, you may use the small-ripple approximation

Question Mark

1 /8

2 110

3 112

4 112

BONUS

Total /42

Last Name:

First Name:

Student #:

Page 1 of15

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Question 1:

[8 marks] Consider the dc-dc converter shown below. All components are ideal, with the exception of

the diode which has a voltage drop of VD = 1 V in the on-state. Vg = 24 V. You may assume that the

converter operates in CCM.

+

+ L2 v R C2

T l L 2... - --I

on

c(t) off

a) [5 marks] Using the small-ripple approximation, find an expression for the steady-state output

v ltage, V. Draw a steady-state equivalent model of the non-ideal converter that includes a dc

tr nsformer.

b) [3 marks] Assume that the converter is operated in closed-loop, where D is adjusted automatically

to maintain V= 48 V. Find the efficiency at the rated output current of l out = VIR = 2 A.

Bon s [1 mark]: Sketch the schematic of another converter that achieves the same idea conversion

ratio sing a single inductor and a single capacitor.

+RO\V\ I\j5.g;

, b (

J)' (-\1

v

Page 2 of 15

=-0 V,-, - \0 ) ~ J) VJ

Last Name: _____ _

11 t)t;.~'" T OiA +- . v]) '+>O~+-

.-;-\--) -t -\ ?! t:>

Last Name: -------

Question 2:

[10 marks] Consider the converter shown below. You may assume that all components are ideal and

that D is controlled in closed-loop to maintain a regulated output voltage of V = lOO V. Vg = 24 V,is =

400 kHz, 0.2 A < lout < 2 A, where lout = VIR.

e(t)

~

+ Vg v

R - C -

T + -I - ----t;:; Ts -I t

DTs l+- on e(t)

off

(a) [3 marks] Find the value of L such that the converter operates in CCM for lout> O.SA.

(b) [4 marks] Sketch the value of D versus lout for 0.2 A < lout < 2 A. What is the minimum value of D

over this range?

(c) [3 marks] Find the minimum value of C such that the output voltage ripple L1 VIV < 2 % at lout =

0.2 A. t-O'IV- :r Ij So@, :

0-) T\{\~t-t~ kLk--

t -.. 80. -=i o/C)

i\ ·'l - "hI V~ -r ....:.-t

Last Name: --------

Bon s [2 mark]: Assume that the converter is constructed with non-ideal semiconductor components. Do you expect this converter to suffer from reverse recovery losses due to the diode when operating in DCM? Justify your answer with a suitable diagram.

r Q (t;;I'v'" .r;

CD 'Dc.~ ~()k dj r'loZk. ~.(A) c;"-\1

I . V t-A~ Fe 7 ",. ) 'r-€.a cS \ I. \, •• ) ,,-Q ct.. ~i "Dr"C .~ !('~ ;oe ~'el~'J (-v...../~t-

\

II-J 'I'

1 ---Page 5 of 15

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Question 3:

[12 arks] This question includes four unrelated parts. Justify your answers to obtain full marks.

(a) [3 marks] An from the datasheet of a commercially available power MOSFETs is shown below. Draw the gate-charge curve for this MOSFET while labelling all relevant quantities. What is the minimum drive voltage that you would use for the MOSFET in a practical application?

" 3V _/

,

J:>r 'AQ..

:.N eJ} '\ 0 tJ ~ 0a-~

o 1.0 o\J'4.- 4V ( lrRt~~)

~ \-. ov-Xd (~ ~V\r t1, ~ '-I

«I: ~ ..,.

I Q3~ \ ~jJ... -\ B?j IRFR/U4105PbF International

I"R Rectifier

Electrical Characteristics @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions

V(BR)DSS Drain·to-Source Breakdown Voltage 55 - - V VGS = OV, ID = 250fJA ~V(BR)DSS"nJ Breakdown Voltage Temp. CDefficient - 0.052 - V/oC Reference to 25°C, ID = 1mA RDS(on) Static Drain-ta-Source On-Resistance - - O~ VGS - 10V, ID = 16A @ VGS(th) Gate Threshold Voltage 2.0 - 114.0 IJ V Vos - VGS, ID = 250fJA gfs Forward Transconductance 6.5 - ~ S Vos - 25V , ID - 16A0

IDSS Drain-ta-Source Leakage Current - - 25 Vos = 55V , VGS = OV - - 250 fJA Vos = 44V, VGS = OV, TJ = 150°C

IGSS Gate-to-Source Forward Leakage - - 100 VGS = 20V Gate-to-Source Reverse Leakage -100

nA VGS = -20V - -

Qg Total Gate Charge - - 34 10 = 16A Qgs Gate-to-Source Charge - - 6.8 nC Vos = 44V Qgd Gate-to-Drain ("Miller") Charge - - 14 VGS = 10V, See Fig. 6 and 13 @0 Idron) Turn-On Delay Time - 7.0 - Voo = 28V tr Rise Time - 49 - ID = 16A

ns Id(off) Turn-Off Delay Time - 31 - RG = 18Q tf Fall Time 40 Ro = 1.8Q, See Fig . 10 @0

Between lead, 0 Lo Intemal Drain Inductance - 4.5 - nH

G~ 6mm (0.25in.) Ls Intemal Source Inductance - 7.5 - from package and center of die contact@ s

Ciss Input Capacitance - 700 - VGS - OV Coss Output CapaCitance - 240 - pF Vos = 25V Crss Reverse Transfer CapaCitance - 100 - f = 1.0MHz, See Fig . 50

Page 6 of 15

Last Name: ______ _

[3 arks] Using a figure, briefly explain the concept of safe operating area (SOA) for a power

MO FET.

o \J c·.-t' J

I

L..~1

\ r 0.

( Oo/'v \-~ 'r ~ 4. \/V 'j k -e.A CM.. v ~f / I; a-P I-rt< C~'0.-r~ r~ Lv:) ~

Page 7 of 15

Last Name: --------

(b) [4 marks] A measured switching waveform for a Si-IGBT is shown below. Is this the turn-on or

turn-off process? Sketch the power dissipation versus time below the graph using the same time

scale. What is the peak power in the device and the switching energy (per cycle).

1200 12

1000 10

- 800 8 en -(5 600 > -6 ~ - I-m C) 400 4 ~

> 200 2

0 a

-200 -2

-200 -150 -100 -50 0 50 100 150 200

Time (ns)

f -::f-kW $w 0:; A\"€.0..

))"DIAS, ,i kvv . -/

\ ),

Last Name: ______ _

(c) [2 marks] Several power MOSFET packages were discussed in class. What effects does the

packaging have on the device performance?

- f~cJle--0cr- 1..,-\\r-~

~" clu. c...J...G.. it Z 0- V'- C9

~)

( Q u..'~ \:

(' ~~* '\ Page 9 of15

I

'])0 (0 c., r +- 'c.

I .0

Last Name:

Question 4:

[12 arks] The block diagram of a commercially available buck converter IC (MIC28500) is shown

below. The relevant component parameters are shown on the diagram. The converter operates in PWM

mode with a regulated output voltage of VOUT = 3.3V for 30 V < V/N < 75 V. You may assume that the

internal supply voltage VDD is derived from V/N using an intemallinear voltage regulator (not shown

on t e diagram).

PVOO

Voc VOD 5Vct-....... ....;..;;. .... -.--t UVLO

2 7PF=!=

lOOk

D1

MIC28500

Control L09C Timer

Sofr-S lar1

FS 10010;

100.

~~ ~ r-*"",;.,;.,..;..-t-~~ ....... -----tl30V to 75V

R l eN

..... 10_10. ...... " : I

R2 3 24k

Figure 1. MIC28500 Block Diagram

a) [3 marks] What is the purpose of the capacitor ex and diode DJ? How should the capacitance value be chosen (ie : what is a lower bound on Cx)?

. l(f~ \0 . ':)..\..

Last Name: -------

b) [4 marks] The measured steady-state waveforms for the converter are shown below. Accurately

determine the following parameters: is, L, CaUl, and VIN (you may assume the converter is ideal for this part only).

VOUT

(20mV/div) [[; .i • ... t

, . •• • • -.1

, . ., ,

1

, .. .. ~

~ e(t) ....... IIIHI ........... _,.. ........... ....-...

~ --

fL (2Ndiv)

~ , ~/ 5, J~

~T':.o.oW~

:;:' -IS ~ 7-.:]g~H~ - -

I O"L-I.. L ~ Vt'~ \j \'v, "-r -~ ::

E S·kv,,,,,1~ CoL-.J.

(', -=:. C bV ')

?->q. b V

:) T:. . (~I :: ... b ~ L-

1-\

lS. YfH f

1 T '- Page 11 of 15

Last Name:

c) [5 marks] Assume the same value of Is and Vin from part b). The measured efficiency of the buck converter and the characteristic curves for the two power MOSFET, MHs and MLs, are

shown below. You may neglect all losses except:

1) Gate-drive losses due to the finite gate-charge of MHs and MLs, Pgale 2) Conduction losses in MHs and MLs, P eond 3) Controller power consumption, P eonlrol 4) Switching losses in MHs and MLs, P sw.

The controller circuits (excluding the gate-drivers and the linear regulator) consume

P eonlrol = 75 m W from VJN, regardless of the output current value.

Using the measured efficiency at lout = 0.5 A, VOUI = 3.3 V, estimate the total switching losses, P sw, at

loul = 0.5 A. (hint: calculate all other known loss components).

'j) .sIN

:::

YStAJ --

. _---- 0;. :::-7~ . . .

~~ k ~\.'~_-'l.J.~

VDD -= 5V ;:;::==-

f· \f ~D

"

'1 i

''? \ ~ L S. • J I

2, S nC

r--- '1 -'j" :

I \ I \

~\ V DO \

}) . (J. ",,3 ~ 12-tNo. H c;) .1

f (-OSS Iy .-, :~" N' \'(.J> ) I J r - IV .~ .-

550 - ( 102, + ,~. '5 + =i-S ) ( IN\ vJ

5~.s Page 12 of 15

• .,A ~.,~

I

so! ::; ~ --Last Name: ------

100

90 Vour=

80 -~ 70 0 ->-t) z 60 w

50 ~ u. 40 u. w

30

20

10

o 6.~ 1 2 3 4 5 6 OUTPUT CURRENT (A)

Page 13 0[15

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~~~

Last Name:

Measured Data for M HS :

100

$ 'E ~ ;:)

(.)

~ 10 :;

0 (/)

B c .~

3 0 .9

vas TOP t5V

tOY B.OV 7.0V ~ ~ I ~ .... 6.0V (f

" 5.5V -5.0V , eonOM 45V

UI .~

~ v

~ I .. VJlI

~ IZiI" ~ V .-' i-'" ,

V ",,'"

.5

1 30~s PULSE WiDWI Tj = 25°C I I I 1

16 .1

VDS~80V 10= 1.6A t-VOS-50V ~ VOS=20V ~ ~

;I'

/~ V

~~ V ~ V .... ~

~ V L ~ o o 2 3 4 5 6

QG Total Gate Charge (nC)

0.1 10 100

V DS' Drain-to-Source Voltage (V)

Measured Data for MLS :

lOCO VGS .... _

TOP 15V 10V 8.0V

--

~ 7 ov l-l+l-~I-HH-H+I--++t+ttHl Ql

20

16

~ 100 ~~§~~·~~~dlllll~911 sv ~ ~ BOTTOM~'~~ .- : : V i 12 ~ ~

S ~. r'~~'''';;;_ ~4--I-H+!t-..,..-rn- S

~ "ifI~'~Ii~~;m~ill ~ g I' i==== E f- c'8 S .9 '0 ~:ttj;j#~~.5y Hlt-- t-t--H-tiiil ~ 4

- hi - _. t--- f- 20/.15 PULrE,WiTID:~';1 > /V' Tj = 250C I I II I ,

8

o 0.1 10 100

VDS. Orain·to-Source Voltage 0/)

Page 14 of 15

10= 18A I

VOS=80V "" VDS=50V I" '''''_

VDS=20V

~ ~ l/

~

/ j

~ o 10 20 30 40 50

QG Total Gate Charge (nC)

7

60

Page 15 of15