8/12/2019 ECE471 WIN12 Design Procedure MIDTERM2

1/2

Here is the design procedure for the midterm 2:

1) calculate td(max) -- either low->high; high->lowFirst calculate the worst-case delay of the FA, from either low->high, or high-

>low. This now is annotated as the FA delay.

2) t(cycle) = 2*td(max)Set the clock cycle time to be equal to 2*td(max). Hence, simulate the FA

assuming that the clock frequency is 1/t(cycle).

3) measure Iavg*Vdd*2td(max) (static leakage)Dont switch anything with the FAkeep all inputs stable. Then, measure the

Iavg current in Vdd. Hence, the energy dissipated during a single cycle of

1/t(cycle) => Ecycle (static) = Iavg * Vdd * t(cycle). This is your static leakageenergy consumed in a single t(cycle) period.

4) measure Iint*Vdd*2*td(max) (BOTH dynamic + static energy together)Now, set your clock period of your FA to t(cycle) = 2*td(max). Use Iint,

integrating ALL the current from the beginning of the clock to the end of

t(cycle). Ecycle (total) = Iint(for entire t(cycle)) * Vdd. This is your TOTAL

energy/computation, including both your static leakage energy and your

dynamic energy together.

5) rise-time issue: use different inverter to drive D-FF clockOne problem with the simulations is that the rise/fall time of the input and

the clocks can greatly affect the dynamic current through Vdd. i.e. fast rise

times result in large capacitive switching. I suggest using another inverter as

a buffer to isolate your fast clock edge from the real input(s) to your D-FF.Make sure to put this separate inverter not on the same VDD as the VDD you

are measuring, however. For example, a previous student Maggie Watkins

suggested making the rise/fall time of the clock/data equal to 1/10 of the

clock period.

6) Vt process variability issueThe second part suggests to change vt of the FA, to emulate process

variability. The real way people do this in industry is to run Monte Carlo,which randomizes across a Gaussian distribution the possible effects that

might occur, and run 100s/1000s of iterations in the hopes of finding howsensitive the design is to failure across a 3-sigma event.

8/12/2019 ECE471 WIN12 Design Procedure MIDTERM2

2/2

For this simple assignment, the easiest way to do this is to change the vt of

the devices. This will be a worst-case simulation, but simplifies thingsbecause you do not need to run Monte Carlo.

Put two voltage sources in series with the transistors in the FA, both for the

NMOS and the PMOS. Make this 1-sigma for each, and effectively makeseach PMOS/NMOS seem much slower (for example, a 50mV higher Vt for

each transistor). Note that 1-sigma for 25um technology will be substantially

different than 1-sigma for 65nm-CMOS. Assume AVT=4mV/um.

You can ignore the gate length variation for this portion.