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ECE 260B CSE 241A Power Consumption 1 http:/ /vlsicad.ucsd.edu
ECE260B CSE241AWinter 2005
Power Consumption
Website: http:/ /vlsicad.ucsd.edu/courses/ece260b-w05
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ECE 260B CSE 241A Power Consumption 2 http:/ /vlsicad.ucsd.edu
VLSI Design MetricsArea / cost
Performance
Power consumption
Reliability
Figure courtesy, D. Singh
l Manufacturing yieldl Signal integrity (e.g., crosstalk, supply voltage drop, etc.)l Logic correctness / acceptable performance variation under
process, operating condition variationsl Expected lifetime (due to eletromigration, soft-error, peak current,
etc.)
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ECE 260B CSE 241A Power Consumption 3 http:/ /vlsicad.ucsd.edu
Power Dissipation
P6Pentium proc
486386
2868086
808580808008
4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Pow
er
(Wat
ts)
Lead Microprocessors power continues to increase
Courtesy, Intel
Power delivery and dissipation will be prohibitive(?)
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ECE 260B CSE 241A Power Consumption 4 http:/ /vlsicad.ucsd.edu
Power Density
400480088080
8085
8086
286 386 486Pentium proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Pow
er
Densi
ty (W
/cm
2)
Hot Plate
NuclearReactor
RocketNozzle
Power density too high to keep junctions at low temp(?)Courtesy, Intel
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ECE 260B CSE 241A Power Consumption 5 http:/ /vlsicad.ucsd.edu
Low Power Design DriversConsumer products
l Affects expected battery lifetimel Slow development of battery technology (90-110 Watt-hrs/Kg)l Low power reducing energy consumption
High performance designsl Increasingly expensive packaging and cooling strategies
- Size, weight, heat sinks, - Air, liquid cooling mechanism
l Supply voltage drop l Temperature
- Every 10OC increase in operating temperature roughly doubles a components failure rate
l Low power reducing peak power consumption for less thermal effects, better signal integrity and reliability
- Signal integrity / logic correctness / acceptable performance variation / design lifetime
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ECE 260B CSE 241A Power Consumption 6 http:/ /vlsicad.ucsd.edu
Low Power Design Metrics
Energy efficiency in Joulesl Energy = power * delay (Joules = Watts * seconds)l Affects battery lifetime
Average power consumption in Wattsl Results in thermal effectsl Sets packaging limits (50W / cm2 ? 120W total ?) ($1/Watt ?)
Worst case supply currentl Simultaneous transistor switchingl Supply voltage drop performance degradationl Maximum device current device lifetimel Electromigration wire lifetime
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ECE 260B CSE 241A Power Consumption 7 http:/ /vlsicad.ucsd.edu
Power Versus Energy
Watts
time
Power is height of curve
Watts
time
Approach 1
Approach 2
Approach 2
Approach 1
Energy is area under curve
Lower power design could simply be slower
Two approaches require the same energy
Slide courtesy of Mary Jane Irwin, PSU
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ECE 260B CSE 241A Power Consumption 8 http:/ /vlsicad.ucsd.edu
Low Power Design Objectives
Worst case supply current IAverage power P = I V
l Maximum cycle powerl Maximum N-cycle powerl Maximum sustainable power
Energy E = P dtEnergy-delay products
l Simultaneous power reduction and performance optimization
Usually to reduce average power under timing constraints
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ECE 260B CSE 241A Power Consumption 9 http:/ /vlsicad.ucsd.edu
Outline
Problem statementPower dissipation componentsPower estimationOptimization techniques
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ECE 260B CSE 241A Power Consumption 10 http:/ /vlsicad.ucsd.edu
Static CMOS Gate Power
Power dissipation in static CMOS gate: 3 components
Dynamic capacitive (switching, useful) powerl Still dominant component in current technologyl Charging and discharging the capacitor
Crowbar current (short-circuit power)l During a transition, current flows through both P and N
transistors simultaneously for a SHORT period of timel Slow transitions worsen short-circuit power
Leakage (useless power) currentl Even when a device is nominally OFF (VGS=0), a small amount of
current is still flowingl With many devices, can add up to hundreds of mW
Slide courtesy of Mary Jane Irwin, PSU
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ECE 260B CSE 241A Power Consumption 11 http:/ /vlsicad.ucsd.edu
Reducing Dynamic Capacitive (Switching) Power
Pdyn = CL VDD2 P01 f
Capacitance:Function of fan-out, wire length, transistor sizes
Supply Voltage:Has been dropping with successive generations
Clock frequency:Increasing
Activity factor:How often, on average, do wires switch?
Slide courtesy of Mary Jane Irwin, PSU
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ECE 260B CSE 241A Power Consumption 12 http:/ /vlsicad.ucsd.edu
Crowbar (Short-Circuit) Current
Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting
When VTN < VIN < VDD+VTPl Both transistors are ONl Current flowing directly from
VDD to VGND is crowbar current
Usually not a problem, e.g.,l P is ON strongly (LIN but with
small VDS if at all)l N is barely ON
time
V ITransition
RNCL
RP
Slide courtesy of Ken Yang, UCLA
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ECE 260B CSE 241A Power Consumption 13 http:/ /vlsicad.ucsd.edu
Leakage (Inactive, Useless) PowerThree sources of leakageThe dominant is the Source-to-Drain leakage current
l Even when VGS = 0, a small amount of charge is still present under the gate
l Exponentially related to the gate (and S/D) voltage
Source/Drain are junctions and some amount of reverse bias, IS is present
l Typically much smaller than S/D leakage
Gate tunneling leakagel When tox is only 5-10atoms, easy for tunneling current to flowl More of an issue sub 0.10-m technology
I DWL
exp q V GSV T /nkT
Slide courtesy of Ken Yang, UCLA
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ECE 260B CSE 241A Power Consumption 14 http:/ /vlsicad.ucsd.edu
2001 ITRS Projections of 1/ and Isd,leak for HP, LP Logic
100
1000
10000
2001 2003 2005 2007 2009 2011 2013 2015
Year
1/
(GH
z)
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
Isd
,leak (A/
m)
`
Isd,leakLow pwr
Isd,leakHigh Perf.
1/High Perf.
1/Low Pwr
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ECE 260B CSE 241A Power Consumption 15 http:/ /vlsicad.ucsd.edu
Projections for Low Power Gate Leakage
Need for high K driven by Low Power, not High Performance
0.0001
0.001
0.01
0.1
1
10
100
1000
10000
100000
2001 2002 2003 2004 2005 2006 2007 2010 2013 2016
Year
J gat
e (n
orm
aliz
ed)
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
To
x (n
orm
alized)Simulated Igate, oxy-nitride
Igate spec. from ITRS
Oxy-nitride no longer adequate: high K needed
Tox
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ECE 260B CSE 241A Power Consumption 16 http:/ /vlsicad.ucsd.edu
Summary: Power and Energy Equations
E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD Ileakage
P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD IleakageDynamic power(~90% today and
decreasing relatively)
Short-circuit power
(~8% today and decreasing absolutely)
Leakage power(~2% today and
increasing relatively)
f01 = P01 * fclock
Slide courtesy of Mary Jane Irwin, PSU
Designers need to comprehend issues of memory and logic power, speed/power tradeoffs at the process (HiPerf vs. LowPower) level,
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ECE 260B CSE 241A Power Consumption 17 http:/ /vlsicad.ucsd.edu
Outline
Problem statementPower dissipation componentsPower estimationOptimization techniques
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ECE 260B CSE 241A Power Consumption 18 http:/ /vlsicad.ucsd.edu
Design Abstraction Levels
BehavioralSynthesis
RTLSynthesis
LogicOptimization
TransistorOptimization
Place & Route
HDL
PowerAnalysis
PowerAnalysis
PowerAnalysis
PowerAnalysis
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 19 http:/ /vlsicad.ucsd.edu
Transistor Level Power Estimation
BehavioralSynthesis
RTLSynthesis
LogicOptimization
TransistorOptimization
Place & Route
HDL
Power Analysis
Current Flows
Circuit Simulation
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 20 http:/ /vlsicad.ucsd.edu
Power EstimationDynamic Analysis
Simulationl requires representative simulation vectors
- Derived by designer- Automatic (Monte Carlo)
Transitor level (PowerMill)l Very accurate l Much faster than SPICE
Gate level (Powergate, DesignPower)l Faster than transistor levell Still very accurate due to good modeling of power dissipation at
cell-level
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ECE 260B CSE 241A Power Consumption 21 http:/ /vlsicad.ucsd.edu
Power Ingredients
VDD
In Out
CL
Dynamic Dissipation
Short-Circuit Currents
Static Dissipation
Pdyn = CLVDDVswf01
Psc = VDDIsc
Pstat = VDDIleakISC
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 22 http:/ /vlsicad.ucsd.edu
Transistor-Level Power Estimation
Spice is the reference, but too slowCommercial tools claim to be within 10% of SPICE
accuracy and up to 1000X faster
I
tP= 1
T0
T
i t v t dt
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 23 http:/ /vlsicad.ucsd.edu
Timing Simulation
Vdd
out1 out2in
out3
i(Vdd)
in
out1
out2
out3
Vdd-Vth
Uses simplified (table-lookup) transistor model Handles leakage, direct path, and reduced swing
Up to 2 orders of magnitude faster than SPICE
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 24 http:/ /vlsicad.ucsd.edu
Switch-Level Simulation
A
BX
F
Cap
(fF/b
it)
Sample
0102030405060708090
100
0 10 20 30 40 50 60
IRSIMSPICE
Up to 3 Orders of Magnitude Faster than Circuit Accurate for Dynamic Power Unreliable on leakage and direct path currents
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 25 http:/ /vlsicad.ucsd.edu
Perspective on accuracy and speed
Comparison between circuit simulation (SPICE)and timing or switch analysis
Adder Shift Register% Error Speedup % Error Speedup
Timing 6 15 7 3.7Switch 27 60 4 22
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 26 http:/ /vlsicad.ucsd.edu
Transistor Level Power Estimation Tools
PowerMill Epic
Star-ADM Avant!
LSIMAnalyst
MentorGraphics
Mixed analog/digital simulation
Analytic closed-form model
Mixed transistor/gate simulation
Series-Parallel Switch algorithm
Mixed transistor/gate simulation
Piecewise linear model
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 27 http:/ /vlsicad.ucsd.edu
Design Abstraction Levels
BehavioralSynthesis
RTLSynthesis
LogicOptimization
TransistorOptimization
Place & Route
HDL
PowerAnalysis
PowerAnalysis
PowerAnalysis
PowerAnalysis
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 28 http:/ /vlsicad.ucsd.edu
Gate-Level Power Estimation
Dynamic Switching Power (Isw) [70-90%]
Also referred to as capacitive power
Internal (Short-Circuit) Power (Iint) [10-30%] Also referred to as short circuit power
Static Leakage Power (Ileak) [< 1%]
Sub-threshold leakage dominates, some due to leakage substrate
InputTransition
V
IntISWI
N
LeakIiC
GND
Complete power model provides infrastructure for analysis and optimization
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 29 http:/ /vlsicad.ucsd.edu
Gate-Level Power Estimation
state of the gate input slope output load temperature fabrication process
toggle rate
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 30 http:/ /vlsicad.ucsd.edu
Design Abstraction Levels
ToggleRates
BehavioralSynthesis
RTLSynthesis
LogicOptimization
TransistorOptimization
Place & Route
HDL
ProbabilisticAnalysis Simulation
PowerAnalysis
Simulationwith integratedPower Analysis
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 31 http:/ /vlsicad.ucsd.edu
Simulation Based Power Estimation
Problems:l The relationship of power versus primary input probabilities
and activities is acomplicated surface.
l The existing methods use discrete points to approximate such a surface.
- The effectiveness strongly depends on the density of the chosen points.
- The more points one chooses, the more accurate results.- More points directly translate to longer CPU time.
Slide courtesy, Z. Chen, K. Roy
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ECE 260B CSE 241A Power Consumption 32 http:/ /vlsicad.ucsd.edu
Toggle Rate Estimation
Probabilistic Propagationl no input vectors neededl much faster than simulationl less accurate than simulationl glitches?
Simulationl requires representative simulation vectors
- derived by designer- automatic (Monte Carlo)
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 33 http:/ /vlsicad.ucsd.edu
Signal probability and activityl Signal probability - probability of a signal being logic ONE
l Signal activity (transition density) - probability of signal switching
ni(T): the number of switching for i(T) in [ -T/2,T/2]
P i=limT
1TT /2
T /2
i t dt
Ai=limT
ni T
T
Signal Probability and Activity
Slide courtesy, Z. Chen, K. Roy
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ECE 260B CSE 241A Power Consumption 34 http:/ /vlsicad.ucsd.edu
l Normalized activityf : clock frequency
Normalized power dissipation measurel Approximated power dissipation
Cj : node capacitance Aj : node activityl Normalized power dissipation measure
fanout(j) : fanout number at node j
ai=Aif
P avg=12V dd
2 jall nodes C
jAj
= jall nodes
f anout j a j
Power Dissipation in terms of Activity
Slide courtesy, Z. Chen, K. Roy
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ECE 260B CSE 241A Power Consumption 35 http:/ /vlsicad.ucsd.edu
Probability Propagation
Let y = f(x1, , xn) be a Boolean function with independent variables xi, the signal probability of f can be obtained in linear time as follows.
where
are the cofactors of f with respect to x1.
Improve runtime by using a BDD
P y =P x1 P f x1 P x 1 P f x1
f x1= f 1, x 2 , . . . , x n , f x1= f 0, x 2 , . . . , x n
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ECE 260B CSE 241A Power Consumption 36 http:/ /vlsicad.ucsd.edu
Activity PropagationLet y = f(x1, , xn) be a Boolean function with independent variables xi,
the signal activity of f can be obtained in linear time as follows.
where Boolean difference
where is the exclusive-or operation.
A y =i=1
n
P y x i
A x i
y x
= yx=1 yx=0
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ECE 260B CSE 241A Power Consumption 37 http:/ /vlsicad.ucsd.edu
AND gatesp(1) = sp1 * sp2tp(01) = sp * (1 - sp)
Example
sp = 0.5 * 0.5 = 0.25
tp = 0.25 * (1 - 0.25) = 0.1875
Probability Propagation
1/21/2
1/21/2
1/4
1/4
7/16
Propagate
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 38 http:/ /vlsicad.ucsd.edu
Probability Propagation for Basic Gates
Ignores Temporal and Spatial Correlations
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 39 http:/ /vlsicad.ucsd.edu
Probability Propagation Problems
0.50.5
0.75 0.375?0.5!
Problem: Reconvergent Fan-out:
Creates spatial correlation between signals
Becomes complex and untractable real fast
P(X) = P(B=1).(P(X=1 | B = 1)
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 40 http:/ /vlsicad.ucsd.edu
Solution to Reconvergence
b
c
a
0 1
1 0
10
1
0
0.5
0.75
0.375
OBDD
Z = bc + abc
1
0.5
0.250.25
0.125
0.375
Preferred Technique:Ordered Binary Decision Diagrams (OBDDs)
Statistics computed in linear time(but graph size could be exponential)
Other approaches:l super-gatesl computation of correlation
coefficients
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 41 http:/ /vlsicad.ucsd.edu
How to introduce time?
And include glitching effects TOUGH! If one also wants to include spatial effects or be general
Example: Symbolic Simulation Approach (for unit delay)Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 42 http:/ /vlsicad.ucsd.edu
Symbolic Network
Transition Counters
Value of d at time t= 0
Problem: Network can be huge and BDD cannot be created!
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 43 http:/ /vlsicad.ucsd.edu
Probability SimulationUser specifies typical signal behavior at the circuit
inputs using probability waveforms, which is a sequence of values indicating the probability that the signal is high for a certain time intervals, and the probability that the signal takes transition from low to high.
Propagation is very similar to event driven logic simulation
0.5
0.25
0.75
0.0
t1 t2 t3
0.2 0.6 0.01
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ECE 260B CSE 241A Power Consumption 44 http:/ /vlsicad.ucsd.edu
How about sequential circuits?
NextState
Comb.Logic
I0
PS0
PSt
It
Next State Logic introduces temporal correlations
between subsequent samples Either assume that all states have equal probability,
or use statistical Markov chains
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 45 http:/ /vlsicad.ucsd.edu
Gate-Level Power Estimation Tools
DesignPower Synopsys
PowerSim Systems Science
Power_tool Veritools
WattWatcherGate
Sente
Viewlogic
GenashorXpower
POET
Probabilistic based
Simulation based
Asynchronous designs
Simulation based
Simulation based
Simulation based
Simulation based
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 46 http:/ /vlsicad.ucsd.edu
Design Abstraction Levels
BehavioralSynthesis
RTLSynthesis
LogicOptimization
TransistorOptimization
Place & Route
HDL
PowerAnalysis
PowerAnalysis
PowerAnalysis
PowerAnalysis
Slide courtesy, Prof. J. Rabaey, UCB
-
ECE 260B CSE 241A Power Consumption 47 http:/ /vlsicad.ucsd.edu
Power Estimation
Simulation l Monte-Carlo techniquel PowerMill at transistor levell Verilog-XL at gate level
Hierarchical simulationl Architectural/gate/transistor-levell Parameterized power model for each module
Statistical estimationl Signal probability propagation
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ECE 260B CSE 241A Power Consumption 48 http:/ /vlsicad.ucsd.edu
Power Estimation MethodologyRTL library Synthesis
condition
Synthesis P&R
Post-layoutnetlist
PowerCharacterization
PowerMacro-model
database
Power model library generator
Powerlib.vhd Powerlib.v Powerlib.c
RTL design
RTL planning/ mapping
Structure(macro)netlist
Power model inference &Estimation code generation
Enhanced RTL
RTL simulation
Powerreport
Testbenchstimuli
Power waveform / profile
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ECE 260B CSE 241A Power Consumption 49 http:/ /vlsicad.ucsd.edu
Inaccuracies in Power EstimationIn increasing order:
The number of input stimuli did not cause any error above the 10% mark if we considered at least 10 input patterns
Using a gate-level simulator as opposed to a circuit simulator caused an error of about +/-15%
Repowering and physical design introduced inaccuracies below 20%
Glitch power varied between 7%-43%Internal gate capacitances, which are a function of the
target library, accounted for about half the power
Optimization and technology mapping may cause power estimates to be off by an order of magnitude
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ECE 260B CSE 241A Power Consumption 50 http:/ /vlsicad.ucsd.edu
Power and Synthesis Flow
Accuracy of Power Estimation
Pote
ntia
l fo
r Po
we
r Sa
vin
gs Behavioral
RTL
Gate
Switch
20%
400%
50%
10%
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 51 http:/ /vlsicad.ucsd.edu
Expectations
Algorithmic
Behavioral
RT Level
Tech. indep.
Tech dep.
Layout
Power manage
Algorithm selection
ConcurrencyMemory
Clock ctrl
Structural transform.
Extr/decomp
Tech. mappingGate sizing
Placement
orders of magnitude
several times
10-90%
10-15%
15%
20%20%
20%
Slide courtesy, Prof. J. Rabaey, UCB
-
ECE 260B CSE 241A Power Consumption 52 http:/ /vlsicad.ucsd.edu
Power Estimation / Improving Guidelines
Before technology mapping, the accuracy levels are unacceptable
It is necessary to take into account internal gate capacitances as well as wire capacitances
Gate-level estimation implies >15% error Simulation with as few as 10 patterns from typical inputs
for a typical starting state is often sufficient to reach confidence levels matching those of gate-level simulation
Power improving transformations should be l run in late design stages, they should be l applied only if they can predict significant power improvement,
and should be l applied many times (hundreds) to maximize the confidence of
positively impacting the design
-
ECE 260B CSE 241A Power Consumption 53 http:/ /vlsicad.ucsd.edu
Outline
Problem statementPower dissipation componentsPower estimationOptimization techniques
-
ECE 260B CSE 241A Power Consumption 54 http:/ /vlsicad.ucsd.edu
Low Power Design Techniques
Reducing chip and package capacitanceScaling the supply / threshold voltagesUsing power management strategiesEmploying better design techniques
-
ECE 260B CSE 241A Power Consumption 55 http:/ /vlsicad.ucsd.edu
Reducing Capacitance
Minimum area minimum power consumptionWirelength minimization with switching activities as
weighting factorsl Placement / routing / partition / floorplanning
Clock gatingSleep transistors
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ECE 260B CSE 241A Power Consumption 56 http:/ /vlsicad.ucsd.edu
CMOS Device and Voltage Scaling
Dual transistor threshold l High Vth transistors optimize performancel Low Vth transistors reduce leakage powerl Transistors with the same Vth need to group together
Dual supply voltage l High Vdd transistors on critical pathsl Low Vdd transistors reduce powerl Level-converters between signals of different voltage swingsl Routing cost of dual power supply
Extension of classical transistor sizing algorithm, e.g., TILOS
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ECE 260B CSE 241A Power Consumption 57 http:/ /vlsicad.ucsd.edu
Power Management Strategies
Inactive hardware modules are automatically turned off to save power (for example, monitors, laptops, etc.)
Transistors on non-critical data paths are slowed down, e.g., by dynamically scaling down their supply voltages (for example, in Transmeta microprocessors)
l Sleep transistorsl Power gating (controllable power supply mechanism)
-
ECE 260B CSE 241A Power Consumption 58 http:/ /vlsicad.ucsd.edu
Design Abstraction Levels
BehavioralSynthesis
RTLSynthesis
LogicOptimization
TransistorOptimization
Place & Route
HDL
PowerAnalysis
PowerAnalysis
PowerAnalysis
PowerAnalysis
Slide courtesy, Prof. J. Rabaey, UCB
-
ECE 260B CSE 241A Power Consumption 59 http:/ /vlsicad.ucsd.edu
Transistor-Level Power Optimization
Optimizes up to 30,000 transistors at a time
Starts from three initial solutions: initial sizes, all transistors sized up with constant factor, and all transistor identical size
Optimization modes: l
individual transistor sizingl
retain ratios between connected NMOS and PMOS devices
l pseudo-NMOS
Optimization Goals
l Delay
l Power
l Slack
AMPS - Epic
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 60 http:/ /vlsicad.ucsd.edu
Design Abstraction Levels
BehavioralSynthesis
RTLSynthesis
LogicOptimization
TransistorOptimization
Place & Route
HDL
PowerAnalysis
PowerAnalysis
PowerAnalysis
PowerAnalysis
Slide courtesy, Prof. J. Rabaey, UCB
-
ECE 260B CSE 241A Power Consumption 61 http:/ /vlsicad.ucsd.edu
Gate-Level Power Optimization
TechLibrary Power Optimization
Logic orGate Netlist Switching Activity
Constraints(timing, power, area)
Parasitics(Capacitance)
Power OptimizedGate Level Netlist
Logic Optimization
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 62 http:/ /vlsicad.ucsd.edu
Gate-Level Tradeoffs for Power
FactoringStructuringBuffer insertion/deletionDont care optimizationTechnology mappingSizingPin assignment
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 63 http:/ /vlsicad.ucsd.edu
Factoring
Idea: Remove common expressions to reduce capacitance
Caveat: This may increase activity!
Pa = 0.1
Pb = 0.5
Pc = 0.5
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 64 http:/ /vlsicad.ucsd.edu
Logic Restructuring
Logic restructuring to minimize spurious transitions
Buffer insertion for path balancing
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 65 http:/ /vlsicad.ucsd.edu
Technology Mapping
a
b
c
d
slack=1
Smaller gates reduce capacitance, but are slower
Slide courtesy, Prof. J. Rabaey, UCB
-
ECE 260B CSE 241A Power Consumption 66 http:/ /vlsicad.ucsd.edu
Technology MappingExample: 6-input AND Implemented using 6 input NAND, 3 input NAND, and 2-input NAND [Bellaouar, ElMasry]
Library 1: High-Speed
Library 2: Low-Area
Slide courtesy, Prof. J. Rabaey, UCB
-
ECE 260B CSE 241A Power Consumption 67 http:/ /vlsicad.ucsd.edu
Technology Mapping Example
6-input 3-input 2-inputArea 9 11 13Delay (ns) 1.1 0.86 0.83Energy (fF) 6.7 42.5 89.4
6-input 3-input 2-inputLibrary 1 6.7 42.5 89.4Library 2 3.5 19.5 43.7
Mapping results for high speed-library
Energy comparison between libraries
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 68 http:/ /vlsicad.ucsd.edu
Sequential Logic OptimizationState encoding
l seems to be of minimal impact in general
Data encoding in data pathsl e.g. use of sign-magnitude , one-hot, or redundant representationsl mostly ad hoc
Retiming for low powerl registers can be strategically placed to reduce glitching, or to perform
path balancing
Clock gatingPre-computation
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 69 http:/ /vlsicad.ucsd.edu
Clock gating
Requires careful skew control ...Scary in current logic synthesis world!
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 70 http:/ /vlsicad.ucsd.edu
Pre-computation
Other options: guarded evaluation
set output directly
Inputs xi xn are not appliedif pre-computing holds
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 71 http:/ /vlsicad.ucsd.edu
Power Compiler
Results:l design dependentl library dependentl average 15-20% push-
button reduction in power
Slide courtesy, Prof. J. Rabaey, UCB
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ECE 260B CSE 241A Power Consumption 72 http:/ /vlsicad.ucsd.edu
Low Power Synthesis
Introduce more concurrency for performance improvement
l Linear power consumption increase
Reduce power consumption by scaling down voltagesl Quadratic power consumption decrease
Concurrency increasing transformationsl Loop unrollingl Control flow optimizations
Critical path reducing transformationsl Logic level minimizationl Retimingl Pipelining
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ECE 260B CSE 241A Power Consumption 73 http:/ /vlsicad.ucsd.edu
Summary
Design Flow for Power well covered at circuit and gate level
Most emphasis on analysis not much on optimizationOverall optimization results are mixedPlenty of room at the physical end
l transistor sizing, circuit style selection, synthesis for pass-transistor networks, threshold selection
Slide courtesy, Prof. J. Rabaey, UCB