ECE 598 JS Lecture 12 I/Osjsa.ece.illinois.edu/ece598js/Lect_12.pdf · Author: StoneCreek Created...

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 598‐JS, Spring 2012 11

ECE 598 JS ‐ Lecture 12I/Os

Spring 2012

Jose E. Schutt-AineElectrical & Computer Engineering

University of [email protected]


- Loads are nonlinear- Need to model reactive elements in the time domain- Generalize to nonlinear reactive elements

Zo

Zo C

Motivations


dvi Cdt

For linear capacitor C with voltage v and current i which must satisfy

Using the backward Euler scheme, we discretize time and voltage variables and obtain at time t = nh

'1 1n n nv v hv

Time-Domain Model for Linear Capacitor


11' n

nivC

11

nn n

iv v hC

1 1 - n n nC Ci v vh h

After substitution, we obtain

so that

The solution for the current at tn+1 is, therefore,



i

v C

Backward Euler companion model at t=nh Trapezoidal companion model at t=nh



Step response comparisons

0 10 20 30 40 50 600.0

0.1

0.2

0.3

0.4

ExactBackward EulerTrapezoidal

Time (ns)

Vo (v

olts

)



div Ldt

1 1: n n nBackward Euler i i hi

11

nn

viL

1 1n n nL Lv i ih h

i

V+

-

R=

Vn1+

-

in+1

L

Lh

-

+Lh

i n

Time-Domain Model for Linear Inductor


1 12n n n nhi i i i

1 12 2

n n nL Lv i vh h

R=

Vn1

+

-

in+1

-

+

2Lh

2Lh

in Vn

i

V+

-L

If trapezoidal method is applied

Time-Domain Model for Linear Inductor


• Diode Properties– Two-terminal device that conducts current freely in one direction

but blocks current flow in the opposite direction.– The two electrodes are the anode which must be connected to a

positive voltage with respect to the other terminal, the cathode in order for current to flow.

+

-

V

I

9

The Diode


out DV V

/ 1D TV VD SI I e

( )S D D D D DV RI V RI V V

Nonlinear transcendental system Use graphical method

Vs/R

VD

ID

VSVout

Load line(external characteristics)

Diode characteristics

Solution is found at itersection of load line characteristics and diode characteristics

Diode Circuits


NPN Transistor

// 1 1BC TBE T v Vv V SC S

R

Ii I e e

// 1 1BC TBE T v Vv VSE S

F

Ii e I e

// 1 1BC TBE T v Vv VS SB

F R

I Ii e e

1F

FF

1

RR

R

Describes BJT operation in all of its possible modes

11

B

C

E

BJT Ebers-Moll Model


Problem: Wish to solve for f(x)=0

Use fixed point iteration method:

( ) ( ) ( )Define F x x K x f x

1: ( ) ( ) ( )k k k k kx F x x K x f x

With Newton Raphson:1

1( ) [ ( )] dfK x f xdx

therefore, 11: [ ( )] ( )k k k kx x f x f x

Newton Raphson Method


Newton Raphson Method(Graphical Interpretation)


11: k k k kN R x x A f x

1 ( ) .k k k k k kA x A x f x S

xk+1 is the solution of a linear system of equations. LU factk kA x S

Forward and backward substitution.

Ak is the nodal matrix for Nk

Sk is the rhs source vector for Nk.

Newton Raphson Algorithm


0 00. 0, ,

voltage controlled current controlled

k gives V i1. , mod .k kFind V i compute companion els

, , ,c c

k k k k

V C

G I R E

2. , .k kObtain A S

3. .k k kSolve A x S

14. kx Solution

15. .k kCheck for convergence x x , .If they converge then stop

6. 1 , 1.k k and go to step

Newton Raphson Algorithm


It is obvious from the circuit that the solution must satisfyf(V) = 0 We also have

/1'( ) tV Vs

t

If V eR V

The Newton method relates the solution at the (k+1)thstep to the solution at the kth step by

1( )- '( )

kk k

k

f VV Vf V

/ 1

1/

- 1

V Vk t

k t

k es

k kV Vs

t

V E IRV V I eR V

Newton Raphson - Diode


After manipulation we obtain

11 -k k k

Eg V JR R

/ k tV Vsk

t

Ig eV

/ ( -1) -k tV Vk s k kJ I e V g

Newton Raphson


out DV V

/( ) 1 0D TV VD SD S

V Vf V I eR

Newton-Raphson Method

Procedure is repeated until convergence to final (true) value of VD which is the solution. Rate of convergence is quadratic.

1( 1) ( ) ( ) ( )'( ) ( )k k k kx x f x f x

/1'( ) D TV VSD

T

If V eR V

( )

( )

( )/

( 1) ( )

/

1

1

kTD D

kTD

kV VS

Sk k

D D V VS

T

V VI e

RV V I eR V

Where is the value of VD at the kth iteration( )kDV

11 '( ) ( )k k k kx x f x f x

Use:

Diode Circuit – Iterative Method


Newton-Raphson representation of diode circuit at kth iteration

/k tV Vsk

t

Ig eV

/ ( -1) - Vk Vtk s k kJ I e V g

Newton Raphson for Diode


+

-V

i

ik

V

I

Companion

+

-

Rk

Ek

+

-

( )

k

ki i

dh iRdi

( )k k k kE h i R i

Current Controlled


Let x = vector variables in the network to be solved for. Let f(x) = 0 be the network equations. Let xk be the present iterate, and define

Let Nk be the linear network where each non-linear resistor is replaced by its companion model computed from xk.

( )k k kA f x Jacobian of f at x x

j -

j ++

-Vj

ij

( )j j jI g V

General Network


jk j k j kV P P j -

j +

IkGk

Vk

I

V

( )

k

kV V

dg VGdV

k k k kI g V G V

Companionmodel

General Network


C(v) Jk Jngk

+

-

V Vn+1

+

-

in+1in+1

Vn+1

+

-

q(V)h

Jn

( ) , dqq f v idt

1

1n

n nt t

dqq q hdt

1 11 1 1

( ), ( )n n nn n n

q q f vor i i vh h h

Nonlinear Reactive Elements


General Element


E

B

C

Vbc

Vbe

Ide

rIdc

Cbc

Cbe

E

C

B

fIde

IdcIB IC

IE

Bipolar Transistor


R1

Vcc

Vout

Q1Q6Vin

RE

Q2Q3

R2R3

Q4

Q5

R4 R5

Vin

R4 R5

RE

R1

R2

Vout

R3

Iout

Vcc

TTL Gate


0 1 2 3 4-200

-100

0

100

200

Vin=0.8VVin=1.4VVin=1.6VVin=1.8V

AS04 TT LI o

ut(m

A)

Vout

IV Curves for TTL Gate

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 598‐JS, Spring 2012

• I/O Buffer Information Specification is a Behavioral method of modeling I/O buffers based on IV curve data obtained from measurements or circuit simulation.

• The IBIS format is standardized and can be parsed to create the equivalent circuit information needed to represent the behavior of an IC.

• Can be integrated within a circuit simulator using an IBIS translator.

IBIS


• Protection of proprietary information

• Adequate for signal integrity simulation

• Models are free from vendors

• Faster simulations (with acceptable accuracy)

• Standardized topology

Advantage of IBIS


PowerClamp

Threshold&

EnableLogic

GNDClamp

GNDClamp

GNDClamp

PowerClamp

PowerClamp

InputPackage

EnablePackage

OutputPackage

PullupRamp

PulldownRamp

PullupV/I

PulldownV/I

IBIS Diagram


Power_Clamp

GND_Clamp

Vcc

R_pkg

C_pkg

L_pkg

C_comp

GNDGND

IBIS Input Topology


Vcc Vcc

Power_ClampGND_Clamp

GND GND

C_pkgL_pkg

R_pkg

C_omp

PullupPulldownRamp

IBIS Input Topology


Create an IBIS modelfrom either simulation

or empirical data

Model fromEmpirical data?

No

Yes

Collect Data

Data in IBIStext file

Run IBIS Parser

Parser Pass

Get SPICE I/Oinfo

No

Yes

Run modelon

Simulator

YesModelvalidated?

No Adoptmodel

Run SPICE to IBISTranslator

IBIS Model Generation


IBIS Model

Static data


IBIS Model

Dynamic data


IBIS VT Waveforms


|************************************************************************| Model lvpclpf5_ew|************************************************************************|[Model] lvpclpf5_ewModel_type I/OPolarity Non-InvertingEnable Active-HighVinl = 1.4500VVinh = 1.7500VVmeas = 1.6000V|C_comp 1.737pF 1.396pF 2.077pF||[Temperature Range] 25.0000 70.0000 0.000[Voltage Range] 3.3000V 3.0000V 3.6000V[Pulldown]| voltage I(typ) I(min) I(max)|-3.3000 -62.3070mA -48.2070mA -75.0990mA-3.1000 -62.3070mA -48.2070mA -75.0990mA-2.9000 -62.3070mA -48.2070mA -75.0990mA

IBIS File


|[Pullup]| voltage I(typ) I(min) I(max)|-3.3000 50.6898mA 38.3720mA 61.1590mA-3.1000 50.6898mA 38.3720mA 61.1590mA-2.9000 50.6898mA 38.3720mA 61.1590mA:|[GND_clamp]| voltage I(typ) I(min) I(max)|-3.3000 -7.7650A -6.8810A -8.3930A-3.2000 -7.4070A -6.5660A -8.0040A-3.1000 -7.0490A -6.2520A -7.6150A:|[POWER_clamp]| voltage I(typ) I(min) I(max)|-3.3000 1.1410A 1.1150A 1.1710A-3.2000 1.0910A 1.0670A 1.1200A-3.1000 1.0420A 1.0190A 1.0690A:

IBIS File


[Ramp]| variable typ min maxdV/dt_r 1.7344/9.6534e-11 1.4944/1.4735e-10 1.9469/7.9570e-11dV/dt_f 1.7528/1.4479e-10 1.5200/2.2995e-10 1.9609/1.2362e-10R_load = 50.0000 |[Rising Waveform]R_fixture = 50.000V_fixture = 0.000V_fixture_min = 0.000V_fixture_max = 0.000|| time V(typ) V(min) V(max)|0.000S 3.587e-04 4.167e-04 3.253e-04132.000pS 7.977e-05 1.311e-04 2.383e-04:[Rising Waveform]R_fixture = 50.000V_fixture = 3.300V_fixture_min = 3.000V_fixture_max = 3.600|| time V(typ) V(min) V(max)|0.000S 4.774e-01 5.704e-01 4.246e-0143.200pS 4.772e-01 5.701e-01 4.244e-01

IBIS File


|[Falling Waveform]R_fixture = 50.000V_fixture = 0.000V_fixture_min = 0.000V_fixture_max = 0.000|| time V(typ) V(min) V(max)|0.000S 2.808e+00 2.415e+00 3.156e+0063.000pS 2.809e+00 2.416e+00 3.156e+00126.000pS 2.808e+00 2.416e+00 3.156e+00:|[Falling Waveform]R_fixture = 50.000V_fixture = 3.300V_fixture_min = 3.000V_fixture_max = 3.600|| time V(typ) V(min) V(max)|0.000S 3.299e+00 2.999e+00 3.599e+0052.200pS 3.300e+00 2.999e+00 3.600e+00121.800pS 3.299e+00 2.999e+00 3.599e+00:|| End

IBIS File


1. Arrange static IV data

2. Pulldown data (current vs voltage) Ipd, mpd points

3. Pullup data (current vs voltage) Ipu, mpu points

4. Ground clamp data (current vs voltage) Igc , mgcpoints

5. Power clamp data (current vs voltage) Ipc , mpcpoints

IBIS Processing


• Next Get VT data. VT data is presented as: Rising waveform:

• Voltage versus time for Vfix low VR1 , mr1 points

• Voltage versus time for Vfix high VR2 , mr2 points: Falling waveform:

• Voltage versus time for Vfix low VF1 , mf1 points

• Voltage versus time for Vfix high VF2 , mf2 points

IBIS Processing


out fixtfixt

fixt

V VI

R

out outcap fixt

V t V t tI C

t

out cap fixtI I I out

comp fixt outIV L Vt

IBIS Circuit Analysis


• Pick value Vcomp1• Find closest corresponding currents in static IV data• Set them as Ipd1, Ipu1, Igc1 and Ipc1• Pick value Vcomp2• Find closest corresponding currents in static IV data• Set them as Ipd2, Ipu2, Igc2 and Ipc2

IBIS Circuit Analysis

We need to extract Ku and Kd


1 1 1 1 1out u pu d pd pc gcI K I K I I I

2 2 2 2 2out u pu d pd pc gcI K I K I I I

1 1 1 1 1 1u pu d pd out pc gc RHSK I K I I I I I

2 2 2 2 2 2u pu d pd out pc gc RHSK I K I I I I I

1 1 1

2 2 2

pu pd u RHS

pu pd d RHS

I I K II I K I

Rearrange as:

or

IBIS Circuit Analysis2 equations, two unknown system

Solve for Ku and Kd


Example of Ku and Kd


IBIS Simulations

u pu comp d pd comp pc comp gc compK I V K I V I V I V

0comp compout comp C comp G compI V I V I V

Solve using Newton-Raphson


IBIS Simulations


IBIS for Signal Integrity

• Crosstalk• Ringing, Overshoot, undershoot• Distortion, Nonlinear effects• Reflections issues• Line termination analysis• Topology scheme analysis

Visit http://www.eigroup.org/ibis/ibis.htm


The Node Voltage method consists in determining potential differences between nodes and ground (reference) using KCL

1 1 1 2 0m

A B C

V V V V VZ Z Z

For Node 1:

Nodal Analysis


22 1 2 0n

C D E

V VV V VZ Z Z

For Node 2:

1 21 1 1 1 1

mA B C C A

V V VZ Z Z Z Z

Rearranging the terms gives:

1 21 1 1 1 1

nC C D E E

V V VZ Z Z Z Z

Defining: 1 1 1 1 1, , , ,A B C D EA B C D E

G G G G GZ Z Z Z Z

Nodal Analysis



1

2

A B C C A m

C C D E E m

G G G G G VVG G G G G VV

The system can be solved to yield V1 and V2.

Nodal Analysis


1 1 1 25 0 10 45 010 5 2 2

V V j V Vj j

For Node 1:

For Node 2: 2 1 2 2 02 2 3 4 5V V V V

j j

Nodal Analysis



1 21 1 1 1 5 0 10 45

10 5 2 2 2 2 10 5V V

j j j j

1 21 1 1 1 0

2 2 2 2 3 4 5V V

j j j

Nodal Analysis


1

2

1 1 1 1 50 05 2 4 4 5

50 901 1 1 154 4 2 2

j VV

j

Nodal Analysis


1

10 0.2525 0.75 0.5 13.5 56.3 24.7 72.25

0.45 0.5 0.25 0.546 15.950.25 0.75 0.5

j jV V

jj

1

0.45 0.5 100.25 25 18.35 37.8 33.6 53.75

0.45 0.5 0.25 0.546 15.950.25 0.75 0.5

jj

V Vj

j

Nodal Analysis


• Nonlinear DevicesDiodes, transistors cannot be simulated in the

frequency domainCapacitors and inductors are best described in the

frequency domainUse time-domain representation for reactive elements

(capacitors and inductors)• Circuit SizeMatrix size becomes prohibitively large

Limitations


* SPICE

* Asymptotic Waveform Evaluation

* Complex Frequency Hopping

* Passive Multipoint Matching Method

* Latency Insertion Method

Y(t) v(t) = I(t)Given, Y and I, find v

Board/Module Chip

Circuit Simulation


spice3f4

conf examples lib doc

helpdir scripts

bjt

utiltmppatches srcnotesman

man1 man3 man5 unsuppobin include lib skeleton

ckt cp dev fte hlp inp mfb mfbpc misc ni sparse mac

asrc bsim1 bsim2 cap cccs ccvs csw dio disto ind isrc mes

mos1

ltrajfet

mos2 mos3 mos6 res sw tra urc vccs vcvs vsrc

lib

Parser StampFromNetlist I=YVDevice To

Solver

Directory Structure

SPICE


.

+- +-

+

-

+

-

+

-

+- +-

+

-

+

-

+

-

+- +-

+

-

+

Latency Insertion Method


- Up to 16 layers- Hundreds of vias- Thousands of TLs- High density- Nonuniformity

Vertical parallel-plate capacitance 0.05 fF/m2

Vertical parallel-plate capacitance (min width) 0.03 fF/mVertical fringing capacitance (each side) 0.01 fF/mHorizontal coupling capacitance (each side) 0.03

Mitsumasa Koyanagi," High-Density Through Silicon Vias for 3-D LSIs"Proceedings of the IEEE, Vol. 97, No. 1, January 2009

TSV Density: 10/cm2 - 108/cm2

Source: M. Bohr and Y. El-Mansy - IEEE TED Vol. 4, March 1998

Packaging Complexity

Chip Complexity

Challenges in Integration


X cells

Y cells

+- +-

+

-

+- +-

+

-

+

-=Unit cell

Typical workstation simulation time for a 1200-cell network is 2 h 40 min.

Too time consuming!

- Determine R,L,G,C parameters and define cell- Synthesize 2-D circuit model for ground plane- Use SPICE (MNA) to simulate transient

Modeling

PDN Modeling


• MNA has super-linear numerical complexity• LIM has linear numerical complexity• LIM has no matrix ill-conditioning problems• Accuracy and stability in LIM are easily

controlled• LIM is much faster than MNA for large circuits

Why LIM?


Each branch must have an inductor*

Each node must have a shunt capacitor*

Express branch current in terms of history of adjacent node voltages

Express node voltage in terms of history of adjacent branch currents

Latency Insertion Method

* If branch or node has no inductor or capacitor, insert one with very small value


• Represents network as a grid of nodes and branches

• Discretizes Kirchhoff's current and voltage equations

• Uses ”leapfrog” scheme to solve for node voltages and branch currents• Presence of reactive elements is required to generate latency

1 1/2 1/2n n n n nij ij i j ij ij

ij

tI I V V R IL

1/2

1/2 1

aNnn ni ii ik

n ki

ii

CV H ItV C G

t

Node structureBranch structure

LIM Algorithm


1 1/2 1/2n n n n nij ij i j ij ij

ij

tI I V V R IL

1/2

1/2 1

aNnn ni ii ik

n ki

ii

CV H ItV C G

t

1 2

1/2 3/2 5/2

n n nij ij ij

n n ni i i

I I I

V V V

n: time

LIM: Leapfrog Method

Leapfrog method achieves second-order accuracy, i.e., error is proportional to t2


1 1/2 1/2 1/2n n n n n nij ij i j ij ij ij

ij

tI I V V R I EL

For branch =1, NbUpdate current as per Equation:

For time=1, Nt

Next branch;For node=1, Nn

Update voltage as per Equation

1/2

1 11/2

iMn Nn n ni ii ik q

k qni

ii

CV H I Jt

V C Gt

Next node;Next time;

timeloop

branchloop

nodeloop

LIM Code


No of Nodes

20,000 30,000 40,000 50,000

SPICE(sec)

1224 2935 4741 7358

LIM(sec)

9 13 17 21

Speedup 136 225 278 350

Simulation Times

Standalone LIM vs SPICE


0 0.5 1 1.5 20

20

40

60

80

100

120

140

Log Size (normalized to 2,000 nodes)

Spe

edup

Fac

tor

LIM v.s. SPICE

LIM vs SPICE


Mutual inductanceuse reluctance (1/L) Branch capacitors special formulation Shunt inductors special formulation Dependent sourcesaccount for dependenciesFrequency dependence use macromodels

LIM: Problem Elements


-0.2

0

0.2

0.4

0.6

0.8

1

Volts

0 5 10 15 20 25 30

Time (ns)

Drive Line at Near End

35 40

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

Volts

0 5 10 15 20 25 30

Time (ns)

Sense Line at Near End

35 40

Computer simulations of distributed model (top) and experimental waveforms of coupled microstrip lines (bottom) for the transmission-line circuit shown at the near end (x=0) for line 1 (left) and line 2 (right). The pulse characteristics are magnitude = 4 V; width = 12 ns; rise and fall times = 1 ns. The photograph probe attenuation factors are 40 (left) and 10 (right).

LIM Simulations


Twisted-pair cable Simulation setupGeneralized model [3]

Ideal line lossy linelossy line

Simulation results Measured response

LIM Simulation Examples

ECE 598 JS Lecture 12 I/Osjsa.ece.illinois.edu/ece598js/Lect_12.pdf · Author: StoneCreek Created...

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Transcript of ECE 598 JS Lecture 12 I/Osjsa.ece.illinois.edu/ece598js/Lect_12.pdf · Author: StoneCreek Created...