ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES
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Transcript of ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES
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ECE 553: TESTING AND TESTABLE DESIGN OF
DIGITAL SYSTES
Motivation and Introduction
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Overview• Motivation• About the Course and the Instructor
– Conduct– Outline– Coursepack
• Introduction– VLSI realization process– Contract between design house and fab vendor– Test v/s verification– Need for testing: doing business, ideal v/s real testing– Levels of testing – rule of 10 (or 20)– Cost of manufacturing
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Motivation
• Where do the manufacturing $ go?
• Overhead of one or two photomicrographs– What is test on a chip?
• Course conduct– Your responsibilities and mine
• Course outline
• Course material information– References and reading material
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Motivation: Moore’s LawComplexity Growth of VLSI circuits
Source (Copp, Int. AOC EW Conf., 2002)
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Moore’s Law – Other Effects
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Thermal Effect of Moore’s lawMoore’s law Greater packaging densities
Higher power densities
Higher temperature
Effects ReliabilityPerformancePower Cooling cost
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Introduction: Challenges under deep submicron technologies (Yao)
Chip size decreasesPower density increases
Leakage power make it worseChip becomes hotter
Source: IntelSource: Intel
Source: Wang et al. ISPD2003
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Microprocessor Cost per TransistorCost of testing will EXCEED cost of design/manufacturing
(Source: ITR-Semiconductor, 2002)
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VLSI Realization Process
Determine requirements
Write specifications
Design synthesis and Verification
FabricationManufacturing test
Chips to customer
Customer’s need
Test development
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Technology Directions: SIA RoadmapYear 1999 2002 2005 2008 2011 2014
Feature size (nm) 180 130 90 45 32 22
Mtrans/cm2 7 14-26 47 115 284 701
Chip size (mm2) 170 170-214 235 269 308 354
Signal pins/chip 768 1024 1024 1280 1408 1472
Clock rate (MHz) 600 800 1100 1400 1800 2200
Wiring levels 6-7 7-8 8-9 9 9-10 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6
High-perf power (W) 90 130 160 170 174 183
Battery power (W) 1.4 2.0 2.4 2.0 2.2 2.4
http://www.itrs.net/ntrs/publntrs.nsf
Present and Future
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Contract between a design house and a fab vendor
• Design is complete and checked (verified)• Fab vendor: How will you test it?• Design house: I have checked it and …• Fab vendor: But, how would you test it?• Desing house: Why is that important? It is between
I and my clients – it is none of your business• Fab vendor – Sorry you can take your business
some where else.
complete the story and determine the reasons for the importance of test generation etc.
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Contract between design …Hence:• “Test” must be comprehensive• It must not be “too long”Issues:• Model possible defects in the process
– Understand the process
• Develop logic simulator and fault simulator• Develop test generator• Methods to quantify the test efficiency
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Verification v/s Testing
Definitions• Design synthesis: Given an I/O function, develop a
procedure to manufacture a device using known materials and processes.
• Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.
• Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.
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Verification v/s Testing • Verifies correctness of
design.
• Performed by simulation, hardware emulation, or formal methods.
• Performed once prior to manufacturing.
• Responsible for quality of design.
• Verifies correctness of manufactured hardware.
• Two-part process:– 1. Test generation: software process
executed once during design
– 2. Test application: electrical tests applied to hardware
• Test application performed on every manufactured device.
• Responsible for quality of devices.
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Need for testing• Functionality issue
– Does the circuit (large or small) work?
• Density issue– Higher density higher failure probability
• Application issue– Life critical applications
• Maintenance issue– Need to identify failed components
• Cost of doing business• What does testing achieve?
– Discard only the “bad product”? – see next three slides
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Problems of Ideal Tests
• Ideal tests detect all defects produced in the manufacturing process.
• Ideal tests pass all functionally good devices.• Very large numbers and varieties of possible
defects need to be tested.• Difficult to generate tests for some real defects.
Defect-oriented testing is an open problem.
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Real Tests• Based on analyzable fault models, which may not map on real defects.• Incomplete coverage of modeled faults due to high complexity.• Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss.• Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.
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Testing as Filter Process
Fabricatedchips
Good chips
Defective chips
Prob(good) = y
Prob(bad) = 1- y
Prob(pass test) = high
Prob(fail test) = high
Prob(fail test) = lowPro
b(pass
te
st) =
low
Mostlygoodchips
Mostlybad
chips
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Levels of testing (1)• Levels
– Chip
– Board
– System• Boards put together
• System-on-Chip (SoC)
– System in field
• Cost – Rule of 10– It costs 10 times more to test a device as we move to
higher level in the product manufacturing process
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Levels of testing (2)• Other ways to define levels – these are important
to develop correct “fault models” and “simulation models”– Transistor– Gate– RTL– Functional– Behavioral– Architecture
• Focus: Chip level testing – gate level design
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Cost of Testing• Design for testability (DFT)
– Chip area overhead and yield reduction
– Performance overhead
• Software processes of test– Test generation and fault simulation
– Test programming and debugging
• Manufacturing test– Automatic test equipment (ATE) capital cost
– Test center operational cost
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Cost of Manufacturing Testing in 2010+
• 0.5-1.0GHz, analog instruments,1024 digital pins: ATE purchase price– = $4.0M + 1,024 x $5,000 = $9.12M
• Running cost (five-year linear depreciation)– = Depreciation + Maintenance + Operation
– = $1.80M + $0.185M + $1.5M– = $3.485M/year
• Test cost (24 hour ATE operation)– = $3.485M/(365 x 24 x 3,600)– = 11.05 cents/second
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Roles of Testing• Detection: Determination whether or not the device
under test (DUT) has some fault.• Diagnosis: Identification of a specific fault that is
present on DUT.• Device characterization: Determination and
correction of errors in design and/or test procedure.• Failure mode analysis (FMA): Determination of
manufacturing process errors that may have caused defects on the DUT.
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Summary• About the course
• Expectations
• Why test?
• Cost issue – First look