ECE 4436ECE 5367 ISA I. ECE 4436ECE 5367 CPU = Seconds= Instructions x Cycles x Seconds Time Program...
-
Upload
oliver-powers -
Category
Documents
-
view
217 -
download
1
Transcript of ECE 4436ECE 5367 ISA I. ECE 4436ECE 5367 CPU = Seconds= Instructions x Cycles x Seconds Time Program...
ECE 4436ECE 5367
ISA I
ECE 4436ECE 5367
CPU = Seconds = Instructions x Cycles x Seconds
Time Program Program Instruction Cycle
CPU = Seconds = Instructions x Cycles x Seconds
Time Program Program Instruction Cycle
ECE 4436ECE 5367
CPU time = ClockCycleTime * CPI * Ii = 1
n
i i
CPI = CPI * F where F = I i = 1
n
i i i iInstruction Count
"instruction frequency"
Invest Resources where time is Spent!
CPIave = (CPU Time * Clock Rate) / Instruction Count = Clock Cycles / Instruction Count
“Average cycles per instruction”
CPI
ECE 4436ECE 5367
MIPS Assembly Language
CPU
I/O
MemoryControl
Datapath
ECE 4436ECE 5367
MIPS Assembly Language
• CPU Datapath (extremely simplified)
Registers ALU
Operand 1
Operand 2
Operation
Result
ECE 4436ECE 5367
Basic Architecture Model
ECE 4436ECE 5367
Software Layer
ECE 4436ECE 5367
MIPS Assembly Language Notation
ECE 4436ECE 5367
0r0r1°°°r31PClohi
Register (32 bits)
ECE 4436ECE 5367Memory Organization
32 bits register 8 bits memory how do byte addresses map onto words?Can a word be placed on any byte boundary?
ECE 4436ECE 5367Addressing Objects: Endianess and Alignment
• Big Endian: address of most significant byte = word address (xx00 = Big End of word)
– IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA
• Little Endian: address of least significant byte = word address (xx00 = Little End of word)
– Intel 80x86, DEC Vax, DEC Alpha (Windows NT)
msb lsb
3 2 1 0
0 1 2 3big endian byte 0
Alignment: require that objects fall on address that is multiple of their size.
0 1 2 3
Aligned
NotAligned
little endian byte 0
ECE 4436ECE 5367
Executing an Assembly Instruction
ECE 4436ECE 5367
Register File Execution
ECE 4436ECE 5367
Register File Execution
ECE 4436ECE 5367
Register File Execution
ECE 4436ECE 5367
Data Access
ECE 4436ECE 5367
Memory Load Operation
ECE 4436ECE 5367
Loading data from Memory
ECE 4436ECE 5367
Loading data from Memory
ECE 4436ECE 5367
MIPS Fields
• op – operation to be performed• rs – first source operand• rt – second source operand• rd – register destination operand, gets the result
of the operation.• shamt – shift amount – used in shift instructions.
• funct – selects specific operation of opcode in op field – R-type……..
ECE 4436ECE 5367
MIPS Assembly Language:Instruction Set
• 3 different instruction formats– I-type,
– R-type, &
– J-type (we’ll discuss first two for now)
ECE 4436ECE 5367
R-type instructions• R-type
– Three register operands– Arithmetic & logical opcodes– Format:
– Rd = destination operand (output)– Rs = source operand (input)– Rt = source operand (input)
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Opcode Rs Rt Rd shamt function
ECE 4436ECE 5367
R-type contd..
• R-type: 6 fields
• R-type at work– ADD $3,$1,$2
– SUB $7,$4,$5
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Opcode Rs Rt Rd shamt function
Page 90
ECE 4436ECE 5367
More R-type examples……• jr $31
• sltu $3, $8, $9
• mult $5, $6
ECE 4436ECE 5367
I-type instructions.• I-type
– Two registers and an immediate– Format:
– Rt = destination operand– Rs = source operand– Immediate = a constant, also a source operand
• Note: immediate operand must fit into 16 bits! (Why?)
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Opcode Rs Rt address
ECE 4436ECE 5367
I-type instructions contd…• I-type: 4 fields
• I-type at work– ADDI $2,$1,32
– LUI $7,OxABCD
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
Opcode Rs Rt address
!Loads & stores are the data transfer
instructions!
ECE 4436ECE 5367
More I-type examples
• lw $5, 60($4)
• sw $5, 60($4)