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Transcript of ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers...
ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Big Picture – Lab 2
int circ_buffer[N], circ_buffer_head = 0;int c[N]; /* coefficients */…int ibuf, ic;for (f=0, ibuff=circ_buff_head, ic=0;
ic<N; ibuff=(ibuff==N-1?0:ibuff++), ic++)f = f + c[ic]*circ_buffer[ibuf];
2ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Outline for Today’s Lecture
Administrative, Lab2, Feedback on Lab1 Embedded CPUs Interrupts IO Embedded System Software Design Basics on Image Manipulation
3ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Readings
Chapters 2, 3 • CPUs, Interrupts
Chapter 4, emphasizing 4.1 through 4.7• I/O, USB, debugging
Chapter 5, emphasizing 5.1-5.4, 5.9• Programming, patterns, test …
Basics on Image manipulation• http://student.kuleuven.be/~m0216922/CG/filtering.html
4ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Objectives of Lab 2
Sense the external world through a camera Transfer the camera data to the DE2 board Process the image in software on the NIOS View the images on the monitor
Concepts:• I/O (camera, monitor, interrupts)• Basic image processing• Embedded software design and test running on an
embedded processor
5ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Outline for Today’s Lecture
Administrative, Lab2, Feedback on Lab1 Embedded CPUs Interrupts IO Embedded System Software Design Basics on Image Manipulation
6ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Superscalar
RISC pipeline executes one instruction per clock cycle (usually).• For example, ARM, MIPS, PowerPC, etc
Superscalar machines execute multiple instructions per clock cycle.• Faster execution.• More variability in execution times.• More expensive CPU.• Requires a lot of hardware.
• n2 instruction unit hardware for n-instruction parallelism.
• For example, Intel X86
7ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Order of execution
In-order:• Machine stops issuing instructions when the next
instruction can’t be dispatched.
Out-of-order:• Machine will change order of instructions to keep
dispatching.• Substantially faster but also more complex.• Can be still in-order completion avoid issues with
precise exceptions etc
8ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
VLIW architectures
Very long instruction word (VLIW) processing provides significant parallelism.
Rely on compilers to identify parallelism. VLIW requires considerably more sophisticated
compiler technology than traditional architectures---must be able to extract parallelism to keep the instructions full.
VLIW is popular for various embedded designs• EPIC = Explicitly parallel instruction computing.
• Used in Intel/HP Merced (IA-64) machine.
9ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Difference between microcontrollers, microprocessors and FPGA systems FPGA systems often contain
CPUs in softcore (synthesized) or hardcore (part of die) format but can also contain logic blocks for other hardware, e.g., state machines, etc
• Recent 65 nm FPGAs (Virtex 5) can achieve high performance. Key issues?
Microcontrollers are more limited in functionality and often do not include support for virtual memory and caches
• Up to 50MHz Microprocessors are more
performance capable and have typically virtual memory support
• From 50MHz to GHz
TxTx
RxRx
DiscreteDiscretePHYPHY
DiscreteDiscretePHYPHY
TxTx
RxRx
Soft coreSoft core
Hard core with built-in
Transceivers
Hard core with built-in
Transceivers
10ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Another perspective:PLDs, FPGAs, ASICs, Structured ASICs Programmable logic devices (PLDs) provide
low/medium density logic. Field-programmable gate arrays (FPGAs) provide
more logic and multi-level logic. Application-specific integrated circuits (ASICs)
are manufactured for a single purpose. Structured ASICs are inbetween FPGAs and ASIC
11ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Memory system
CPU fetches data, instructions from a memory hierarchy:
Mainmemory
L2cache
L1cache CPU
Some systems also include TLB to provide a cache during address translation
DRAM/FlashSRAM
SRAM
12ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Memory hierarchy complications
Program behavior is much more state-dependent.• E.g., depends on how earlier execution left the cache.
Execution time is less predictable.• Memory access times can vary by 100X.• Virtual memory, TLB, etc all affect performance
13ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Types of memory
ROM:• Mask-programmable.
• High density – downside?• Flash programmable.
• Challenges? Advantages? # of erase cycles
RAM:• DRAM. Access time?• SRAM. Access time?
What kinds of memory do we use in Lab 1?In Lab 2? Why?
14ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Memory device organization
n r
c
w
n address lines w data lines
Word-line
Bit-line
Memory cell
Memory array
15ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Cache Organization
MatchlineCAM
Tags
Data
SRAM
Cache Bank
32
lines
8 words
16 Banks
Tag Bank Word Byte
31 9 8 5 4 2 1 0
Virtual Address:
MUX
Data
16ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Virtual Memory Organization Example
17ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
In Embedded Designs MMU Can Look Much Simpler
18ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
But Also Fairly Complicated
19ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Programming model in Processors
Assembly language• One-to-one with machine instructions (more or less).• Labels provide names for addresses (usually in first
column).• Pseudo-ops: constants, define storage, define address
Programming model: registers visible to the programmer.• For example ARM has 32 registers• Some registers are not visibible: system registers
20ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
ARM assembly language example
label1 ADR r4,c
LDR r0,[r4] ; a comment
ADR r4,d
LDR r1,[r4]
SUB r0,r0,r1 ; comment
21ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Visualizing
Control Flow Graphs Procedures Loops Basic Blocks Instructions
Copyright BlueRISC 2007
22ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Outline for Today’s Lecture
Administrative, Lab2, Feedback on Lab1 Embedded CPUs Interrupts IO Embedded System Software Design Basics on Image Manipulation
23ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Interrupt interface
CPU
statusreg
datareg
mec
hani
sm
PC
intr request
intr ack
data/address
IR
24ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Prioritized interrupts
CPU
device 1 device 2 device n
L1 L2 .. Ln
interruptacknowledge
Masking: interrupt with priority lower than current priority is not recognized until pending interrupt is complete.
Non-maskable interrupt (NMI): highest-priority, never masked.
• Often used for power-down.
25ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Example: Prioritized I/O
:interrupts :foreground :A :B :C
B
A,B
C
A
26ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Generic interrupt mechanism
intr?N
YAssume priority selection is
handled before this point.
Nignore
Y
ack
vector?Y
Y
Ntimeout?
Ybus error
call table[vector]
intr priority > current priority?
continueexecution
27ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Interrupt vectors
Allow different devices to be handled by different code.
Interrupt vector table:
handler 0
handler 1
handler 2
handler 3
Interruptvector
table head
28ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Sources of interrupt overhead
Handler execution time. Interrupt mechanism overhead. Register save/restore. Pipeline-related penalties. Cache-related penalties.
29ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
ARM interrupts
ARM7 supports two types of interrupts:• Fast interrupt requests (FIQs).• Interrupt requests (IRQs).
Interrupt table starts at location 0.
30ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Exception and Trap
Exception: internally detected error.• Exceptions are synchronous with instructions but
unpredictable.• Build exception mechanism on top of interrupt
mechanism.
Trap (software interrupt): an exception generated by an instruction.• Call supervisor mode.• ARM uses SWI instruction for traps.
31ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Outline for Today’s Lecture
Administrative, Lab2, Feedback on Lab1 Embedded CPUs Interrupts IO Embedded System Software Design Basics on Image Manipulation
32ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
I/O devices
I/O devices:• serial links (UART, USB, SPI, RS-232, RS-485, I2C, S2C,
high-speed such as PCIe…)• timers and counters• keyboards• displays• analog I/O
33ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Application: 8251 UART
Universal asynchronous receiver transmitter (UART) : provides serial communication.
8251 functions are integrated into standard PC interface chip.• 8255 used to a be a parallel interface
Allows many communication parameters to be programmed.
34ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Serial communication
Characters are transmitted separately:
time
bit 0 bit 1 bit n-1
nochar
start stop...
35ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Serial communication parameters
Baud (bit) rate. Number of bits per character. Parity/no parity. Even/odd parity. Length of stop bit (1, 1.5, 2 bits).
36ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
8251 CPU interface
CPU 8251
status(8 bit)
data(8 bit)
serialport
xmit/rcv
37ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Programming I/O
Two types of instructions can support I/O:• special-purpose I/O instructions;• memory-mapped load/store instructions.
Intel x86 provides in, out instructions. Most other CPUs use memory-mapped I/O.
I/O instructions do not preclude memory-mapped I/O.
38ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
USB 2.0 Goals:
• Easy to use.• Low cost for consumer devices.• Up to 480 Mb/s in 2.0.
• A Low Speed (1.1, 2.0) rate of 1.5 Mbit/s (187 kB/s) that is mostly used for Human Interface Devices (HID) such as keyboards, mice, and joysticks.
• A Full Speed (1.1, 2.0) rate of 12 Mbit/s (1.5 MB/s). Full Speed devices divide the USB bandwidth between them in a first-come first-served basis and it is not uncommon to run out of bandwidth with several isochronous devices. All USB Hubs support Full Speed.
• A Hi-Speed (2.0) rate of 480 Mbit/s (60 MB/s). • Experimental data rate:
• A Super-Speed (3.0) rate of 4.8 Gbit/s (600 MB/s).
39ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
USB bus protocol
Polled bus, all transfers initiated by host. Basic transaction:
• Host sends token packet:• Type and direction.• USB device number.• Endpoint number (subdevice).
• Data transfer packet.• Acknowledge packet.
Differential signaling: Vdd+, Vdd-, Data+, Data-
40ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
PCIe Architecture
X8 EndX8 EndPointPoint
X8 EndX8 EndPointPoint
X4 EndX4 EndPointPoint
X4 EndX4 EndPointPoint
X2 EndX2 EndPointPoint
X2 EndX2 EndPointPoint
PCIPCIBridgeBridge
PCIPCIBridgeBridge
SWITCHSWITCHSWITCHSWITCH
CPUCPUCPUCPU
ROOT COMPLEXROOT COMPLEXROOT COMPLEXROOT COMPLEX
SWITCHSWITCHSWITCHSWITCH SWITCHSWITCHSWITCHSWITCH
X1 EndX1 EndPointPoint
X1 EndX1 EndPointPoint PCIPCIPCIPCI
PCI Express PCI Express Graphics : 16XGraphics : 16XPCI Express PCI Express
Graphics : 16XGraphics : 16X
- PCIe Link
MemoryMemoryMemoryMemory
•Not a bus but point to pointFull duplex Communication•1-32 lanes each32MB/s
41ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Outline for Today’s Lecture
Administrative, Lab2, Feedback on Lab1 Embedded CPUs Interrupts IO Embedded System Software Design Basics on Image Manipulation
42ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Software components
Need to break the design up into pieces to be able to write the code.
Some component designs come up often.• A design pattern is a generic description of a
component that can be customized and used in different circumstances.
Firmware – basic system software for a chip Device driver – control of hardware modules in a
system tightly coupled with operating systems
43ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Building Code Image
HLL compile assembly assembleHLLHLLsource
assemblyassembly
linkexecutableload
44ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Assemblers
Major tasks:• generate binary for symbolic instructions;• translate labels into addresses;• handle pseudo-ops (data, etc.).
45ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Linking
Combines several object modules into a single executable module.
Jobs:• put modules in order;• resolve labels across modules.
46ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Dynamic linking
Some operating systems link modules dynamically at run time:• shares one copy of library among all executing
programs;• allows programs to be updated with new versions of
libraries.
47ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Embedded system design often includes software state machines State machine keeps internal state as a variable,
changes state based on inputs.
A B
C D
in1=1/x=a
in1=0/x=b
r=0/out2=1
r=1/out1=0
s=1/out1=1
s=0/out1=0
48ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
C state table
switch (state) {case A: if (in1==1) { x = a; state = B; } else { x = b; state = D; }
break;case B: if (r==0) { out2 = 1; state = B; } else { out1 = 0; state = C; }
break;case C: if (s==0) { out1 = 0; state = C; } else { out1 = 1; state = D; }
break;
49ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
How to build/debug? Host-target design, debugging Use a host system to prepare software for target
• Cross compiler: compiles code on host for target system. Cross debugger: displays target state, allows target to be
controlled. Optimizing for execution time, energy/power, program size.
targetsystem
host systemserial line
50ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
In-circuit emulators
A microprocessor in-circuit emulator is a specially-instrumented microprocessor.
Allows you to stop execution, examine CPU state, modify registers.
Many microprocessors also support software debugging through special ports and (typically) Jtag interface
51ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Outline for Today’s Lecture
Administrative, Lab2, Feedback on Lab1 Embedded CPUs Interrupts IO Embedded System Software Design Basics on Image Manipulation
52ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Images
A picture is a rectangular array of pixels (=picture element)
A digital picture is a picture stored in binary (bits).• The picture resides in a digital storage system as a file.
53ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Pixels, Grey Values and Quantization
Conceptually, a monochrome (black and white) image is a function f(x, y), sampled over a two-dimensional grid. • Each sample value is called a pixel (picture element).
Conceptually, the function is real-valued and has a continuous range. This is called the grey value of the pixel.• On a computer, it is represented with a finite number of bits.
This is called quantization.
54ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Example
Raw picture format, 256x256, 1 byte per pixel
1 2 3 ... 256
257 258 259 ... 512
513 514 515 ... 768
... ... ... ... ...
65,280 65,281 ... ... 65,536
Pixel sequence in file
55ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Calculations In the so-called raw format, the file contains only the gray values
of the pixels. Bits/picture = Rows x Columns x bits/pixel Bytes/picture = Rows x Columns x bytes/pixel Example:
• For the previous slide, 256 rows, 256 columns, 1 byte per pixel.• Bytes = 256x256x1 = 65536
56ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Pixels, Quantization, and Quality
A given picture can be represented with different numbers of pixels and various numbers of bits per pixel.• Fewer pixels produces lower quality• Fewer bits per pixel produces lower quality
There is a tradeoff between quality and picture storage requirements.
57ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Examples of quantization vs. resolution
64x64, 8 bit, 4 kBLower resolution
256x256, 1 bit, 8 kB256x256, 4 bit, 32 kB256x256, 8 bit, 64 kB 256x256, 2 bit, 16 kB
58ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Some Image Processing functions
Add timestamp onto image Counter to keep track of number of pictures
taken Rotate, mirror, invert image Simple edge detection (hard) Detect motion in images (harder) Detect illegal behavior in images (computer
vision)
59ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Uses of Digital Pictures
Consumer and Commercial Photography Web-cam Medical Imaging
• X-ray• Tomography• Ultrasound
Video• DVD• Broadcast• Surveillance
What quality levels are required for each?Storage requirements?
60ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Why Standard Formats?
Interoperability• Image made by Nikon, viewed on computer made by
Apple.
Advantages of standards• Competition among vendors (lower prices)• Creation of markets• Multiple vendors - product cycle safety
61ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Image Coding (Compression)
Why compress?• Store more pictures in same memory• Spend less time sending picture over web
Lossless compression (LZ, Huffman, RLE):• Decompress file and get the same picture, bit - for - bit
Lossy compression (JPEG,…):• Decompress and get something similar.• Any amount of compression is possible.• Tradeoff between image quality and compression.
62ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Example of JPEG compression
Very high quality: compression = 2.33Photoshop Image
Very low quality: compression = 115Produced by MATLABwith Quality = 0
63ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
What’s Next ?
Lab 2 details by TA.
64ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
BACKUP
65ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Design patterns
Design pattern: generalized description of the design of a certain type of program.
Designer fills in details to customize the pattern to a particular programming problem.
Useful in both C and Verilog!• Patterns are close but not the same in C and Verilog
66ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
State machine pattern
State machine
state
output step(input)
67ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
C implementation
#define IDLE 0#define SEATED 1#define BELTED 2#define BUZZER 3switch (state) {
case IDLE: if (seat) { state = SEATED; timer_on = TRUE; }break;
case SEATED: if (belt) state = BELTED;else if (timer) state = BUZZER;
break;…
}
68ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Circular buffer
x1 x2 x3 x4 x5 x6
t1 t2 t3
Data stream
x1 x2 x3 x4
Circular buffer
x5 x6 x7
69ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Circular buffer pattern
Circular buffer
init()add(data)data head()data element(index)
70ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Circular buffer implementation: FIR filter
int circ_buffer[N], circ_buffer_head = 0;int c[N]; /* coefficients */…int ibuf, ic;for (f=0, ibuff=circ_buff_head, ic=0;
ic<N; ibuff=(ibuff==N-1?0:ibuff++), ic++)f = f + c[ic]*circ_buffer[ibuf];
71ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Example: FIR filter
Code:for (firout = 0.0, j =0; j < N; j++)
firout += buff[j] * c[j];if (firout > 100.0) firout = 100.0;if (firout < -100.0) firout = -100.0;
Controllability: to test range checks for firout, must first load circular buffer.
Observability: how do we observe values of buff, firout?
72ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Patterns for digital images?
For Lab 3, It is required that you implement two forms of image processing
Recommendations include:• Add timestamp onto image• Counter to keep track of
number of pictures taken• Rotate, mirror, invert image• Simple edge detection
(challenging)• Detect changes in images
(challenging)
Pattern for image processing
http://www.student.kuleuven.ac.be/~m0216922/CG/filtering.html#Find_Edges_
73ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Circular buffers
Indexes locate currently used data, current input data:
d1
d2
d3
d4
time t1
use
input d5
d2
d3
d4
time t1+1
use
input
74ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
C circular buffer
To compute FIR filter value f:
for (f=0, ic=0, ibuff = circ_buff_head;
ic < N;
ibuff = (ibuff = N-1 ? 0 : ibuff++) )
f = f + c[ic] * circ_buff[ibuff]
75ECE 354 © Moritz 2009, some slides modified from Moritz/Koren/Burleson, UMass and Wolf, Computers as Components, Morgan Kaufman, 2005
Program design and analysis
Program validation and testing.
Make sure software works as intended.• We will concentrate on functional testing---performance
testing is harder.
What tests are required to adequately test the program?• What is “adequate”?