ECE 3450 M. A. Jupina, VU, 2014 Analog-to-Digital and Digital-to-Analog Conversion Introduction...

ECE 3450 M. A. Jupina, VU, 2014

Analog-to-Digital and

Digital-to-Analog Conversion

Introduction (Applications and S/H Circuit)

DAC ADC


Computerized Motor Control Through the Use of a DAC


Example: Function Generator Using a ROM and a DAC

TCLK

TSIGNAL

2 1

2

2 1

PP

N

OUT REFN

N

V V

V

Low PassFilter

N=8 and 5

5256

B is a value between

0 and 255 stored in a ROM register

REF

A

For V V

BV t V

where


What clock frequency will result in a 100 Hz sine wave at the output?

What method could be used to vary the peak-to-peak amplitude of the sine wave?

100 256 25.6KHz

Adjust the reference voltage of the DAC.


Programmable Gain Amplifier with a DACAC Input Signal

AC Output Signal

Digital Inputs

IO

IO

14

O O

O DC AC

SREFO

S

R I

R I I t

V tVR A A

R R

DC Input Signal

DC Blocking Capacitor

SO O

S

V tV R A

R


DVM Using an ADC


Real World Applications

Analog-to-digital converters (ADC) and digital-to-analog converters (DAC) are used to interface a computer to the analog world so that the computer can monitor and control a physical variable.


Data Sampling System Block Diagram


Simplified Diagram of a Sample-and-Hold Circuit


LF398 Sample-and-Hold (S/H) Circuit

F


Block Diagram of a Digital Storage Oscilloscope


Digital Signal Processor (DSP) Architecture


Ideal FIR LP Filter

Digital Filter (FIR Low Pass) Implementation on UP1 Board


Example Filter Measurements on a Scope

ALL Pass Filter (Sampling Effects) ALL Pass Filter (Alias Signal)

FIR Low Pass Filter (Gain and Phase Measurements)

Vinpp

Voutpp

0360 S

pp

pp

VoutGain

Vin

Phase hift tT


Digital-to-AnalogConversion

Definitions Example Problems Various DAC Circuitries DAC0808


Four-Bit DAC with Voltage Output

VREF = 16 V

2 1 2FS REF

STEP N N

V VV


Output Waveform of a 4-Bit DAC with a Binary Counter Supplying the Input


DAC Transfer Function


Definitions• Full Scale Output – the maximum value that the D/A converter can produce.• Resolution or Step Size – the smallest change that can occur in the analog

output as a result of a change in the digital input.

where N is number of bits

• Analog Output = K • decimal value of the digital input• Percentage Resolution

• Accuracy Full Scale Error – maximum deviation of the DAC’s output from its ideal value. Linearity Error – maximum deviation in step size from the ideal step size. Offset Error – the small output voltage that exists when all inputs are “0”

• Settling Time – the time required for the DAC output to go from zero to full scale as the binary input goes from all 0’s to all 1’s.

100%

resolution

full scale

2 1FS

N

AK


Example Problems1) An eight-bit DAC produces an output voltage of 2.0 V for an input

code of 01100100. What will the value of VOUT be for an input code of 10110011?

011001002 = 10010

101100112 = 17910

(179/100) = (X/2V)X = 3.58V

2) What is the resolution of the DAC in the previous? Express it in volts and as a percentage. Determine the weight of each input bit.

Resolution = 2V/100 = 20mV Full Scale Voltage = 20mV (28 -1) = 5.1V% Resolution = [20mV / {20mV (28 -1) }] x 100% 0.4%LSB = 2V/100 = 20mVOther bits: 40mV, 80mV, 160mV, 320mV, 640mV, 1280mV, and 2560mV.


Example Problems3) What is the resolution in volts of a 10-bit DAC whose Full-Scale

output is 5 V?

10 bits---> 210 -1 = 1023 steps

Resolution = 5V/1023 = 4.89 mV 5mV

4) How many bits are required for a DAC so that its Full-Scale output is 10 mA and its resolution is less than 40 A?

The maximum resolution is 40µA. The number of steps required to produce 10mA full scale will be at least 10mA/40µA = 250.

Therefore, it requires at least 8 bits.


Example Problems5) Assuming a 12-bit DAC with perfect accuracy, how close to 250 rpm can the motor speed be adjusted for the motorized system below?

12-bit DAC gives us 212 -1 steps = 4095. Step-Size = 2mA/4095 = 488.4nA

To have exactly 250 RPM the output of the DAC must be(250 RPM x 2mA) / 1000 RPM = 500µA.

In order to have 500µA at the output of the DAC, the computer must increment the input of the DAC to the count of 500µA/488.4nA = 1023.75.

Thus, the motor will rotate at (1024/4095) x 1000 RPM = 250.061 RPM when the computer's output has incremented 1024 steps.


Example Problems6) An eight-bit DAC has a full-scale error of 0.2% F.S. If the DAC has a full-

scale output of 10 mA, what is the most that it can be in error for any digital input? If the DAC output reads 50 A for a digital input of 00000001, is this within the specified range of accuracy? (Assume no offset error.)

Full Scale error = 0.2% x 10mA = 20µA

Step-Size = 10mA/255 = 39.2µA. Ideal output for 000000012 is 39.2µA.

The possible range is 39.2µA ± 20µA = 19.2µA to 59.2µA.

Thus, 50µA is within this range.


Example Problems7) A particular 6-bit DAC has a full-scale output rated at 1.260 V. Its accuracy is

specified as ± 0.1% F.S., and it has an offset error of ±1 mV. Assume that the offset error has not been zeroed out. Consider the measurements made on this DAC in the table below, and determine which of them are not within the device’s specifications.

Step-Size = 1.26V/63 = 20mV

±0.1% F.S. = ±1.26mV

Thus, maximum error will be ±1.26mV ±1mV = ±2.26 mV.

0000102 --> 2 x 20mV = 40mV [41.5mV is within specs.] .0001112 --> 7 x 20mV = 140mV [140.2mV is within specs.] .0011002 --> 12 x 20mV = 240mV [242.5mV isn't within specs.] .1111112 --> 63 x 20mV = 1.260V [1.258 V is within specs.] .

Input Code Output

000010 41.5 mV

000111 140.2 mV

001100 242.5 mV

111111 1.258 V


Simple DAC Using an Op-Amp Summing Amplifier with Binary-Weighted Resistors

1 1 12 4 8

F F F FOUT D C B A

D C B A

D C B A

R R R RV V V V V

R R R R

V V V V

1 K

2 K

1 K

4 K

8 K


Improved DAC using Summing Amplifier with Precision Voltage Source

1 K2 K

1 K

4 K

8 K


Basic R/2R Ladder DAC


DAC0808 R/2R Ladder DAC with Current Output


DAC0808 Block Diagram


DAC0808 Specifications

• The DAC0808 is an 8-bit monolithic DAC• Full Scale Error: ±0.19% • Offset current levels less than 4 A for • Maximum output current: 2 mA.• Fast settling time: 150 ns typical• Power supply voltage range: ±4.5V to ±18V• Low power consumption: 33 mW @ ±5V

REFI 2 mA


DAC Circuit

MSB

LSB

F ref

O ref

Assuming matched resistors (R = R ),

A1 A2 A3 A4 A5 A6 A7 A8thus E = V

2 4 8 16 32 64 128 256


Analog-to-DigitalConversion

Definitions Effects of Sampling Various ADC Circuitries Example Problems ADC0804


General Diagram of One Class of ADCs


Typical Computer Data Acquisition System

Waveforms showing how the computer initiates each new conversion cycle andthen loads the digital data into memoryat end of conversion (EOC).


ADC Ideal Linear Transfer Function


Definitions• Full Scale Input – the maximum value that the A/D converter can accept.

• Resolution or Step Size – the smallest change that can occur in the analog input to produce a change in the digital output.

where N is number of bits

• Accuracy Quantization Error – the maximum difference between the actual analog input

voltage and the digital output value representing it. This is equal to the resolution. Full Scale Error – maximum deviation in the ADC’s comparator reference voltage

or the internal DAC’s output voltage from the ideal value.

• Conversion Time – the time required for the ADC to convert an analog input voltage into a digital output.

2 1FS

N

AK


Digitizing an Analog Signal

fed through a DAC

ADC

DAC

LPF


Nyquist Criterion

In order to avoid loss of information, the incoming signal must be sampled at a rate greater than two times the highest frequency component in the incoming signal.

Example: CD Audio, FSAMPLING = 44 KHz since FMAX = 22 KHz

A signal alias is produced by sampling the signal at a rate less than the minimum rate (twice the highest frequency).

SAMPLING MAXF 2 F


An Alias Signal Due to Under-Sampling

Sine wave frequency is 1.9 KHz. This signal is sampled every 500 s (FSAMPLING = 2 KHz). Data samples are indicated by square dots. These square dots form a sinusoidal waveform with a period of 10 ms or a frequency of 100 Hz.. The alias frequency is the difference between the sampling frequency and the frequency of the incoming signal.


Digital-Ramp ADC


Three-Bit Flash ADC3 K

1 K

1 K

1 K

1 K

1 K

1 K

1 K


Four-Bit Successive-Approximation ADC


Example Problems1) An eight-bit digital ramp ADC with a 40 mV resolution uses a clock

frequency of 2.5 MHz. Determine the following values:a) the digital output for an analog voltage of 6.005 Vb) the digital output for an analog voltage of 6.035 Vc) the maximum and average conversion times

a) 6.005 V / 40 mV = 150.125 = 15110 = 100101112.

b) Using same method as in (a) the digital value is again 100101112.

c) Maximum conversion time = (max. # of steps) x (TCLOCK) tmax_conv = (28-1) x (0.4µs) = 102µs. Average conversion time = 102µs/2 = 51µs


Example Problems

2) Why were the digital outputs the same for parts a) and b) of question 1?

Because the difference in the two values of VA was smaller than the resolution of the converter.


Example Problems3) An ADC has the following characteristics: resolution of 12

bits, full scale error of 0.03%, and full scale input of 5 V. What is the quantization error in volts? What is the total possible error in volts?

With 12 bits, percentage resolution is (1/(212-1)) x 100% = 0.024%.

Thus, quantization error = 0.024% x 5V = 1.2mV.

Error due to 0.03% inaccuracy is0.03% x 5V = 1.5mV.

Total Error = 1.2mV + 1.5mV = 2.7mV.


Example Problems

4) A data acquisition system is being used to digitize an audio signal. The sampling frequency is 20 KHz. Determine the output frequency that will be heard for each of the following input frequencies?

a) 5 KHz < FMAX, 5 KHzb) 10.1 KHz > FMAX, 9.9 KHzc) 10.2 KHz > FMAX, 9.8 KHzd) 15 KHz > FMAX, 5 KHze) 19.1 KHz > FMAX, 900 Hzf) 19.2 KHz > FMAX, 800 Hz


Example Problems5) The figure below shows the waveform at VAX for a 6-bit successive

approximation ADC with a step size of 40 mV during a complete conversion cycle. Examine this waveform and describe what is occurring at times t0 to t5. Then determine the resultant digital output.


Example Problems5)

Full scale input = (26-1) 40mV = 2.52V

t0: Set MSB (bit 5); t1: Set bit 4; clear bit 4; t2: Set bit 3; clear bit 3;

t3: Set bit 2; t4: Set bit 1; clear bit 1; t5: Set LSB;

Digital result = 1001012 = 3710 Thus 1.48 V < VA < 1.52 V


ADC0804 Eight-Bit Successive-Approximation ADC with Tri-State Outputs


ADC0804 Block Diagram


ADC0804 Specifications• It has two analog inputs, VIN(+) and VIN(-), to allow

differential inputs.

• Eight bit resolution at the output. The digital outputs are tri-state buffered for bus interfacing.

• VREF/2 pin is for a precision voltage source.

• Separate ground connections for digital and analog voltages (for noise considerations).

• It has an internal Schmitt Trigger oscillator that can be configured with an external R and C for self-clocking or an external clock can be used. Typical clock frequency is 640 KHz. Higher frequencies possible but error increases.

• Typical conversion time is 100 s or 0.1 ms.


ADC0804 Control PinsINPUTS

• Chip Select, , must be LOW for and inputs to have any

effect. With HIGH, the digital outputs are in the Hi-Z state and

no conversions can take place.

• READ, , must be LOW to enable the digital output buffers.

• WRITE, , when a LOW pulse is received at this input, a new

conversion starts.

OUTPUT

• INTERRUPT, , will go HIGH at the start of a conversion and

will return LOW to signal the end of a conversion.

CS RD

CS

WR

RD

WR

INTR


Self-Clocking the ADC0804

sampling rate = conversion rate = fCLK/64.


An Application of an ADC0804


MSB

LSB

8 Clocks

ADC Circuit in Free Running Mode

sampling rate = conversion rate = fCLK/72


Appendix: Schmitt-Trigger Inverter

(a) If input transition times are too long, a standard logic device-output might oscillate or change erratically; (b) a logic device with a Schmitt-trigger type of input will produce clean, fast output transitions.


Schmitt-Trigger Inverter Operation

• As VIN increases, VOUT = VOH until VIN > VTH then VOUT = VOL

• When VIN begins to decrease, VOUT = VOL until VIN < VTL then VOUT = VOH

VOH

VOL

VTL VTH

VOUT

VIN


Schmitt-Trigger Oscillator

IIN


Analysis of a Schmitt-Trigger Oscillator

Capacitor Discharging Capacitor Charging

VC(t) VTH

VTL

VOH

VOUT(t) VOL

t

t

TL TH

Assume Iin = 0, thus IR(t) = IC(t)

t = 0 t = 0'

VOL

VC(t)VOH

VC(t)


Analysis of a Schmitt-Trigger OscillatorContinued

Capacitor Discharging Capacitor Charging

I.C. (0)

( )

( ) ( )

( ) ( )

( )

ln( )

tRC

TLRC

TH OL

TL OL

C TH

C L TL

OL C C

C OL OL TH

TL OL OL TH

V VL V V

V V

V T V

V V t dV tC

R dt

V t V V V e

V V V V e

T RC

I.C. (0 )

( )

( ) ( )

( ) ( )

( )

ln( )

tRC

THRC

OH TL

OH TH

C TL

C H TH

OH C C

C OH OH TL

TH OH OH TL

V VH V V

V V

V T V

V V t dV tC

R dt

V t V V V e

V V V V e

T RC

1 1 , H

L H

TOSC T T T Tf Duty Cycle


Example: Show how to use a 74LS14 Schmitt-trigger inverter to produce an approximate square wave with a frequency of 10 KHz.

Solution:


PSPICE Simulation of a Schmitt-Trigger Oscillator (7414)

ECE 3450 M. A. Jupina, VU, 2014 Analog-to-Digital and Digital-to-Analog Conversion Introduction...

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