ECE 341

Lecture # 3

Instructor: Zeshan Chishti

zeshan@ece.pdx.edu

October 7, 2013

Portland State University

Lecture Topics

• Counters

• Finite State Machines

• Decoders

• Multiplexers

• Reference: Appendix A of the textbook, sections A.8 to A.13.

Announcements

• Next class (Wednesday, Oct. 9) will start at 5:30PM

• Homework 1 due next class

Counters

• Counters are arithmetic circuits used for the purpose of counting – Can increment or decrement by 1 each cycle

• Counters often implemented with T flip-flops – Toggle feature naturally suited for counting operation

• Applications of counters – Count occurrences of certain events, for example, no. of add instructions

– Track elapsed time between events

– Generate control and timing signals, for example, to produce signals whose frequencies are multiples of original clock frequency

A 3-bit Up-counter

Counter Value

x2 x1 x0

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

Consider a 3-bit counter x2x1x0 shown in table. •The least significant bit x0 toggles at every increment of counter • x1 toggles on 1->0 transitions of x0 (half the rate of toggling of x0) • x2 toggles on 1->0 transitions of x1 (half the rate of toggling of x1)

A 3-bit Up-counter

Practice Exercise

• Design a 3-bit down counter with T flip-flops. How does the down counter circuit differ from the up-counter circuit?

A 3-bit Down-counter

Counter Value

x2 x1 x0

7 1 1 1

6 1 1 0

5 1 0 1

4 1 0 0

3 0 1 1

2 0 1 0

1 0 0 1

0 0 0 0

•The least significant bit x0 toggles at every decrement of counter • x1 toggles on 0->1 transitions of x0 • x2 toggles on 0->1 transitions of x1

Practice Exercise Solution

• Design a 3-bit down counter with T flip-flops. How does the down counter circuit differ from the up-counter circuit?

• Solution: – Two ways to convert the previous up-counter to a down-counter:

1. Either, replace the +ve edge-triggered T flip-flops with –ve edge-triggered T flip-flops

2. Or, connect the Q outputs (instead of NOT(Q) outputs) from previous flip-flops to clock inputs of next flip-flops

Asynchronous Counters

• The previous counter is an example of asynchronous counters. Also called ripple counters – Input clock only connected to one flip flop

– Clocks for other flip-flops are derived from outputs of previous flip-flops

• Asynchronous counters are slow because of cascaded clocking – The input clock pulse ripples from stage to stage

– Propagation delay of individual flip-flops limit speed of operation

• Solution: Synchronous sequential circuits (finite state machines)

Finite State Machines

• Recall that in a sequential circuit:

– Outputs depend both on present inputs and the sequence of previous inputs

• The state of a sequential circuit determines its behavior when various input patterns are applied

• A finite state machine model formally describes a sequential circuit

Inputs Outputs

Combinational Logic

Next State

Present State

Delay Elements (Flip-flops)

Synthesis of Finite State Machines

Synthesis of FSM involves the following steps:

• Step 1: Develop a state diagram or state table

– Depict how state transitions occur in response to input patterns

• Step 2: Determine # and types of needed flip flops

• Step 3: Determine state assignment (flip-flop values for each state)

• Step 4: Determine the state-assigned state table

• Step 5: Derive the logic expressions for next-state logic and outputs

• Step 6: Use the derived expressions to implement the circuit

Example: Up/Down Counter with D flip-flops

Problem Statement: Design a mod-4 counter which counts up or down depending on an input and has an output of 1 if the count is equal to 2

• States: 4 states (S0, S1, S2 and S3) corresponding to 4 count values

• Input: Variable x. Count up if x=0, down if x=1

• Output: Variable z. If present state is S2, then z=1, otherwise z=0;

State Diagram

S0/0 S1/0

S2/1 S3/0

x=0

x=0

x=0

x=0

x=1

x=1

x=1

x=1

State Table

Present State Next State Output z

x = 0 x = 1

S0 S1 S3 0

S1 S2 S0 0

S2 S3 S1 1

S3 S0 S2 0

Need 2 state variables to represent 4 states => use 2 D flip-flops

State-Assigned State Table

Present State Next State Output z

x = 0 x = 1

y2y1 Y2Y1 Y2Y1

00 01 11 0

01 10 00 0

10 11 01 1

11 00 10 0

• State variables y1 and y2 used to express each state as a 2-bit number y2y1

• We choose the following state assignment S0=00, S1=01, S2=10, S3=11

xyyY 122Logic Expressions

11 yY

12yyz

Next state

Output

Logic Circuit

xyyY 122Logic Expressions

11 yY

12yyz

Next state

Output

Decoder

• Decoder is used to decode encoded information

• A decoder has n data inputs and 2n outputs

• For any input data combination, a unique output line has logic value 1 and all the other outputs have the value 0 (one-hot encoding)

• Example: Consider an instruction which performs 8 different functions. A 3-bit field may be used to denote 1 out of the 8 possible functions. A 3-to-8 decoder would decode any instance of the instruction to determine the desired function

……

n

inputs

…………

2n outputs

n-to-2n decoder

2-to-4 Decoder Circuit

x0

x1

y0

y1

y2

y3

x0 x1 Active Output

0 0 y0

0 1 y1

1 0 y2

1 0 y3

x0

x1

y3

y2

y1

y0

BCD to Seven-Segment Display Decoder

• In typical decoders, only one output line asserted for an input combination

• There are other special decoders, where multiple lines may be asserted

• Example: BCD (binary-coded decimal) to seven-segment display decoder

– Input: a 4-bit BCD digit

– Output: 7 bits (a through g) corresponding to 7 display segments

– Any number from 0 to 9 can be displayed by turning some lights on and others off

– Multiple outputs may be asserted at once

• E.g., if input is 0100 (digit 4): b, c, f and g are on

– See Figure A.36 in book for truth table and circuit

d

a

b

c e

f g

Multiplexer

• A multiplexer (MUX) circuit has:

– 2k data inputs

– k select inputs

– One output

• A MUX passes the signal value on one of its data inputs to the output based on the value of the select signals

– Can be used for gating of data that may come from many different sources

…………

2k data inputs Output

k select inputs

…

MUX Multiplexer Symbol

A 4-Input Multiplexer

z 4-input MUX

w0 w1

x0

x1

x2

x3

w0 w1 z

0 0 x0

0 1 x1

1 0 x2

1 1 x3

• Logic circuit implementation shown in Figure A.37 • Example usage: A register can be loaded from one of four distinct sources by using a 4-input MUX

103102101100 wwxwwxwwxwwxz

Logic Functions using MUXes

• MUXes can be used to synthesize logic functions

• Example: Consider a function f of 3 input variables x0, x1 and x2 defined by following truth table. This function can be synthesized with a 4-input mux

x0 x1 x2 f

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

x0 x1 f

0 0 0

0 1 X2

1 0 1

1 1 NOT(x2)

Logic Functions using MUXes

• MUXes can be used to synthesize logic functions

• Example: Consider a function f of 3 input variables x0, x1 and x2. This function can be synthesized with a 4-input mux

x0 x1 x2 f

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

MUX

x0 x1

0

x2

1

NOT(x2)

f

Practice Problem

• Synthesize the function f1 in the following truth table by using a 4-input mux with y1 and y2 as selector inputs.

y0 y1 y2 f1

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

Solution

• Transform the truth table to use y1 and y2 as inputs

y0 y1 y2 f1

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

y1 y2 f1

0 0 0

0 1 1

1 0 NOT(y0)

1 1 1

Solution

• 4-input MUX with y1 and y2 as selector inputs

y0 y1 y2 f1

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

MUX

y1 y2

0

1

NOT(y0)

1

f1