ECE 340 Lecture 37 : Metal- Insulator-Semiconductor...

ECE 340 Lecture 37 : Metal-

Insulator-Semiconductor FET

Class Outline: • Metal-Semiconductor Junctions • MOSFET Basic Operation • MOS Capacitor

• What is the difference between an ohmic contact and a rectifying contact? • What is a MOSFET? • What are the transfer

characteristics when VG changes? • What are the transfer

characteristics when VD changes? M.J. Gilbert ECE 340 – Lecture 37 11/30/12

Things you should know when you leave…

Key Questions

M.J. Gilbert ECE 340 – Lecture 37 11/30/12

Metal-Semiconductor Junctions

Now let’s bring the metal and semiconductor together… E0

ФM > ФS

Metal Semiconductor N-type

ФS EC

EFS

EV

EFM

Χ ФM

Ei

EV

EC

Ei

ФB

EF

• When the materials are brought into contact with one another, they are not in equilibrium (EFS ≠ EFM).

• Electrons begin moving from the semiconductor to the metal.

• The net transfer of electrons leaves a reduced electron concentration in the semiconductor and the barrier between the materials grows.

• Process continues until Fermi level is constant.

χ−Φ=Φ MB

Surface potential energy barrier for electrons.



What happens if ФM < ФS?

ФM < ФS


ФS

EC

EFS

EV

EFM

Χ ФM

Ei

EV

EC

Ei EF

• When the materials are brought into contact with one another, they are not in equilibrium (EFS ≠ EFM).

• Electrons begin moving from the metal to the semiconductor.

• The net transfer of electrons from the metal into the semiconductor leaves a net excess of electrons at the surface.

• Process continues until Fermi level is constant.



But the point of adding contacts was to apply fields, let’s look at this…

ФM > ФS


V Apply positive bias, V…

EV

EC

Ei

EFS

Current

EFM

•  This lowers EFM below EFS and reduces the barrier seen by electrons.

•  Current begins to flow from the semiconductor to the metal.

•  Continue to raise the positive bias and more electrons will have enough energy to surmount the barrier and contribute to current flow.



What happens if we apply a negative bias to the contact…

ФM > ФS


V Apply increasingly negative bias, V…

EV

EC

Ei

EFS

Current

EFM

•  This lowers EFS below EFM and increases the barrier seen by electrons.

•  Current flow from the semiconductor is blocked by the large potential barrier.

•  Only a small leakage current may flow from the metal to the semiconductor.



What happens when we reverse the relationship between the workfunctions?

ФM < ФS


EV

EC

Ei

V

EFS EFM

Positive bias…

EV

EC

Ei

EFM

EFS Current

Negative bias…

Current I

V


MOSFET Basic Operation

What is a MOSFET?

• MOSFET is an acronym which stands for Metal Oxide Semiconductor Field Effect Transistor.

• N+ source and drains are implanted into a relatively lightly doped p-type substrate (n-channel).

• Can also be made with n-type substrates and p-type source and drain (p-channel).

• Thin oxide layer separates the conducting gate region from the conducting gate region.

• Oxide regions are on either side of the MOSFET to isolate it from other devices in the integrated circuit.

• This device forms the backbone of much of the digital logic used in microprocessor technology today.



Is there a current flowing? Let’s check the energy bands…

EF

EC

EV

n n p • No current flows between the source and the drain in equilibrium.

• The p-type region separating creates built-in electric fields which creates a large potential barrier.

• So, how do we get current to flow from the source to the drain?



Let’s start applying bias to the MOSFET… Let’s begin with an n-type MOSFET • N-type source and drain and P-type channel. • Apply a small positive drain voltage (VD) to try to draw a current from the source to the drain. • Positive charge on gate draws electrons towards the gate forming a channel which allows current to flow from the source to the drain.

VG

VD

- - - - - -

++++ ++++++++++ + ++

- - - - - -

EF

EC

EV

n n p qVG



So as we vary the gate voltage, what does the current look like? ++++ ++++++++++ + ++

- - - - - -

Depletion Region Channel Region

VG

• When the barrier region is sufficiently reduced, then a current flows from the source to the drain.

• As we put more positive charge on the gate, more holes are repelled depleting the concentration near the surface and populating it with electrons. • The point in the gate voltage sweep when significant current begins to flow is the threshold voltage, VT. • This corresponds to the point when the channel is formed under the gate. • Were we to have made a PNP device the application of a negative VG would repel electrons and attract hole forming a channel.



What if we sweep the drain voltage??

- - - - - -

Depletion Region Channel Region

++++ ++++++++++ + ++ VD

• With VD swept in small positive increments, the channel merely acts like a resistor and the drain current is proportional to the drain voltage. • Past a few tenths of a volt of bias, the voltage drop from the source to the drain associated with current flow begins to negate the inverting effect of the gate. • Channel carriers begins to decrease leading to a reduction in the channel conductivity. This is due to the electron flow not being through the channel but a larger region about the drain.

• Drain current is said to be in saturation as changes in VD produce no changes in ID.

Pinch off



What do we know about a MOSFET so far?

No channel formed at VG = 0 V.

Channel formed at VG = 0 V.

What if we use n+-n-n+ instead??

Enhancement mode

Depletion mode



What do we know about a MOSFET?

- - - - - -

+ + + + + + + + + + + + +

P-MOS N-MOS

B.S. Doyle et al., IEEE TED (2003)

For NMOS: • For current to flow VGS > VT • Enhancement mode: VT > 0 • Depletion mode: VT < 0

• Transistor is on when VG = 0 V. For PMOS: • For current to flow VGS < VT • Enhancement mode: VT < 0 • Depletion mode: VT > 0

• Transistor is on when VG = 0 V.

P-type Si

N-type Si



Using MOSFETs for logic…

P-‐MOS

N-‐MOS

ip

in

iout

Input (A) Output (Q)

1 (Vdd) 0 (Vss)

0 (Vss) 1 (Vdd)

• We can string multiple MOSFETs together to trace out logical functionality.

• CMOS (Complementary Metal Oxide Semiconductor) Logic

• Left, we show the simple connection method for different devices on the same wafer.

• Below, the connection scheme for a logical inverter.

0 1 0 1



But from a MOSFET to a microprocessor…

12” wafer filled with 100s of die.

Single die after removal and packaging.

Contents of single die before packaging.

Cross section of single element. Single transistor


Ideal MOS Capacitor

But we saw that the operation in most regimes was controlled by the channel… The channel of a MOSFET is an example of a MOS capacitor…

What is the structure of a MOS capacitor? • Heavily doped polycrystalline Si film as the gate electrode material.

• N-type for “n-channel” transistors (NMOS). • P-type for “p-channel” transistors (PMOS).

• SiO2 as the gate dielectric • Band gap = 9 eV. • Relative dielectric constant εr = 3.9.

• Si as the semiconductor material. • P-type for n-channel devices. • N-type for p-channel devices.

Useful for: • Digital and analog logic • Memory functionality • Imaging (CCD) and displays (LCD)


Ideal MOS Capacitor

Remember all of the components…

•  Charges only exist at the surface of the metal.

•  We assume that there are no charges or dopants located in the oxide region.

•  We cannot achieve thermal equilibrium through the oxide layer.

•  To achieve thermal equilibrium we need to use a wire to connect the metal to the semiconductor.

Let’s start with the ideal situation, ФM = ФS


Ideal MOS Capacitor

Let’s now apply a negative gate voltage to our MOS capacitor…

•  Applying a negative gate voltage deposits negative charge on the metal.

•  We expect to see this charge compensated by a net positive charge on the semiconductor.

•  The applied negative voltage depresses the potential of the metal.

•  As a result the electron energies are raised in the metal relative to the semiconductor.

•  Moving EFM up causes a tilt in the oxide bands and the semiconductor bands

( )dxdE

qxE i1=

TkEE

ib

Fi

enp−

=

More holes accumulate at the surface of the semiconductor.


Ideal MOS Capacitor

Now apply a positive gate voltage…

•  Deposition of positive charge on the gate requires compensation by negative charges in the semiconductor.

•  The negative charge in a p-type semiconductor arises from the depletion of holes from the surface.

•  This leaves behind uncompensated ionized acceptors.

•  The bands bend downward near the semiconductor surface (EI closer to EF).

What happens if we keep increasing the amount of positive gate voltage we apply to the metal relative to the semiconductor?

Increased electron concentration


Ideal MOS Capacitor

•  Define a potential qφS which determines how much band bending there is at the surface.

•  When qφS = 0 we are in flat band condition.

•  When qφS < 0 we have hole accumulation at the surface.

•  When qφS > 0 we have electron accumulation at the surface.

•  When qφS > qφF we have inversion at the surface.

•  Surface should be as strongly n-type as the body is p-type.

When VG is large enough, the surface is inverted. The n-type surface that forms as a result of the applied electric field is the key to transistor operation!

FbulkIF EEq −=φ

⎟⎟⎠

⎞⎜⎜⎝

⎛==

i

AbF

INVS n

NqTk ln22φφ

⎟⎟⎠

⎞⎜⎜⎝

⎛==

i

DbF

INVS n

NqTk ln22φφ

ECE 340 Lecture 37 : Metal- Insulator-Semiconductor...

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