ECE 331 – Digital System Design Transistor Technologies, and Realizing Logic Gates using CMOS...

ECE 331 – Digital System Design

Transistor Technologies,and

Realizing Logic Gates using CMOS Circuits

(Lecture #23)

ECE 331 - Digital System Design 2

Transistor Technologies

Two transistor technologies:

1. Transistor-Transistor Logic (TTL)2. Metal Oxide Semiconductor (MOS)


TTL Technology

TTL = Transistor-transistor Logic Dominant technology prior to the emergence of

CMOS technology. Not as suitable for large-scale integration as

CMOS technology. Largely obsolete for new designs.

Good for labs and educational use because it is more robust than CMOS.


TTL Technology Bipolar Junction Transistor (BJT)

Base – controls current flow in transistor Collector – current flow enters transistor Emitter – current flow exits transistor

npn BJT Collector, Emitter: n-type semiconductor Base: p-type semiconductor

pnp BJT Collector, Emitter: p-type semiconductor Base: n-type semiconductor


MOS Technology CMOS

Complementary Metal Oxide Semiconductor NMOS

N-channel MOSFET PMOS

P-channel MOSFET MOSFET

Metal Oxide Semiconductor Field Effect Transistor


Drain Source

x = "low" x = "high"

(a) A simple switch controlled by the input x

V D V S

(b) NMOS transistor

Gate

(c) Simplified symbol for an NMOS transistor

V G

Substrate (Body)

NMOS Transistor


NMOS Transistor

Four-terminal device Simplified three-terminal representation

Conducting channel is N-type material Drain pulled high (connected to supply voltage)

in digital circuits Source pulled low (connected to ground) in

digital circuits


NMOS Transistor

Gate-to-Source Voltage (VGS

)

Controls the drain current (iD) via an electric

field Oxide (silicon dioxide) insulates the gate from

the drain and the source i

G ~= 0 Amps

iD ~= i

S

Low power


NMOS Transistor

Operates as a binary switch in digital circuits V

G = 0V (V

S = GND = 0V)

VGS

~= 0V

“looks like” an open switch (in the cutoff region; “off”)

ID = I

S = 0A

VG = VDD (V

S = GND = 0V)

VGS

~= VDD

“looks like” a closed switch (in the saturated region; “on”)


Gate

x = "high" x = "low"

(a) A switch with the opposite behavior of the NMOS transistor

V G

V D V S

(b) PMOS transistor

(c) Simplified symbol for a PMOS transistor

V DD

Drain Source

Substrate (Body)

PMOS Transistor


PMOS Transistor

Four-terminal device Three-terminal simplified representation

Conducting channel is P-type material Drain pulled low (connected to ground) in digital

circuits Source pulled high (connected to supply

voltage) in digital circuits


PMOS Transistor

Gate-to-Source Voltage (VGS

)

Controls the drain current (iD) via an electric

field Oxide (silicon dioxide) insulates the gate from

the drain and the source i

G ~= 0 Amps

iD ~= i

S

Low power


PMOS Transistor

Operates as an binary switch in digital circuits V

G = 0V (V

S = VDD = Supply Voltage)

VGS

~= -VDD (VSG

~= VDD)

“looks like” an closed switch (in the saturated region; “on”)

VG = VDD (V

S = VDD = Supply Voltage)

VGS

~= 0V (VSG

= 0V)

“looks like” a open switch (in the cutoff region; “off”)

ID = I

S = 0A


(a) NMOS transistor

V G

V D

V S = 0 V

V S = V DD

V D

V G

Closed switch when V G = V DD

V D = 0 V

Open switch when V G = 0 V

V D

Open switch when V G = V DD

V D

V DD

Closed switch when V G = 0 V

V D = V DD

V DD

(b) PMOS transistor

NMOS and PMOS Transistors


V f

V DD

Pull-down network

Pull-up network

V x 1

V x n

(PUN)

(PDN) NMOS transistors

PMOS transistors

CMOS Logic Circuit


Voltage Levels in CMOS Circuits

Voltages are used to represent Logic values in CMOS (and TTL) circuits:

Logic 1 = VDDLogic 0 = GND


Voltage Ranges in CMOS Circuits

Logic value 1

Undefined

Logic value 0

Voltage

V DD

V 1,min

V 0,max

V SS (Gnd)


CMOS Logic Beneficial to use NMOS and PMOS in same design

No steady state drain (or gate) current Low power dissipation

Configuration of NMOS and PMOS transistors For Output of CMOS circuit = Logic 0

PDN (NMOS transistors) ON PUN (PMOS transistors) OFF

For Output of CMOS circuit = Logic 1 PDN (NMOS transistors) OFF PUN (PMOS transistors) ON


(a) Circuit

V f

V DD

V x

(b) Truth table and transistor states

T 1

T 2

on

off

off

on

1

0

0

1

f x T 1 T 2

CMOS Circuit: Inverter (NOT)


CMOS Circuit: NAND Gate

(a) Circuit

V f

V DD


on

on

on

off

0

1

0

0

1

1

0

1

off

off

on

off

off

on

f

off

on

1

1

1

0

off

off on

on

V x 1

V x 2

T 1 T 2

T 3

T 4

x 1 x 2 T 1 T 2 T 3 T 4


CMOS Circuit: NOR Gate

(a) Circuit

V f

V DD


on

on

on

off

0

1

0

0

1

1

0

1

off

off

on

off

off

on

f

off

on

1

0

0

0

off

off on

on

V x 1

V x 2

T 1

T 2

T 3 T 4

x 1 x 2 T 1 T 2 T 3 T 4


V f

V DD

V x 1

V x 2

V DD

CMOS Circuit: AND Gate

NAND Gate

Inverter


CMOS Circuit: OR Gate


CMOS Circuits

Analysis


The functional behavior of a CMOS circuit can be determined by analyzing the behavior of the

individual PMOS and NMOS transistors, and, thus, the behavior of the PUN and PDN.

CMOS Circuits: Analysis


CMOS Circuits: Analysis (Steps)

• Determine the state of each transistor for each input combination.

• Determine the output of the CMOS circuit for each input combination.

• Derive the corresponding Truth Table

• Determine the Boolean Expression that defines the behavior of the CMOS circuit.


Example #1:

Analyze the following CMOS circuit to determine the logic function that it implements.



CMOS Circuit: Analysis (Ex. #1)


Example #2:

Analyze the following CMOS circuit to determine the logic function that it implements.



CMOS Circuit: Analysis (Ex. #2)

ECE 331 – Digital System Design Transistor Technologies, and Realizing Logic Gates using CMOS...

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