ECE 311 Digital Electronics

Final Project

CMOS Half Adder

Components and Equipment

CD4007UB CMOS Dual Complimentary Pair plus Inverter

LTspice IV version 4.13a

Agilent Technologies Infinvision Mixed Signal Oscilloscope M50-X2004A

Trus RMS Multimeter M9803R

RSR DC Power Supply Hy3002-3

Bread Board

Objective:

The objective of the final project is to design, implement and evaluate a half-adder at the

transistor level. For this project, CD4007 ICs will be used to build the logic circuit. The

half-adder is first designed and simulated using LTspice IV making sure to use the

parameters for a CD4007 and not LTspice’s default PMOS and NMOS parameters.

Finally, the half-adder is physically implemented on a bread board using the CD4407 IC

and evaluated using a signal oscilloscope and DC power source to compare speeds and

margins with the half-adder that was designed in LTspice.

Procedure:

o Design Process

- Transistors as logic gates:

The CMOS inverter is one of the most popular logic inverters used today. This is

because the CMOS configuration most closely approaches the ideal logic inverter

transfer characteristic. A CMOS inverter is made using an n-channel and p-

channel MOSFET connected in series and driven simultaneously as show in Fig-1

below.

Fig-1

CMOS’s are also favored over other transistors because of their high noise

immunity and low static power consumption. Significant power is only drawn

when the transistors are switching states between on and off. The inverter in Fig-1

works by creating either a path from VDD (DC power source-logic high) or VSS

(ground-logic low) to V_out. When V_in is larger than the threshold voltage

(Vtr), the p-channel device will be in cutoff (off) and the n-channel device will be

in the constant current region (on) creating a conduction path from VSS (0V in

this circuit) to V_out. This means that the output will be 0V or just 0 which is the

output expected from an inverter with logic 1 input. Conversely, when V_in is

below Vtr, the p-channel device will be in constant current and the n-channel will

be in cutoff creating a path from VDD (5V in this circuit) to V_out giving us logic

high. The internal resistance of MOSFETs is very small so the circuit loses little

power when it is in a logic high state.

- Half-Adder:

The half-adder is digital circuit that adds two one-bit binary numbers and

produces a sum bit and carry-out bit. The carry-out bit is theoretically passed to

the next addition like the “carry” does in arithmetic addition. Fig-2 and Fig-3

below show the schematic and logic diagram of a half-adder respectively.

Fig-3

Fig-2

As shown above, the half-adder uses an “AND” gate and an “XOR” gate. The

truth tables for these two gates are shown below.

Fig-4 AND truth table Fig-5 XOR truth table

To implement the logic required the n-channel and p-channel MOSFET’s must be

connected in way that will produce the desired output. For the AND gate the

CMOS should only have a conducting path to VDD (logic high) when BOTH

inputs are at high voltages (logic high) and will have a conducting path to ground

for all other input voltages. The XOR gate must have one input at a high voltage

and one at low in order to produce a logic high output. The CMOS designs for

these gates are shown on the next few pages.

AND gate:

XOR gate:

o Design Simulation: With the design of the half-adder complete, the circuit is now ready to be built and simulated using LTspice IV version 4.13a. Recall that the parameters for the CD4007 IC must be entered into LTspice. The code that will do this is given below. There is one for the NMOS and one for the PMOS on the CD4007.

Code for PMOS:.model CD4007P PMOS(Level=1 Gamma=0.6 Tox=1200n Phi=.6 Rs=0 Kp=55u Vto=-1.5 Lambda=0.04 Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8 Cgso=0.2p Cgdo=0.2p Is=16.64p N=1)

Code for NMOS:.model CD4007N NMOS(Level=1 Gamma=0.6 Tox=1200n Phi=.6 Rs=0 Kp=111u Vto=2.0 Lambda=0.01 Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 Cgso=0.1p Cgdo=0.1p Is=16.64p N=1)

After the parameters are set the circuit can built in exactly the same way it was designed above. When building the circuit the bodies of both the NMOS and PMOS have to be manually connected to VSS and VDD respectively. The schematic for the half-adder designed in LTspice IV is show below in Fig-6.

Fig-6

Half-Adder Simulations:

A square wave with amplitude of 5V is used as the inputs A and B. A has a period twice as long as B so as to simulate all four possible logic combinations 00, 01, 10, 11. The small spikes on the V(sum) wave are due to the transitions from Vb and Va going from low to high at the same time.

When zoomed in on the simulation you can see the rise time of V(sum) and the fall time of V(carryout).

From the graph above we see that the rise time for V(sum) is approximately 260ns and the fall time for V(carryout) is approximately 60ns.

The next graph is used to find the fall time of V(sum):

From the graph above the fall time of V(sum) is approximately 200ns.

The graph for the rise time of V(carryout):

From the graph above the rise time of V(carryout) is approximately 90ns.

o Build: To physically implement the half-adder three CD4007 ICs were used. The pin layout for the CD4007 IC is shown below in Fig-7:

Fig-7 The pin connections for the AND gate is shown below in Fig-8:

The pin connections for the XOR gate is shown below in Fig-9

Fig-9

Here is picture of what the half-adder looks like on the bread board.

To test functionality of circuit, A DC power source was used for input ‘B’ and a square-wave pulse from the function generator is used for input ‘A’. With ‘B’ set to zero and ‘A’ cycling between 5V and 0V, the output waveform of the circuit looks like the following.

Signal key:

1=’A’ 2=’B’ 3=’Sum’ 4=’carryout’

When ‘B’ is on (5V)

The rise and fall time for the XOR gate are shown below:

The rise and fall time for the AND gate is shown below:

o Analysis As was expected the physical circuit did not perform as well as the simulation said the circuit would behave but was quite comparable. A table of the data taken from simulation in LTspice and the test data retrieved from the physical implementation are showed below.

LTspice simulation Physical circuitAND (Carryout) Rise = 90ns AND (Carryout) Rise = 154ns

Fall = 60ns Fall = 104nsXOR(Sum) Rise = 260ns XOR (Sum) Rise = 326ns

Fall = 200ns Fall = 192ns

Some possible reasons for the discrepancies in rise and fall time could be due to the manufacturing of the batch of CD4007 ICs used in the project. Other possible causes are the non ideal properties of the materials used and the accuracy of the oscilloscope.

o Conclusion The data provided in this project further validate the use of CMOS logic gates. The relationship between ideal functionality and actual functionality make the CMOS one of the preferred methods for building logic gates today.