EC7451: MICROPROCESSOR AND MICROCONTROLLER II - 8086 Microprocessor_28Jan2020.pdf8086 Microprocessor...

EC7451: MICROPROCESSOR AND MICROCONTROLLER

Dr. V. SATHIESH KUMAR Department of Electronics Engg., MIT1

Presentation Slides:

www.sathieshkumar.com/tutorials

Unit II : 16-BIT MICROPROCESSOR1. Architecture and pin details of 80862. Instruction Set3. Addressing Modes4. Minimum and Maximum mode configuration5. Assembler Directives, 6. Assembly Language Programming, 7. Interrupts8. Features of 80186, 80286, 80386, and 80486

TEXT BOOKK M Bhurchandi, A K Ray, “Advanced Microprocessors andPeripherals". Third edition, Tata McGraw Hill Publishing. 2013.

Presented By,

Dr. V. Sathiesh Kumar Department of Electronics Engg.,

MIT-Anna University

EC7451: MICROPROCESSOR AND MICROCONTROLLER UNIT II – 8086


8086 Microprocessor Features:

1. It is a 16-bit Microprocessor having 20 address lines and 16 data lines that

provides up to 1MB storage.

2.It consists of powerful instruction set, which provides operations like multiplication

and division.

3.It supports two modes of operation, i.e. Maximum mode and Minimum mode.

Maximum mode is suitable for system having multiple processors and Minimum

mode is suitable for system having a single processor.

4. It has an instruction queue, which is capable of storing six instruction bytes from

the memory resulting in faster processing.

5.It is available in 4 versions based on the frequency of operation −

8086 → 5MHz

8086-2 → 8MHz

8086-1 → 10 MHz

8086-4 → 4 MHz



8086 Microprocessor Features:

6. It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which

improves performance.

7.Fetch stage can pre-fetch up to 6 bytes of instructions and stores them in the

queue.

8.Execute stage executes these instructions.

9.It has 256 vectored interrupts.

10.It consists of 29,000 transistors.



Comparison between 8085 and 8086 Microprocessors:

1.Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.

2.Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus.

3.Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of

memory.

4.Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an

instruction queue.

5.Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a

pipelined architecture.

6.I/O − 8085 can address 28 = 256 I/O's, whereas 8086 can access 216 = 65,536 I/O's.

7.Cost − The cost of 8085 is low whereas that of 8086 is high.

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8086 Microprocessor Architecture: Register Organization

•Has a powerful set of registers known as general purpose and special purpose

registers.

•All of them are 16-bit registers.

•The general purpose registers, can be used as either 8-bit registers or 16-bit

registers.

•They may be either used for holding data, variables and intermediate results

temporarily or for other purposes like a counter or for storing offset address for

some particular addressing modes etc.


Dr. V. SATHIESH KUMAR Department of Electronics Engg., MIT

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8086 Microprocessor Architecture: Register Organization – General Data Register

• The registers AX, BX, CX and DX are the general purpose 16-bit registers.

•AX is used as 16-bit accumulator, with the lower 8-bits of AX designated as AL and

higher 8-bits as AH.

•AL can be used as an 8-bit accumulator for 8-bit operations.

•Usually the letters L and H specify the lower and higher bytes of a particular register.

•The letter X is used to specify the complete 16-bit register.

•The register CX is also used as a default counter in case of string and loop

instructions.

•The register BX is used as an offset storage for forming physical addresses in case of

certain addressing modes.

•DX register is a general purpose register which may be used as an implicit operand

or destination in case of a few instructions.



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8086 Microprocessor Architecture: Register Organization – General Data Register



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8086 Microprocessor Architecture: Register Organization – Segment Registers

• Unlike 8085, the 8086 addresses a segmented memory.

•The complete 1 megabyte memory, which the 8086 addresses is divided into 16

logical segments.

•Each segment thus contains 64 Kbytes of memory.

•The special purpose registers are used as segment registers, pointers, index

registers or as offset storage registers for particular addressing modes.

•There are four segment registers (Code Segment Register – CS, Data Segment

Register – DS, Extra Segment Register – ES and Stack Segment Register - SS).

•The code segment register is used for addressing a memory location in the code

segment of the memory, where the executable program is stored.

•Similarly, the data segment register points to the data segment of the memory,

where the data is resided.

•The extra segment register also refers to a segment which essentially is another data

segment of the memory.



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•The stack segment register is used for addressing stack segment of memory i.e.

memory which is used to store stack data.

•The CPU uses the stack for temporarily storing important data, e.g. the contents of

the CPU registers which will be required at a later stage.

•The stack grows down, i.e. the data is pushed onto the stack in the memory locations

with decreasing addresses.

•When this information is required by the CPU, they will be popped off from the stack.

•While addressing any location in the memory bank, the physical address is

calculated from two parts, the first is segment address and the second is the

offset.

•The segment register contain 16-bit base addresses, related to different segments.

•Any of the pointers and index registers or BX may contain the offset of the

location to be addressed.



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•The advantage of this scheme is that instead of maintaining a 20-bit register for a

physical address, the processor just maintains two 16-bit registers which are within

the word length capacity of the machine.

•Thus the CS, DS, SS and ES segment registers, respectively, contain the segment

addresses for the code, data, stack and extra segments of the memory.

•Note: All these segments in RAM are the logical segments. They may or may not be

physically separated.

•In other words, a single segment may require more than one memory chip or more

than one segment may be accommodated ins a single memory chip.



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8086 Architecture: Register Organization – Pointers and Index Registers

•The pointers contain offset within the particular segments.

•The pointers IP, BP and SP usually contain offsets within the code (IP), and stack

(BP and SP) segments.

•The index registers are used as general purpose registers as well as for offset

storage in case of indexed, based indexed and relative based indexed addressing

modes.

•The register SI is generally used to store the offset of source data in data segment

while the register DI is used to store the offset of destination in data or extra

segment.

•The index registers are particularly useful for string manipulations.



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Flag Register:

•It is a 16-bit register, i.e. it changes its status according to the result stored in the

accumulator.

•It has 9 flags and they are divided into 2 groups − Conditional Flags and Control

Flags.



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Flag Register: Conditional Flags

•It represents the result of the last arithmetic or logical instruction executed.

1.Carry flag (Cy) − This flag is set when there is a carry out of MSB in case of

addition or a borrow in case of subtraction.

2.Auxiliary flag (Ac) − When an operation is performed at ALU, it results in a

carry/borrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7).

3.Parity flag (P) − This flag is used to indicate the parity of the result, i.e. when the

lower order 8-bits of the result contains even number of 1’s, then the Parity Flag is

set. For odd number of 1’s, the Parity Flag is reset.

4.Zero flag (Z) − This flag is set to 1 when the result of arithmetic or logical operation

is zero else it is set to 0.

5.Sign flag (S) − This flag holds the sign of the result, i.e. when the result of the

operation is negative, then the sign flag is set to 1 else set to 0. For signed

computations, the sign flag equals the MSB of the result.



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Flag Register: Conditional Flags

6.Overflow flag (O)− This flag is set if an overflow occurs, i.e. if the result of a

signed operation is large enough to be accommodated in a destination register.

Eg: In case of addition of two signed numbers, if the result overflows into the sign bit, i.e

the result is of more than 7-bits in size in case of 8-bit signed operations and more than

15-bits in size in case of 16-bit signed operations, then overflow flag will be set.



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Flag Register: Control Flags

•Control flags controls the operations of the execution unit.

1.Trap flag (T) − It is used for single step control and allows the user to execute

one instruction at a time for debugging. If it is set, then the program can be run in

a single step mode. In other words, a trap interrupt is generated after execution of each

instruction. The processor executes the current instruction and the control is transferred

to the Trap interrupt service routine.

2.Interrupt flag (I) − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the

interruption of a program. It is set to 1 for interrupt enabled condition and set to 0 for

interrupt disabled condition.

3.Direction flag (D)− It is used in string manipulation instructions. If this flag bit is 0, the

string is processed beginning from the lowest address to the highest address, i.e.

autoincrementing mode. Otherwise, the string is processed from the highest

address towards the lowest address, i.e. autodecrementing mode.



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8086 Architecture:

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8086 Microprocessor Architecture: BIU

8086 Microprocessor is divided into two functional units, i.e., BIU (Bus Interface

Unit) and EU (Execution Unit).

1. Bus Interface Unit (BIU): It contains the circuit for physical address calculations

and a pre-decoding instruction byte queue (6 bytes long).

•BIU takes care of all data and addresses transfers on the buses for the EU like

sending addresses, fetching instructions from the memory, reading data from the

ports and the memory as well as writing data to the ports and the memory.

•EU has no direct connection with System Buses.

•EU and BIU are connected with the Internal Bus.



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The complete physical address which is 20-bits long is generated using segment

and offset registers, each 16-bits long.

For example, if the segment address is 1005H and the offset is 5555H, then the

physical address is calculated as follows,



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Thus, the segmented addressed by the segment value 1005H can have offset values

from 0000H to FFFFH within it, i.e. maximum 64 K locations may be accommodated in

the segment.

Thus the segment register indicates the base address of a particular segment,

while the offset indicates the distance of the required memory location in the

segment from the base address.

Since the offset is a 16-bit number, each segment can have a maximum of 64 K

locations.

The BIU has a separate adder to perform this procedure for obtaining a physical

address while addressing memory.

The segment address value is to be taken from an appropriate segment register

depending upon whether code, data or stack are to be accessed, while the offset

may be the contents of IP, BX, SI, DI, SP, BP or an immediate 16-bit value,

depending upon the addressing mode.



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•It has the following functional parts −

1.Instruction queue − BIU contains the instruction queue.

•BIU gets up to 6 bytes of next instructions and stores them in the instruction

queue.

•When EU executes instructions and is ready for its next instruction, then it simply reads

the instruction from this instruction queue resulting in increased execution speed.

•Fetching the next instruction while the current instruction executes is

called pipelining.

• Once the opcode is fetched and decoded, the external bus remains free for some time,

while the processor internally executes the instruction.

•This time slot is utilized to achieve the overlapped fetch and execution cycles.

•While the fetched instruction is executed internally, the external bus is used to fetch the

machine code of the next instruction and arrange it in a queue known as pre-decoded

instruction byte queue. It is a 6 bytes long, first-in first-out (FIFO) structure.



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•Once a byte is decoded, the queue is rearranged by pushing it out and the queue

status is checked for the possibility of the next opcode fetch cycle.

•While the opcode is fetched by the Bus Interface Unit (BIU), the Execution Unit

(EU) executes the previously decoded instruction concurrently.

•The BIU along with the Execution Unit thus forms a pipeline.



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2. Segment register − BIU has 4 segment registers, i.e. CS, DS, SS and ES.

•It holds the addresses of instructions and data in memory, which are used by the

processor to access memory locations.

•It also contains 1 pointer register IP (16-bit register), which holds the address of

the next instruction to executed by the EU.

•CS − It stands for Code Segment. It is used for addressing a memory location in

the code segment of the memory, where the executable program is stored.

•DS − It stands for Data Segment. It consists of data used by the program and is

accessed in the data segment by an offset address or the content of other register

that holds the offset address.

•SS − It stands for Stack Segment. It handles memory to store data and addresses

during execution.

•ES − It stands for Extra Segment. ES is additional data segment, which is used by

the string to hold the extra destination data.



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8086 Microprocessor Architecture: EU

•The execution unit contains the register set of 8086 except segment registers and

IP.

•It has a 16-bit ALU, able to perform arithmetic and logic operations.

•The 16-bit flag register reflects the results of execution by the ALU.

•The decoding unit decodes the opcode bytes issued from the instruction byte queue.

•The timing and control unit derives the necessary control signals to execute the

instruction opcode received from the queue, depending upon the information made

available by the decoding circuit.

•The execution unit may pass the results to the bus interface unit for storing them

in memory.



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8086 Architecture: Memory Segmentation

•The memory in an 8086 is organized as segmented memory.

•In this scheme, the complete physically available memory may be divided into a

number of logical elements.

•Each segment is 64 K bytes in size and is addressed by one of the segment

registers.

•The 16-bit contents of the segment register actually point to the starting location

of a particular segment.

•To address a specific memory location within a segment, we need an offset

address.

•The offset address is also 16-bit long so that the maximum offset value can be

FFFFH, and the maximum size of any segment is thus 64K locations.

•The 8086 CPU is able to address 1Mbytes of physical memory.

•The complete 1Mbytes memory can be divided into 16 segments, each of 64Kbytes

size.The address of the segments may be assigned as 0000H to F000H, respectively.



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•The offset address values are from 0000H to FFFFH so that the physical addresses

range from 00000H to FFFFFH.

•Segments can be of two types,

1. Non-overlapping segments

2. Overlapping segments – Suppose a segment starts at a particular address and its

maximum size can be 64K bytes. But, if another segment starts before this 64K bytes

locations of the first segment, the two segments are said to be overlapping segments.

• The area of memory from the start of the second segment to the possible end of

the first segment is called an overlapped segment area.

•The locations lying in the overlapped area may be addressed by the same

physical address generated from two different sets of segment and offset

addresses.



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•The main advantages of the segmented memory scheme are as follows,

1. Allows the memory capacity to be 1MBytes although the actual addresses to be

handled are of 16-bit size.

2.Allows the placing of code, data and stack portion of the same program in different

parts (segments) of memory, for data and code protection.

3.Permits a program and/or its data to be put into different areas of memory each time

the program is executed, i.e. provision for relocation is done.



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8086 Microprocessor Pin Details:

• It is a 16-bit CPU available in four clock rates, i.e. 5, 4, 8 and 10 MHz, packaged in a

40 pin CERDIP or plastic package.

•8086 operates in single processor or multiprocessor configurations to achieve

high performance.

•Some pins serve a particular function in minimum mode (single processor mode)

and others function in maximum mode (multiprocessor mode) configurations.



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• The following signal descriptions are common to both the minimum and

maximum modes.

1. AD15 – AD0 : Time multiplexed memory or I/O address and data lines.

•Address remains on the lines during T1 state, while the data is available on the data

bus during T2, T3, Tw and T4.

•Here T1, T2, T3, T4 and Tw are the clock states of a machine cycle.

• Tw is a wait state.

•These lines are active high and float to a tristate during interrupt acknowledge

and local bus hold acknowledge cycles.



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2. A19/S6, A18/S5, A17/S4, A16/S3 : Time multiplexed address and status lines.

• During T1, these are the most significant address lines for memory operations.

•During I/O operations, these lines are low.

•During memory or I/O operations, status information is available on those lines for

T2, T3, Tw and T4.

•The status of the interrupt enable flag bit (displayed on S5) is updated at the

beginning of each clock cycle.

•The S4 and S3 together indicate which segment register is presently being used

for memory accesses.

•These lines float to tri-state off (tristated) during the local bus hold acknowledge.

• The status line S6 is always low (logical).

•The address bits are separated from the status bits using latches controlled by

the ALE signal.



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3. BHE*/S7 – Bus High Enable/Status : The bus high enable signal is used to indicate

the transfer of data over the higher order (D15 – D8) data bus.



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• It goes low for the data transfers over D15 – D8 and is used to derive chip selects of

odd address memory bank or peripherals.

•BHE* is low during T1 for read, write and interrupt acknowledge cycles, whenever

a byte is to be transferred on the higher byte of the data bus.

• The status information is available during T2, T3 and T4.

• The signal is active low and is tristated during ‘hold’.

•It is low during T1 for the first pulse of the interrupt acknowledge cycle.

•S7 is not currently used.

4. RD* - Read : Read signal, when low, indicates the peripherals that the processor

is performing a memory or I/O read operation.

• RD* is active low and shows the state for T2, T3, Tw of any read cycle.

•The signal remains tristated during ‘hold acknowledge’.



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5. READY : This is the acknowledgement from the slow devices or memory that

they have completed the data transfer.

• The signal made available by the devices is synchronized by the 8284A clock

generator to provide ready input to the 8086.

•The signal is active high.

6. INTR – Interrupt Request : This is a level triggered input.

• This is sampled during the last clock cycle of each instruction to determine the

availability of the request.

•If any interrupt request is pending, the processor enters the interrupt

acknowledge cycle.

•This can be internally masked by resetting the interrupt enable flag.

•This signal is active high and internally synchronized.

7. TEST* - This input is examined by a ‘WAIT’ instruction. If the TEST* input goes

low, execution will continue, else, the processor remains in an idle state.



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8. NMI – Non-maskable Interrupt: This is an edge-triggered input which causes a

Type2 interrupt.

• The NMI is not maskable internally by software.

•A transition from low to high initiates the interrupt response at the end of the

current instruction.

•This input is internally synchronized.

9. RESET – This input causes the processor to terminate the current activity and

start execution from FFFF0H.

•The signal is active high and must be active for at least four clock cycles.

•It restarts execution when the RESET returns low.

•RESET is also internally synchronized.

10. CLK – Clock Input: It provides the basic timing for processor operation and the

bus control activity. It’s an asymmetric square wave with 33% duty cycle.

The range of frequency for different versions is from 5MHz to 10MHz.



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11. Vcc : +5V power supply for the operation of the internal circuit.

12. GND: Ground for the internal circuit.

13.MN/MX* : The logic level at this pin decides whether the processor is to operate

in either minimum (single processor) or maximum (multiprocessor) mode.

• The following pin functions are for minimum mode operations of 8086:

1.M/IO* - Memory/IO : This is a status line logically equivalent to S2* in the

maximum mode.

• When it is low, it indicates the CPU is having an I/O operation, and when it is high,

it indicates that the CPU is having a memory operation.

•This. line becomes active in the previous T4 and remains active till final T4 of the

current cycle

•It is tristated during local bus ‘hold acknowledge’.

2. INTA* - Interrupt Acknowledge : This signal is used as a read strobe for interrupt

acknowledge cycles. It is active low during T2, T3 and Tw of each interrupt ack cycle.



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3. ALE – Address Latch Enable : This out signal indicates the availability of the

valid address on the address/data lines, and is connected to latch enable input of

latches.

• This signal is active high and is never tristated.

4. DT/R* - Data Transmit/Receive : This output is used to decide the direction of

data flow through the transreceivers (bidirectional buffers).

• When the processor sends out data, this signal is high and when the processor is

receiving data, this signal is low.

•Logically, this is equivalent to S1* in maximum mode.

•Its timing is the same as M/IO*.

•This is tristated during ‘hold acknowledge’.



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5. DEN* - Data Enable: This signal indicates the availability of valid data over the

address/data lines.

• It is used to enable the transreceivers (bidirectional bufferes) to separate the data

from the multiplexed address/data signal.

• It is active from the middle of T2 until the middle of T4.

•DEN* is tristated during ‘hold acknowledge’ cycle.

6. HOLD, HLDA – Hold/Hold Acknowledge: When the HOLD line goes high, it

indicates to the processor that another master is requesting the bus access.

• The processor, after receiving the HOLD request, issues the hold acknowledge

signal on HLDA pin, in the middle of the next clock cycle after completing the

current bus (instruction) cycle.

•At the same time, the processor floats the local bus and control lines.

•When the processor detects the HOLD line low, it lowers the HLDA signal.

•HOLD is an asynchronous input, and it should be externally synchronized.



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•The following pin functions are for maximum mode operations of 8086,

1.S2*, S1*, S0* - Status Lines : These are the status lines which indicate the type of

operation, being carried out by the processor.

• These become active during T4 of the previous cycle and remain active during T1

and T2 of the current bus cycle.

•The status lines return to passive state during T3 of the current bus cycle so that

they may again become active for the next bus cycle during T4.

•Any change in these lines during T3 indicates the starting of a new cycle, and return to

passive state indicates end of the bus cycle.



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2. LOCK* - This output pin indicates that the other system bus master will be

prevented from gaining the system bus, while the LOCK* signal is low.

• The LOCK* signal is activated by the ‘LOCK’ prefix instruction and remains active

until the completion of the next instruction.

•When the CPU is executing a critical instruction which requires the system bus, the

LOCK prefix instruction ensures that other processors connected in the system will not

gain the control of the bus.

3. QS1, QS0 – Queue Status : These lines give information about the status of the

code-prefetch queue.

•These are active during the CLK cycle after which the queue operation is performed.

•8086 architecture has a 6-byte instruction prefetch queue.

•Thus even the largest (6-bytes) instruction can be prefetched from the memory

and stored in the prefetch queue.

•This results in faster execution of the instructions.



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• By pre-fetching the instruction, there is a considerable speeding up in instruction

execution in 8086. This scheme is known as instruction pipelining.



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4. RQ*/GT0*, RQ*/GT1* - Request/Grant : These pins are used by other local bus

masters, in maximum mode, to force the processor to release the local bus at the

end of the processor’s current bus cycle.

• Each pins is bidirectional with RQ*/GT0* having higher priority than RQ*/GT1*.

•RQ*/GT* pins have internal pull up resistors and may be left unconnected.

•The request/grant sequence is as follows:

i) A pulse one clock wide from another bus master requests the bus access to 8086.

ii) During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from 8086 to the

requesting master, indicates that the 8086 has allowed the local bus to float and it will

enter the ‘hold acknowledge’ state in the next clock cycle. The CPU’s bus interface

unit is likely to be disconnected from the local bus of the system.

iii) A one clock wide pulse from the another master indicates to 8086 that the ‘hold’

request is about to end and the 8086 may regain control of the local bus at the next

clock cycle.



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• Thus, each master to master exchange of the local bus is a sequence of 3 pulses.

•There must be at least one dead clock cycle after each bus exchange.

•The request and grant pulses are active low.



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8086 Microprocessor Instruction Queue Operation:

• In the beginning, the CS:IP is loaded with the required address from which the

execution is to be started.

•Initially, the queue will be empty and the microprocessor starts a fetch operation

to bring one byte (the first byte) of instruction code, if the CS:IP address is odd or

two bytes at a time, if the CS:IP address is even.

•The first byte is a complete opcode incase of some instructions (one byte opcode

instruction) and it is a part opcode, in case of other instructions (two byte long

opcode instructions), the remaining part of opcode may lie in the second byte.

•But invariably the first byte of an instruction is an opcode.

•These opcodes along with data are fetched and arranged in queue.



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• When the first byte from the queue goes for decoding and interpretation, one

byte in the queue becomes empty and subsequently the queue is updated.

•The microprocessor does not perform the next fetch operation till at least two

bytes of the instruction queue are emptied.

•The instruction execution cycle is never broken for fetch operation.

•After decoding the first byte, the decoding circuit decides whether the instruction

is of single opcode byte or double opcode byte.

•If it is a single opcode byte, the next bytes are treated as data bytes depending

upon the decoded instruction length, otherwise, the next byte in the queue is

treated as the second byte of the instruction opcode.

•The second byte is then decoded in continuation with the first byte to decide the

instruction length and the number of subsequent bytes to be treated as

instruction data.



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•The queue is updated after every byte is read from the queue but the fetch cycle

is initiated by BIU only if at least two bytes of the queue are empty and the EU may

be concurrently executing the fetched instruction.

•The next byte after the instruction is completed is again the first opcode byte of the next

instruction.

•A similar procedure is repeated till the complete execution of the program.



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8086 Microprocessor : Addressing Modes

• The different ways in which a source operand is denoted in an instruction is

known as addressing modes.

•There are 8 different addressing modes in 8086 programming.

1.Immediate addressing mode: The addressing mode in which the data operand is a

part of the instruction itself is known as immediate addressing mode.

Eg: MOV CX, 4456 H

ADD AX, 2376 H,

MOV AL, F0H

2. Register addressing mode: It means that the register is the source of an operand

for an instruction.

Eg: MOV CX, AX

ADD AX, CX



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3. Direct addressing mode: The addressing mode in which the effective address of

the memory location is written directly in the instruction.

Eg: MOV AX, [1590H]

MOV AL, [0400H]

4. Register indirect addressing mode: This addressing mode allows data to be

addressed at any memory location through an offset address held in any of the

following registers: BP, BX, DI & SI.

Eg: MOV AX, [BX] ; Suppose the register BX contains 4845H, then the contents ;

4845H are moved to AX

ADD CX, [BX]

5. Based addressing mode: The offset address of the operand is given by the sum

of contents of the BX/BP registers and 8-bit/16-bit displacement.

Eg: MOV CX, [BX+04]

ADD AL, [BX+08]



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6. Indexed addressing mode: The operands offset address is obtained by adding

the contents of SI or DI register and 8-bit/16-bit displacements.

Eg: MOV BX, [SI+16]

ADD AL, [DI+16]

7. Based-index addressing mode: The offset address of the operand is computed

by summing the base register to the contents of an Index register.

Eg: ADD CX, [AX+SI]

MOV AX, [AX+DI]

8. Based Indexed with Displacement mode: The operands offset is computed by

adding the base register contents, An Index registers content and 8 or 16-bit

displacement.

Eg: MOV AX, [BX+DI+08]

ADD CX, [BX+SI+16]



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8086 Microprocessor : Interrupts

• Interrupt is the method of creating a temporary halt during program execution and

allows peripheral devices to access the microprocessor.

•The microprocessor responds to that interrupt with an execution of ISR (Interrupt

Service Routine), which is a short program to instruct the microprocessor on how to

handle the interrupt.

•After executing the ISR, the control is transferred back again to the main program

which was being executed at the time of interruption.

•Whenever a number of devices interrupt a CPU at a time, and if the processor is able to

handle them properly, it is said to have multiple interrupt processing capability.



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8086 Microprocessor : Interrupt Execution Procedure

•Suppose an external device interrupts the CPU at the interrupt pin, either NMI or

INTR of the 8086, while the CPU is executing an instruction of a program.

•The CPU first completes the execution of the current instruction.

•The IP is then incremented to point to the next instruction.

•The CPU then acknowledges the requesting device on its INTA* pin immediately if

it is a NMI, TRAP or Divide by Zero interrupt.

•If it is an INT request, the CPU checks the IF flag.

•If the IF is set, the interrupt request is acknowledged using the INTA* pin.

•If the IF is not set, the interrupt requests are ignored.

•After an interrupt is acknowledged, the CPU computes the vector address from

the type of the interrupt that may be passed to the interrupt structure of the CPU

internally or externally, i.e. from an interrupt controller in case of external interrupts.



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•The contents of IP and CS are next pushed to the stack.

•The contents of IP and CS now point to the address of the next instruction of the main

program from which the execution is to be continued after executing the ISR.

•The PSW is also pushed to the stack.

•The Interrupt Flag (IF) is cleared

•The TF is also cleared, after every response to the single step interrupt.

•The control is then transferred to the interrupt service routine for serving the

interrupting device.

•The new address of ISR is found out from the interrupt vector table.

•The execution of the ISR starts.

•If further interrupts are to be responded to during the time the first interrupt is being

serviced, the IF should again be set to 1 by the ISR of the first interrupt.

•If interrupt flag is not set, the subsequent interrupt signals will not be acknowledged by

the processor, till the current one is completed.



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•The programmable interrupt controller is used for managing such multiple

interrupts based on their priorities.

•At the end of ISR the last instruction should be IRET.

•When the CPU executes IRET, the contents of flags, IP and CS which were saved

at the start by the CALL instruction are now retrieved to the respective registers.

•The execution continues onwards from this address, received by IP and CS.



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8086 Microprocessor : Interrupt Execution Procedure – Nested Interrupts



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8086 Microprocessor : Interrupts

•The following image shows the types of interrupts in 8086 microprocessor,



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8086 Microprocessor : Interrupts - Hardware

• Hardware interrupt or external interrupt is caused by any peripheral device by

sending a signal through a specified pin to the microprocessor.

•The 8086 has two hardware interrupt pins, i.e. NMI and INTR.

•NMI is a non-maskable interrupt and INTR is a maskable interrupt (masked using

the Interrupt Flag (IF)) having lower priority.

• One more interrupt pin associated is INTA called interrupt acknowledge.

•8086 supports of 256 types of interrupts.

•The Interrupt types may be from 00 to FFH (00 to 255).

•If more than one type of INTR interrupt occurs at a time, then an external chip

called programmable interrupt controller is required to handle them.



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8086 Microprocessor : Interrupts - Hardware



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8086 Microprocessor : Interrupts – Hardware

•In the zeroth segment of physical address space, i.e. CS = 0000, Intel has reserved

1024 locations for storing the interrupt vector table.

• Each interrupt requires 4 bytes, i.e. two bytes each for IP and CS of its ISR.

•Thus a total of 1024 bytes are required for 256 interrupt types, hence the interrupt

vector table starts at location 0000:0000 and ends at 0000:03FFH.

•Interrupt vector table contains the IP and CS of all the interrupt types stored

sequentially form address 0000:0000 to 0000:03FFH.

•The interrupt type N is multiplied by 4 and the hexadecimal multiplication obtained

gives the offset address in the zeroth code segment at which the IP and CS addresses

of the ISR are stored.



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8086 Microprocessor : Interrupts – Hardware - NMI

• It is a single non-maskable interrupt pin (NMI) having higher priority than the

maskable interrupt request pin (INTR)and it is of Type 2 interrupt.

•When this interrupt is activated, these actions take place −

1. Completes the current instruction that is in progress.

2. Pushes the Flag register values on to the stack.

3. Pushes the CS (code segment) value and IP (instruction pointer) value of the return

address on to the stack.

4. IP is loaded from the contents of the word location 00008H.

5. CS is loaded from the contents of the next word location 0000AH.

6. Interrupt flag and trap flag are reset to 0.



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8086 Microprocessor : Interrupts – Hardware - INTR

• The INTR is a maskable interrupt (masked by resetting the Interrupt flag) because

the microprocessor will be interrupted only if interrupts are enabled using set

interrupt flag instruction.

•It is level triggered.

•The INTR interrupt is activated by an I/O port.

•If the interrupt is enabled and NMI is disabled, then the microprocessor first

completes the current execution and sends ‘0’ on INTA pin twice.

•The first ‘0’ means INTA informs the external device to get ready and during the

second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable

interrupt controller.

•The status of the pending interrupt is checked at the end of each instruction

cycle.



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8086 Microprocessor : Interrupts – Hardware - INTR



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8086 Microprocessor : Interrupts – Hardware – INTR

•These actions are taken by the microprocessor −

1. First completes the current instruction.

2. Activates INTA output and receives the interrupt type, say X.

3. Flag register value, CS value of the return address and IP value of the return address

are pushed on to the stack.

4. IP value is loaded from the contents of word location X * 4

5. CS is loaded from the contents of the next word location.

6. Interrupt flag and trap flag is reset to 0



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8086 Microprocessor : Interrupts – Software – INT

•The Internal Interrupt or Software interrupt is generated internally by the processor

circuit, or by the execution of an interrupt instruction.

•Some instructions are inserted at the desired position into the program to create

interrupts.

•These interrupt instructions can be used to test the working of various interrupt

handlers.

•Examples: divide by zero interrupt, overflow interrupt, interrupts due to INT instructions.

•It includes: INT- Interrupt instruction with type number

•It is 2-byte instruction. First byte provides the opcode and the second byte provides

the interrupt type number.

•There are 256 interrupt types under this group.



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•Its execution includes the following steps −

1. Flag register value is pushed on to the stack.

2. CS value of the return address and IP value of the return address are pushed on to

the stack.

3. IP is loaded from the contents of the word location ‘type number’ * 4


5. Interrupt Flag and Trap Flag are reset to 0.



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• The starting address for type0 interrupt is 00000H, for type1 interrupt is 00004H

similarly for type2 is 00008H and ……so on.

•The first five pointers are dedicated interrupt pointers.

1. TYPE 0 interrupt represents division by zero situation.

2. TYPE 1 interrupt represents single-step execution during the debugging of a

program.

3. TYPE 2 interrupt represents non-maskable NMI interrupt.

4. TYPE 3 interrupt represents break-point interrupt.

5. TYPE 4 interrupt represents overflow interrupt.

•The interrupts from Type 5 to Type 31 are reserved for other advanced

microprocessors, and interrupts from Type 32 to Type 255 are available for

hardware and software interrupts.



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8086 Microprocessor : Interrupts – INT3 :Breakpoint interrupt instruction

•It is a 1-byte instruction having opcode is CCH.

•These instructions are inserted into the program so that when the processor

reaches there, then it stops the normal execution of program and follows the break-

point procedure.


1. Flag register value is pushed on to the stack.


the stack.

3. IP is loaded from the contents of the word location 3*4 = 0000CH


5. Interrupt Flag and Trap Flag are reset to 0



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8086 Microprocessor : Interrupts – INTO :Interrupt on Overflow instruction

•It is a 1-byte instruction and their mnemonic INTO.

•The opcode for this instruction is CEH.

•As the name suggests, it is a conditional interrupt instruction, i.e. it is active only

when the overflow flag is set to 1 and branches to the interrupt handler whose

interrupt type number is 4.

•If the overflow flag is reset then, the execution continues to the next instruction.


1. Flag register values are pushed on to the stack.


the stack.

3. IP is loaded from the contents of word location 4*4 = 00010H


5. Interrupt flag and Trap flag are reset to 0



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