DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING QUESTION BANK

SUBJECT CODE/TITLE : EC2203 / DIGITAL ELECTRONICSSUBJECT NO. : S3STAFF NAME : N.NAGARAJ.

UNIT-IPART – A

1. State Demorgan’s Theorem. (EC2203/APRIL/MAY 2010)2. Draw an active- High tri-state buffer & write its truth table. (EC2203/APRIL/MAY

2010)3. An 8 bit transistor register stores decimal 240. What is the binary output of the

register? (EC1201/ APRIL/MAY 2010)4. Subtract using 2’s complement method: (74)10-(85)10. (EC1201/ APRIL/MAY 2010)5. List some of the advantages of CMOS logic. (EC1201/ APRIL/MAY 2010)6. Realize an OR gate using NAND gates. (EC1201/ APRIL/MAY 2010)7. Convert (0.513)10 to octal. (EC1201/NOV/DEC 2007)8. Express (A+B’C) as sum of min terms. (EC1201/NOV/DEC 2007)9. Draw the logic diagram for X=AB+B’C. (EC1201/NOV/DEC 2007)10. Implement F= (AB’+A’B) (C+D’) with only NOR gates. (EC1201/NOV/DEC 2007)11. Convert Binary number 11011110 into its decimal equivalent.

(EC1201/MAY/JUN E 2007)12. Mention any two applications of Demorgan’s Theorem. (EC1201/ MAY/JUN E 2007)13. What are the major categories of logic circuits? (EC1201/ MAY/JUN E 2007)14. Write the Boolean expression for the output of the system shown in figure below:

(EC1201/ MAY/JUN E 2007)15. Determine the decimal value of the fractional binary number 0.1011.

(EC1201-NOV/DEC 2006)16. Explain De-Morgan’s Theorem. (EC1201-NOV/DEC 2006)17. What is Propagation Delay of a gate? (EC1201-NOV/DEC 2006)18. A certain gate draws 2mA when its output is high & 3.6mA when its output is

low. What is the average power dissipation if Vcc is 5V & it is operated on a 50% duty cycle? (EC1201-NOV/DEC 2006)

19. How will you use a 4 input NAND gate as a 2 input NAND gate? (nov2k2)20. Obtain the complement of F=wx’y+xy’ using demorgans theorem. 21. How will you use a 4 input NAND gate as a 2 input NAND gate? (nov-2k2) 22. Complement x (y’+z’). (nov-2k4) 23. Write down fan-in and fan-out of a standard TTL IC.24. Draw a tri state inverter and its truth table. 25. What is logic gate? 26. Why NAND and NOR gates are known as Universal gates? 27. Develop the circuit using only NAND gates: Y=AB(C+D)28. Develop the circuit using only NAND gates: Y=A (B’+C)29. State Demorgans laws.30. Convert the given expression in canonical SOP form: Y=A+AB+ABC.31. Convert the given expression in canonical POS form: Y=A (A+B)(A+B+C).32. Simplify the following three variable expression using Boolean algebra:

Y=лM(3,5,7)33. What is the need for K Map?34. Plot Boolean expression:

Y=A’BC’D’+AB’CD’+A’BCD’+AB’CD+ABC’D on the K map35. Plot Boolean expression:

Y= (A+B+C+D’) (A+B’+C’+D) (A+B+C’+D’)(A’+B’+C+D’)(A’+B’+C’+D)36. What is the need for Quine-Mc cluskey or tabular method? 37. State Consensus theorem.38. Convert 725.28 to the base 8 to decimal, binary, hexadecimal.39. Convert 61.3 from base 10 to base 2.40. 225 to the base X =(341) to the base 8 what is the value of X.

PART-B1. Express the Boolean function as (EC2203/APRIL/MAY 2010)

i)POS form. ii)SOP form.D = (A’ +B) (B’ + C). (4)

2. Minimize the given terms. (EC2203/APRIL/MAY 2010)Π M (0, 1, 4, 11, 13, 15) + Πd (5, 7, 8) using Quine-McCluskey methods & verify the results using K-map methods. (12)

3. Implement the following function using NOR gates. (8) (EC2203/APRIL/MAY 2010)Output = 1 when the inputs are ∑m (0,1,2,3,4)Output = 0 when the inputs are ∑m (5,6,7).

4. Discuss the general characteristics of TTL & CMOS logic families.(8) (EC2203/APRIL/MAY 2010)

5. Derive the equation for a 4-bit Look Ahead Carry Adder circuit. (6) (EC2203/APRIL/MAY 2010)

6. Simplify using Tabulation method. (EC1201/ APRIL/MAY 2010)F(A,B,C,D,E) = ∑(0,2,4,6,9,11,13,15,17,21,25,27,29,31) (16)

7. Use K-map to obtain the POS form for (EC1201/ APRIL/MAY 2010)F=A’B’D’ + A’CD + A’BC +A’BC’D + ACD + AB’D’. (8)

8. Draw the circuit of 2-input CMOS NAND gate & explain its operation. (10) (EC1201/ APRIL/MAY 2010)

9. Explain the operation of tri-state Inverter. (6) (EC1201/ APRIL/MAY 2010)10. Explain the working of a TTL NAND gate. (12) (EC242/APRIL/MAY 2010)11. Write a note on HTL gate. (4) (EC242/APRIL/MAY 2010)12. Explain the working of a CMOS logic gate. (12) (EC242/APRIL/MAY 2010)13. Write a note on ECL gate. (4) (EC242/APRIL/MAY 2010)14. Convert the binary number 0.1100 to its equivalent decimal number. (4)

(EC1201/NOV/DEC 2007)15. Convert the number (326)8 to its equivalent decimal number. (4)

(EC1201/NOV/DEC 2007)16. Convert the following binary number to its hexadecimal equivalent 1111110000.

(4) (EC1201/NOV/DEC 2007)17. Convert (2497.50)10 to its octal equivalent. (4) (EC1201/NOV/DEC 2007)18. Simplify the following using K-map: (EC1201/NOV/DEC 2007)

X=A’B+A’B’C+ABC’+AB’C’ (4)19. Convert SOP to equivalent POS: (EC1201/NOV/DEC 2007)

A’B’C+A’B’C+A’BC+A’BC+AB’C+ABC. (4)20. Apply Demorgan’s theorem to the following expression: ((A+B+C) D)’. (4)

(EC1201/NOV/DEC 2007)

21. Using Boolean Laws & rules simplify the logic expression. Z= (A’+B) (A+B). (4) (EC1201/NOV/DEC 2007)

22. Implement the Boolean expression using gates: X=(AB+C’)D+E. (4) (EC1201/NOV/DEC 2007)

23. Draw the logic symbol of a XNOR GATE & give its truth table. (4) (EC1201/NOV/DEC 2007)

24. Sketch a NAND-NAND logic circuit for the Boolean expression, Y=AB’+AC+BD. (8) (EC1201/NOV/DEC 2007)

25. Convert the following hexadecimal numbers to decimal.(8) (EC1201-NOV/DEC 2006)

(i)(IC)16

(ii)(A85)16

(iii)(E5)16

(iv)(B2F8)16

26. List out any 4 basic rules that are used in Boolean Algebra expressions. (8) (EC1201-NOV/DEC 2006)

27. Explain the basic laws of Boolean Algebra with example.(8) (EC1201-NOV/DEC 2006)

28. Explain the precautionary measures to be considered while handling CMOS device. (5) (EC1201-NOV/DEC 2006)

29. List out and explain the data sheet parameters.(11) (EC1201-NOV/DEC 2006)

30. Implement the expression: (EC1201-NOV/DEC 2006)

(i)AB + BCD + EFGH.(ii)(A + B) ( C + D + E ) ( F + G + H + I ) with logic gates. (8)

31. Compare the performance characteristics of TTL & CMOS. (8) (EC1201-NOV/DEC 2006)

32. Convert the following decimal numbers to their hexadecimal equivalent : (8) (EC1201/ MAY/JUN E 2007)

i)(14)10 (ii)(80)10 (iii)(3000)10 (iv)(62.5)10

33. Explain the fundamental rules used in Boolean expression. (8) (EC1201/ MAY/JUN E 2007)

34. Elaborate the basic laws of Boolean Algebra with example. (6) (EC1201/ MAY/JUN E 2007)

35. Write the steps for simplifying a logic expression using a Karnaugh map. (10) (EC1201/ MAY/JUN E 2007)

36. Explain the precautionary measures to be considered while handling CMOS device.(8) (EC1201/ MAY/JUN E 2007)

37. Simplify and draw the logic diagram for the expression shown below. (EC1201/ MAY/JUN E 2007)

Y=C.B.A + C.B.A + C.B.A. (8)38. Analyse the performance characteristics of TTL & CMOS Logic. (8) (EC1201/

MAY/JUN E 2007)

39. Simplify using K map F=∑m(0,1,6,7,9,13-17,32,33,38,39,46-49,57,61)(nov-2k4 )40. State and prove idempotent laws of Boolean algebra. (nov-2k2) 41. Distinguish between Boolean addition and binary addition. (apr-2k3) 42. Using Tabulation method simplify the Boolean function

F(V,W,X,Y,Z)= å(0,1,8,11-12,15,20-22,24,29,31) which has the don’t care

Condition d (9, 18, 30). (May-2k8) 43. Simplify:

Y=A’B’CD+AB’C’D’+A’B’C’D’+ABC’D+A’B’C’D+AB’C’D+ABCD44. Simplify using K Map:

Y=Q’RS+RS’+P’Q’R’S’+P’Q’R.Y= (P’+Q+R’) (P+Q+R) (P+Q+R’).

45. Simplify F(A,B,C,D)=summation m(0,1,2,3,11,12,14,15)46. Design a logic circuit to provide an output when any two or three of four switches

are closed.47. Using Quine-Mccluskey method, simplify

F(A,B,C,D)=∑m(1,3,5,8,9,11,15)+d(2,13).48. Find the reduced SOP form using K map

F(W,X,Y,Z)= ∑m(0,7,8,9,10,12)+ ∑d(2,5,13).

UNIT-IIPART-A

1. Write an expression for borrow & difference in a full subtractor circuit. (EC2203/APRIL/MAY 2010)

2. Draw the circuits diagram for 4-bit odd parity generator. (EC2203/APRIL/MAY 2010)

3. What is decoder? (nov-2k6) 4. What do you mean by encoder? (nov-2k6) 5. What is multiplexer? (nov-2k6) 6. Draw the logic diagram of party generator and checker. (nov-2k2) 7. What is Demultiplexer?8. What is the difference between Decoder and Demultiplexer? 9. Write short note on Priority Encoder? (may-2k8) 10. State the functions of different pins of IC74181.11. Write down the truth table full subtractor. (dec-2k4) 12. How you build a full adder using two half adder and OR gate:13. Draw the block diagram of combinational circuit.14. Define half Adder and full adder.15. Define half Adder using only NAND gates.16. Define half Adder using only NOR gates.17. Define Half subtractor and full subtractor.18. What do you mean by carry propagation delay?19. What is meant by comparator?

PART-B1. Draw & explain the block diagram of a 4-bit serial adder to add the contents of

two registers. (10) (EC2203/APRIL/MAY 2010)2. Multiply (1011)2 by (1101)2 using addition & shifting operation. Also draw block

diagram of the 4-bit by 4-bit parallel multiplier. (8) (EC2203/APRIL/MAY 2010)3. Design & implement the conversion circuits for Binary code to gray code. (8)

(EC2203/APRIL/MAY 2010)

4. Design a BCD to Excess 3 code converter. (8) (EC1201/ APRIL/MAY 2010)5. Design a BCD to seven segment decoder circuit. Assume don’t cares. (8) (EC1201/

APRIL/MAY 2010)6. Design a 3-bit magnitude comparator. (8) (EC1201/ APRIL/MAY 2010)7. Design a BCD to Gray code converter. Uses don’t care. (16)

(EC242/APRIL/MAY 2010)8. Design and implement a binary to Gray code converter. (16)

(EC242/APRIL/MAY 2010)9. A system of logic is to be designed which has two outputs & three inputs. One

output will be TRUE if an odd number of inputs are TRUE. The other output will be TRUE if only one input alone is TRUE. Draw the truth table & write the corresponding Boolean equations. (8) (EC242/APRIL/MAY 2010)

10. Implement Full Adder using two half adders.(8) (EC1201/NOV/DEC 2007)

11. Draw & explain the BCD adder circuit. (8) (EC1201/NOV/DEC 2007)

12. Draw the diagram and explain 1 to 16 Demultiplexer circuit.(8) (EC1201/ MAY/JUN E 2007)

13. Design 16 bit adder using two 7483ICs.14. Design a 3 bit comparator using three one bit comparators and logic gates 15. Design a combinational circuit to convet gray code to BCD. (may-2k8) 16. Design a combinational circuit to convet BCD to Excess 3 code. (may-2k8) 17. Design a 3 bit Adder. (may-2k8) 18. Implement the following functions using multiplexer:

F(A,B,C)= ∑ m(2,4,5,8,9.10,12)F(A,B,C,D)= пM(1,5,8,11,12,15)F(A,B,C,D)= ∑ m(0,3,4,7,8,11)+d(2,10,12) 

19. Implement the following functions using 3:8 DecodersF (A, B, C) =∑ m (0, 1, 4, 5, 7)

20. Design full adder circuit using decoder and Demultiplexer. 21. Write short note on Parity generator and checker. 22. Design the logic circuit for odd parity checker . 23. Implement the following multiple output function using suitable De-Mux and

Logic gates:F1 (A, B, C) =∑ m(1,3,5,7) +d(0,2)  F2 (A, B, C) =∑ m(0,2,5,6) +d(1,7)

24. Implement the Boolean function using 4:1 MUX.F(W,X,Y,Z)= ∑(1,2,3,6,7,8,11,12,14). (May-2k8)

25. Implement the following functions using 3:8 decoder: F(A,B,C)= ∑m(0,1,4,5,7)

26. Design full adder circuit using decoder and demultiplexer. 27. Draw and explain the block diagram of n-bit parallel adder. 28. Explain the working of n- bit subtractor with neat diagram. 29. Design the 4 bit BCD adder using 4 bit binary adders. 30. Draw and explain the working of 4 bit BCD subtractor using 9’s complement

Method. 31. Implement Excess 3 adder circuit using binary adders.

32. Design 16 bit adder using two 7483ICs. 33. Design a 3 bit comparator using three one bit comparators and logic gates.

UNIT-IIIPART-A

1. Mention any two difference between the edge triggering & level triggering. (EC2203/APRIL/MAY 2010)

2. What is meant by programmable counter? Mention its application. (EC2203/APRIL/MAY 2010)

3. Give the characteristic equation & excitation of T Flip Flop. (EC1201/ APRIL/MAY 2010)

4. What is ring counter? (EC1201/ APRIL/MAY 2010)5. Sketch Decoder circuit to decode 3 bits into 8 outputs. (EC1201/ APRIL/MAY

2010)6. Give the characteristics expression of a JK Flip Flop. (EC1201/NOV/DEC 2007)7. What is a Flow table? (EC1201/NOV/DEC 2007)8. How does a JK flip-flop differ from the SR flip-flop in its basic operation?

(EC1201/ MAY/JUN E 2007)9. Classify the registers with respect to serial and parallel input output. (EC1201/

MAY/JUN E 2007)10. How does a JK flip-flop differ from an SR flip-flop in its basic operation?

(EC1201-NOV/DEC 2006)11. Define Synchronous Counter. (EC1201-NOV/DEC 2006)12. What is decoder?13. What do you mean by encoder?14. What is Demultiplexer?15. What is the difference between Decoder and Demultiplexer?16. Write short note on Priority Encoder?17. State the functions of different pins of IC7418118. List the basic types of Programmable logic devices?19. What is PLA? How it differs from ROM?20. What is mask Programmable and field Programmable logic array?21. Give the array logic symbol for eight inputs AND gate?22. Explain various types of ROM.23. Draw the block diagram of sequential circuit24. State the difference between combinational logic and sequential logic25. Define flip flop26. What do you mean by present state and next state27. What is rise time?28. What is fall time?29. Define clock skew:30. What is race round condition? How is it avoided?31. How synchronous counters differ from asynchronous counters?32. Write short notes on PRBS generator?33. State various applications of shift registers:34. What is Primary disadvantage of an asynchronous counter?

PART-B1. Construct a clocked JK Flip-flop which is triggered at the positive edge of the

clock pulse from a clocked SR flip-flop consisting of NOR gates. (4) (EC2203/APRIL/MAY 2010)

2. Design a synchronous up/down counter that will count up from zero to one to two to three, & will repeat whenever an external input x is logic 0, & will count down from three to two to one to zero, and will repeat whenever the external input x is logic 1. Implement your circuit with one TTL SN74LS76 device & one TTL SN74LS00 device. (12). (EC2203/APRIL/MAY 2010)

3. Write down the Characteristic Table for the JK flip-flop with NOR gates. (4) (EC2203/APRIL/MAY 2010)

4. What is meant by Universal Shift Register? Explain the principle of operation of 4-bit Universal Shift Register. (12) (EC2203/APRIL/MAY 2010)

5. Design and explain the working of mod-7 counter. (10) (EC242/APRIL/MAY 2010)6. Write a note on state minimization. (6) (EC242/APRIL/MAY 2010)7. Explain the working of master-slave JK Flip-flop. (6) (EC242/APRIL/MAY 2010)8. Design a 3-bit binary counter using T-Flip flop that has a repeated sequence of 6

states. 000-001-010-100-101-110. Give the state table, state diagram & logic diagram. (16) (EC1201/NOV/DEC 2007)

9. Design the sequential circuit whose state table is given as (16) (EC1201/NOV/DEC 2007)

Present state

Input Next State Output

A1 A2 X A1 A2 Y

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 1 0

0 1 1 0 0 1

1 0 0 1 0 0

1 0 1 0 1 0

1 1 0 1 1 0

1 1 1 0 0 1

10. Draw the clocked RS Flip-flop & explain with truth table. (8) (EC1201/ MAY/JUN E 2007)11. Draw the 4-bit Johnson counter & explain the operation. (8) (EC1201/ MAY/JUN E 2007)12. Draw the logic diagram of a 5-bit serial load shift right register using D Flip-flop

& Explain. (8) (EC1201/ MAY/JUN E 2007)

13. Draw the logic diagram of a 4-bit parallel load re-circulating shift register & explain. (8) (EC1201/ MAY/JUN E 2007)

14. Draw the logic diagram for a master slave JK flip-flop & explain. (8) (EC1201-NOV/DEC 2006)

15. Draw 4-bit Johnson counter & explain the operation.(8) (EC1201-NOV/DEC 2006)16. Draw a 4-bit serial in serial out shift register & explain. (8)

(EC1201-NOV/DEC 2006)17. Draw the 8-bit serial in parallel out shift register & explain its operation. (8)

(EC1201-NOV/DEC 2006)19. Implement the following functions using multiplexer:

a. F(A,B,C)= ∑ m(2,4,5,8,9.10,12)b. F(A,B,C,D)= пM(1,5,8,11,12,15)c. F(A,B,C,D)= ∑ m(0,3,4,7,8,11)+d(2,10,12)

20. Implement the following functions using 3:8 DecodersF (A, B, C) =∑ m (0, 1, 4, 5, 7).

21. Design full adder circuit using decoder and Demultiplexer.22. Design the combinational Circuit for Common – anode 7 segment display/Driver.23. Write short note on Parity generator and checker.24. Design the logic circuit for odd parity checker.25. Implement the following multiple output function using suitable De-Mux and

logic gates:F1 (A, B, C) =∑ m (1, 3, 5, 7) +d (0, 2)F2 (A, B, C) =∑ m (0, 2, 5, 6) +d (1, 7)

26. 8. Implement the following Boolean Expressions using Rom 1. F1 (A, B, C) =∑ m (0, 2, 4, 7)2. F2 (A, B, C) =∑ m(1,3,5,7)

27. Draw the logic diagram of IC 74180.28. Draw and explain the working of following flip flops:

(a)RS (b) Clocked RS (c) D (d) JK (e) clock JK29. Write short notes on: (i) edge triggered flip flop (ii) Master slave flip flop30. Convert SR flip flop to JK flip flop 31. Convert JK flip flop to T flip flop 32. Convert SR flip flop to T flip flop 33. Convert D flip flop to T flip flop 34. Draw and explain the operation of Parallel in Parallel out shift register 35. Draw and explain the working of 4 bit UP/Down synchronous counter 36. Explain the working of 4 bit Johnson counter with the help of neat diagram: 37. Explain the working of 8 bit ring counter: 38. Design a 4 bit Binary Up/Down ripple counter using T flip flop 39. Explain the working of Frequency counter with the help of neat diagram: 40. Explain with the help of neat diagram 4 bit asynchronous decade counter 41. Design the following ripple counter using JK flip flop divide by 1142. Design a divide by 13 ripple up down counter using JK flip flop 43. When a counter is said to affect from lock out? (nov-2k4) 44. What is binary counter? (nov-2k6) 45. Draw the internal circuit of NOR gate latch and derive the truth table (may-2k6) 46. Draw the logic diagram of T flip flop. (may-2k8) 47. What is modulo N counter? (may-2k8) 48. Explain the different types of shift registers with neat diagram. (may-2k8) 49. Design a sequence detector to detect the sequence 101011. (may-2k8)

UNIT-IV

PART-A

1. What is meant by memory expansion? Mention its limit. (EC2203/APRIL/MAY 2010)

2. What are the advantages of static RAM compared to dynamic RAM? (EC2203/APRIL/MAY 2010)

3. Discuss how PLA differs from PAL. (EC1201/ APRIL/MAY 2010)4. What is PAL? Show how a PAL is programmed for the following logic function.

X=ABC+ABC+AB+AC. (8) (EC242/APRIL/MAY 2010) 5. Draw the logic diagram of a memory cell. (EC1201/NOV/DEC 2007) 6. What is a combinational PLD? (EC1201/NOV/DEC 2007) 7. Define Static Memory. (EC1201/ MAY/JUN E 2007) (EC1201-NOV/DEC 2006) 8. Whether ROM is classified as a non volatile storage device? Why? (EC1201/

MAY/JUN E 2007) 9. Write the advantage of EPROM over a PROM. (EC1201/ MAY/JUN E 2007)

10. What is RAM? (EC1201-NOV/DEC 2006) 11. Mention the two types of erasable PROM. (EC1201-NOV/DEC 2006) 12. List the basic types of Programmable logic devices? 13. What is PLA? How it differs from ROM? 14. What is mask Programmable and field Programmable logic array? 15. Give the array logic symbol for eight input AND gate? 16. Explain various types of ROM:

PART B1. We can expand the word size of a RAM by combining 2 or more RAM chips. For

instance, we can use two 32 * 8 memory chips where the number 32 represents the number of words & 8 represents the number of bits per word, to obtain a 32*16 RAM. In this case the number of words remains the same but the length of each word will 2 bytes long. Draw a block diagram to show how we can use two 16*4 memory chips to obtain a 16*8 RAM. (8) (EC2203/APRIL/MAY 2010)

2. Explain the principle of operation of Bipolar SRAM cell. (8) (EC2203/APRIL/MAY 2010)

3. A Combinational circuit is defined as the functions F1 = AB’C’+AB’C+ABCF2 = A’BC+AB’C+ABC. Implement the digital circuit with a PLA having 3 inputs, 3 product terms & 2 outputs. (8) (EC2203/APRIL/MAY 2010)

4. Write a note on SRAM based FPGA. (8) (EC2203/APRIL/MAY 2010)5. Explain memory decoding. (5) (EC242/APRIL/MAY 2010)6. Draw a RAM cell & explain its working. (5) (EC242/APRIL/MAY 2010)7. Write short notes on : (i) RAM (ii) Types of ROM. (16) (EC1201/NOV/DEC 2007)8. Implement the following 2 Boolean function with a PLA. (16)

(EC1201/NOV/DEC 2007)F1(A,B,C)=Σ (0,1,2,4)F2(A,B,C)=Σ (0,5,6,7)

9. Illustrate the concept of 16*8 bit ROM arrange with diagram. (8) (EC1201-NOV/DEC 2006)

10. Describe the typical ROM internal organization with necessary diagram. (8)

(EC1201-NOV/DEC 2006)11. Elaborate the single fused PROM cell with clear sketch. (6)

(EC1201-NOV/DEC 2006)12. Draw and explain the working of PLA.13. Implement the following Boolean function using PLA:

F1 (A, B, C) =∑ m(0,1,3,5)F2 (A, B, C) =∑ m(0,3,5,7)

14. Implement the following Boolean function using PAL:F1 (A, B, C) =∑ m(0,2,6,8.9,14)F2(A, B, C) =∑ m(1,2,4,5,9,10,14)

15. Tabulate the PLA Programmable table for the four Boolean functions listed below:A(x,y,z)= ∑ m(0,1,2,4,6)B(x,y,z)= ∑m(0,2,6,7)C(x,y,z)= ∑ m(3,6)D(x,y,z)= ∑ m(1,3,5,7)

16. Give the comparison between PROM,PLA,PAL17. Design sequence detector to detect a sequence 1101 using suitable PLA. Give

state diagram and state table:18. Categorize RAM & ROM. Explain in Detail. (8) (EC1201/ MAY/JUN E 2007)19. Explain the following terms: (EC1201/ MAY/JUN E 2007)

i)Dynamic memory.ii)Volatile Storage.iii)Field Programmable.iv)Mask Programmable. (8)

20. Explain the basic structure of 256 * 4 static RAM with neat sketch. (16) (EC1201-NOV/DEC 2006) (10) (EC1201/ MAY/JUN E 2007)

21. Implement the following Boolean Expressions using Rom F1 (A, B, C) =∑ m(0,2,4,7) F2(A, B, C) =∑  m(1,3,5,7) 

22. A combinational circuit is defined by the functions F1= ∑ (1,3,5) F2= ∑(5,6,7) 23. Implement the circuit with PLA having 3 inputs, 3 product terms and two

Outputs. (may-2k8)24. What are the advantages of EPROM? 25. What is the maximum range of a memory that can be accessed by 10 address lines

(may-2k8)

UNIT VPART A

1. Draw the block diagram for MOORE Model. (EC2203/APRIL/MAY 2010)2. What are hazard free digital circuits? (EC2203/APRIL/MAY 2010)3. Define the term Race in asynchronous sequential circuits.

(EC1201/ APRIL/MAY 2010)4. Define Dynamic Hazard. (EC1201/ APRIL/MAY 2010)5. What is MOORE machine? (EC1201/NOV/DEC 2007)6. What is Race? (EC1201/NOV/DEC 2007) (EC1201-NOV/DEC 2006)7. Draw and explain block diagram of Moore circuit 8. Draw and explain the block diagram of Mealy circuit9. Compare Moore and Mealy circuits 10. What is Moore and Mealy machine? Compare them11. Explain state minimization procedure with the help of example

12. Define state equivalence and machine equivalence related to sequential machine13. What are races and cycles? 14. What is the significance of state assignment? 15. What are Hazards?

16. What are essential hazards? 17. What is VERILOG HDL? 18. Explain the feature of VERILOG HDL: 19. State the difference between Asynchronous and synchronous sequential circuits: 20. What is Lock out? How is it avoided? 21. What is a hazard in combinational circuit? ( may-2k8) 22. What are the assumptions that must made for fundamental mode circuit? 23. What are the assumptions that must made for pulse mode circuit? (nov-2k6) 24. What is the difference between PLA and PAL? (nov-2k6)

    PART-B 1. For the circuit shown in figure, write down the state table & draw the state

diagram & analyze the operation. (16) (EC2203/APRIL/MAY 2010)2. What are called as essential hazards? How does the hazard occur in sequential

circuits? How can the same be eliminated using SR latches? Give an example. (16) (EC2203/APRIL/MAY 2010)

3. What are Hazards? Explain in detail with a suitable example. (16) (EC1201/NOV/DEC 2007)

4. The circuit has 2 inputs T (toggle) & C (Clock) & one output Q. The output state is complemented if T=1 & clock C changes from 1 to 0 (negative edge triggered) otherwise, under any other input condition, the output Q remains unchanged. Derive the Primitive flow table & Implication table. (16) (EC1201/NOV/DEC 2007)

5. Draw the fundamental mode & pulse mode asynchronous circuit & explain in detail. (16) (EC1201/ MAY/JUN E 2007)

6. Explain the following terms : (EC1201-NOV/DEC 2006) (EC1201/ MAY/JUN E 2007)i)Critical Raceii)Non Critical Race.iii)Hazard.iv)Flow Table. (8)

7. Illustrate the mixed operating mode sequential circuit model. (EC1201-NOV/DEC 2006) (EC1201/ MAY/JUN E 2007) (8)

8. Draw the fundamental mode asynchronous circuit & explain in detail. (8) (EC1201-NOV/DEC 2006)

9. Illustrate Pulse Mode Asynchronous circuit. (8) (EC1201-NOV/DEC 2006)10. Design sequential circuit for the given state diagram using T flip flop: 11. Explain state minimization Procedure with the help of examples: 12. Explain static, dynamic and essential hazards in digital circuit. Give Hazard free

realization for the following Boolean function F (a,b,c,d) = ∑m(1,3,4,5,6,7,9,11,15) (may-2k8).

13. Explain the Procedure to give Hazard free realization of Boolean function: 14. An asynchronous sequential circuit is described by the following excitation and

output function? X= (Y1Z1’W2) X+ (Y1’’Z1W2’); S=X’ (may 2k8).15. Draw the logic diagram of the circuit.16. Derive the transition table and output map17. Describe the behavior of the circuit.  18. Design a 3 bit adder and 4:1 mux using verilog.

19. Design D flip flop and SISO register by verilog.20. Draw and explain block diagram of Moore circuit.21. Draw and explain the block diagram of Mealy circuit.22. Compare Moore and Mealy circuits.23. State the difference between Asynchronous & Synchronous circuits. What is

Moore and Mealy machine? Compare them.24. Explain state minimization procedure with the help of example.25. Define state equivalence and machine equivalence related to sequential machine:]26. What are races and cycles?27. What is the significance of state assignment?28. What are Hazards?29. What are essential hazards?30. What is VHDL?31. Explain the feature of VHDL.32. What is Lock out? How is it avoided?33. Design sequential circuit for the given state diagram using T flip flop:34. Explain state minimization Procedure with the help of examples:35. Explain static, dynamic and essential hazards in digital circuit. Give Hazard free

realization for the following Boolean function:F(a,b,c,d)= ∑m(2,3,5,7,10,14)

36. Explain the Procedure to give Hazard free realization of Boolean function:

DAILY ASSESSMENT PRACTICE QUESTIONS

YEAR/SEMESTER : II / IIIIV/ V II

SUB/SUB CODE : EC1201/Digital Electronics

SUBJECT NO. : S3

NAME OF THE STAFF : N.NAGARAJ.

Date Unit-I Questions

DAP-1

1. Convert the binary number 0.1100 to its equivalent decimal number. 2.Convert the number (326)8 to its equivalent decimal number. 3.Convert the following binary number to its hexadecimal equivalent 1111110000. 4.Convert (2497.50)10 to its octal equivalent.5.Simplify the following using K-mapX=A’B+A’B’C+ABC’+AB’C’6.Convert SOP to equivalent POSA’B’C+A’B’C+A’BC+A’BC+AB’C+ABC.

DAP-2 1. Simplify using K map F=∑m(0,1,6,7,9,13-17,32,33,38,39,46-49,57,61)

2. State and prove idempotent laws of Boolean algebra.

3. Distinguish between Boolean addition and binary addition. 4. Using Tabulation method simplify the Boolean function

F(V,W,X,Y,Z)= Σm(0,1,8,11-12,15,20-22,24,29,31) which has the don’t care condition d (9, 18, 30).

DAP-3

1. Draw & explain the block diagram of a 4-bit serial adder to add the contents of two registers.2. Multiply (1011)2 by (1101)2 using addition & shifting operation. Also draw block diagram of the 4-bit by 4-bit parallel multiplier.3. Design & implement the conversion circuits for Binary

code to gray code.

4. Design a BCD to Excess 3 code converter.

DAP-4

1. Draw the logic diagram for a master slave JK flip-flop & explain.

2. Draw 4-bit Johnson counter & explain the operation.3. Draw a 4-bit serial in serial out shift register & explain.

4. Draw the 8-bit serial in parallel out shift register & explain its operation.

DAP-5

1. Write short notes on : (i) RAM (ii) Types of ROM.2. Implement the following 2 Boolean function with a PLA.

F1(A,B,C)=Σ (0,1,2,4)F2(A,B,C)=Σ (0,5,6,7)

3. Illustrate the concept of 16*8 bit ROM arrange with diagram. 4. Describe the typical ROM internal organization with

necessary diagram.

DAP-6

1. For the circuit shown in figure, write down the state table & draw the state diagram & analyze the operation.

2. What are called as essential hazards? How does the hazard occur in sequential circuits? How can the same be eliminated using SR latches? Give an example.

3. What are Hazards? Explain in detail with a suitable example.

DAP-7

1. Design a 3 bit adder and 4:1 mux using verilog.2. Design D flip flop and SISO register by verilog.3. Draw and explain block diagram of Moore circuit.

4. Draw and explain the block diagram of Mealy circuit.

ASSIGNMENT QUESTIONS

YEAR/SEMESTER : II / IIIIV/ V II

SUB/SUB CODE : EC2203/Digital Electronics

SUBJECT NO. : S3

NAME OF THE STAFF : N.NAGARAJ.

Date Assignment no QuestionsASGN-1 PART-A

1.Plot Boolean expression: Y=A’BC’D’+AB’CD’+A’BCD’+AB’CD+ABC’D on the K map2.Plot Boolean expression: Y= (A+B+C+D’) (A+B’+C’+D) (A+B+C’+D’)(A’+B’+C+D’)(A’+B’+C’+D)3. What is the need for Quine-Mc cluskey or tabular method? 4. State Consensus theorem.5. Convert 725.28 to the base 8 to decimal, binary, hexadecimal.PART-B1. Discuss the general characteristics of TTL & CMOS logic families.2. Derive the equation for a 4-bit Look Ahead Carry Adder circuit.3. Simplify using Tabulation method. F(A,B,C,D,E) = ∑(0,2,4,6,9,11,13,15,17,21,25,27,29,31)4.Use K-map to obtain the POS form for F=A’B’D’ + A’CD + A’BC +A’BC’D + ACD + AB’D’.5. Draw the circuit of 2-input CMOS NAND gate & explain its operation.

6. Explain the operation of tri-state Inverter.

ASGN-2 PART-A1. Define half Adder using only NAND gates.2. Define half Adder using only NOR gates.3. Define Half subtractor and full subtractor.4. What do you mean by carry propagation delay?5. What is meant by comparator?PART-B1. Draw & explain the block diagram of a 4-bit serial adder to add the contents of two registers.2. Multiply (1011)2 by (1101)2 using addition & shifting operation. Also draw block diagram of the 4-bit by 4-bit parallel multiplier. 3. Design & implement the conversion circuits for Binary code to gray code.4. Design a BCD to Excess 3 code converter.5. Design a BCD to seven segment decoder circuit. Assume don’t cares.

6. Design a 3-bit magnitude comparator.

ASGN-3 PART-A1. Write short note on Priority Encoder?2.State the functions of different pins of IC741813. List the basic types of Programmable logic devices?4. What is PLA? How it differs from ROM?5. What is mask Programmable and field Programmable logic array?PART-B

1.Implement the following functions using multiplexer:a. F(A,B,C)= ∑ m(2,4,5,8,9.10,12)b. F(A,B,C,D)= пM(1,5,8,11,12,15)c. F(A,B,C,D)= ∑ m(0,3,4,7,8,11)+d(2,10,12)

2.Implement the following functions using 3:8 DecodersF (A, B, C) =∑ m (0, 1, 4, 5, 7).

3. Design full adder circuit using decoder and Demultiplexer.4. Design the combinational Circuit for Common – anode 7 segment display/Driver.5. Write short note on Parity generator and checker.6. Design a 3-bit binary counter using T-Flip flop that has a repeated sequence of 6 states. 000-001-010-100-101-110. Give the state table, state diagram & logic diagram.

ASGN-4 PART-A1. List the basic types of Programmable logic devices? 2. What is PLA? How it differs from ROM? 3. What is mask Programmable and field Programmable logic array? 4. Give the array logic symbol for eight inputs AND gate? 5. Explain various types of ROM: PART-B1. Draw and explain the working of PLA.2. Implement the following Boolean function using PLA:

F1 (A, B, C) =∑ m(0,1,3,5)F2 (A, B, C) =∑ m(0,3,5,7)

3.Implement the following Boolean function using PAL:F1 (A, B, C) =∑ m(0,2,6,8.9,14)F2(A, B, C) =∑ m(1,2,4,5,9,10,14)

4.Tabulate the PLA Programmable table for the four Boolean functions listed below:

A(x,y,z)= ∑ m(0,1,2,4,6)B(x,y,z)= ∑m(0,2,6,7)C(x,y,z)= ∑ m(3,6)D(x,y,z)= ∑ m(1,3,5,7)

5.Give the comparison between PROM,PLA,PAL

6. Design sequence detector to detect a sequence 1101 using suitable PLA. Give state diagram and state table.

ASGN-5 PART-A1. Draw the block diagram for MOORE Model. 2. What are hazard free digital circuits? 3. Define the term Race in asynchronous sequential circuits. 4. Define Dynamic Hazard. 5. What is MOORE machine?

PART-B1. What are called as essential hazards? How does the hazard occur

in sequential circuits? How can the same be eliminated using SR latches? Give an example.

2. Illustrate the mixed operating mode sequential circuit model.3. An asynchronous sequential circuit is described by the following

excitation and output function? X= (Y1Z1’W2) X+ (Y1’’Z1W2’); S=X’

4. Explain static, dynamic and essential hazards in digital circuit. Give Hazard free realization for the following Boolean function:F(a,b,c,d)= ∑m(2,3,5,7,10,14)

5. State the difference between Asynchronous & Synchronous circuits. What is Moore and Mealy machine? Compare them.

6. Explain state minimization procedure with the help of example.