SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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SIR PADAMPAT SINGHANIA UNIVERSITY

Udaipur

School of Engineering

LABORATORY MANUAL

VLSI DESIGN LAB

EC-402

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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LIST OF EXPERIMENTS

S. N. Title of the Experiment

(a).Write the program for basic logic gates using:

Data flow style (b).Behavioral style(c).Structural style. 1.

(b).Write VHDL code for Half adder and Full adder, using data flow.

(a).Write VHDL code for four bit adder. 2.

(b).Write a VHDL code for 4X1 MUX and for 16X1 MUX.

(a).Write VHDL code for 4X1 using concurrent & sequential statements 3.

(b).Write VHDL code using case statement for 2X4 decoder.

(a).Write a program in VHDL to implement a comparator circuit.

4. (b).Write a program for D latch also for D flip flop using synchronous reset &

asynchronous reset.

(a).Write a program in VHDL for implementing a n bit counter. 5.

(b).Write a program in VHDL and synthesize it using Xilinx for Logic gates.

6. a).Write the program for basic logic gates usingVerilog

b).Write Verilog code for Half adder and Full adder.

7. Design a Schematic of CMOS Inverter circuit.

8. Design a Schematic Of CMOS NAND gate.

9. Design a Schematic of CMOS NOR gate

10.. Draw a layout for CMOS Inverter circuit.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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OVERVIEW OF LAB

BASIC SIMULATION FLOW

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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MODEL SIM SIMULATION

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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MODEL SIM TUTORIAL

Step 1: Load ModelSim

Using ModelSim to simulate VHDL files is a three step process:

1. Edit the VHDL source code so that your design describes the item of hardware you are trying to model.

2. Compile the VHDL source code into an internal format that is ready for ModelSim to simulate. The internal format is the low-level description of your design: it is important to note that VHDL isn't simulating your VHDL source code, it is simulated the compiled internal format. Hence, each time you change the source code you need to re-compile before re-simulating.

3. Simulate the internal format by instantiating all the design modules and using a top level stimulus file to drive test signals onto the inputs of your design and inspecting the outputs.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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The first step is to actually load the ModelSim software, to do this you need to follow the steps on the online form which detail the sign-up and set-up process. Once you start ModelSim, the main window will appear. There are three main parts to the main window which is tiled either vertically or horizontally depending on your preference. The top or left pane is the project workspace which details the files and modules that are currently being edited or hand been compiled. The bottom or right pane is the command shell which is used to issue textual commands to ModelSim and where ModelSim prints out any errors, warnings or output from your code. At the top of the window is the third pane, a tool-bar which holds the command buttons that act as short cuts for actions such as compilation.

Step 2: Start or Load a Project

ModelSim is project based in the sense that it likes you to work on VHDL files grouped into a collection called a project. The next step is to either open an existing project or make a new one. Use the File\Open\Project menu item to open an existing project or File\New\Project to make a new one.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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The first step in making a new project is to name both the project and the library associated with it. The library for a project is simply where all the compiled modules are stored in the internal format by ModelSim so that it can simulate them. There are no rules about these names but it helps to call them something associated with what you are doing.

Once the new, empty project is created you need to add new or existing VHDL files to it so you can work on them. Use the File\Add To Project\New File menu item to add a new file or File\Add To Project\Existing File to add a file you have already. The type of the file you are adding should be a VHDL file: ModelSim can deal with other HDL like VHDL, if you add a VHDL file and then put VHDL source code in it, ModelSim will get confused ! The default file type tries to guess the type based on the extension of the file name.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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After adding the source file, the project workspace includes this new item. The name and type of the file are self-evident; the status of the file refers to the compilation status. A question mark indicates that ModelSim currently has no compiled version of the file; a cross indicates that ModelSim tried to compile it but failed due to some errors; a tick indicates the file was compiled and is ready for simulation. Note that errors at this stage are syntactic errors; problems with the syntax of your source code, maybe a missing semicolon or something like this.

Step 3: Edit and Compile the Design

In order to edit the file and make the source code describe what you want it to, right click on the file name in the project workspace and select Edit to open the editor window. This will allow you to edit the VHDL code.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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Once you are happy with the source code, you need to compile it into the ModelSim internal format ready for simulation. You can either compile lots of files at once or one at a time: either use the buttons from the tool-bar or the Compile menu item. Having started the compilation process, ModelSim will report and errors in the command window. In this case there were no errors and the file status indicates the file is ready for simulation. In the event that there were compilation errors, right click on the file name in the project workspace and select Compile\Compile Report to open a window which details where and why the errors occurred. Correct the errors by re-editing the source code and compile the file again.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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Once the file is ready for simulation, you can move to the Library tab of the project workspace. You should find an entry for the library which you named earlier. After refreshing this entry by right clicking on it and selecting the Refresh menu item, it should contain all the modules from your design: in this case the alu_cmp and alu_exe modules and the top level stimulus called alu_test.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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Step 4: Instantiate and Simulate the Design Having edited and compiled the VHDL source code, you are now ready to actually simulate the internal representation of your design that ModelSim has constructed. The next step is to ask ModelSim to take this internal representation and instantiate it ready for simulation. This is done by double clicking on the module name in the library. ModelSim proceeds to build the design and instantiate any modules that your selected module contains. At this point you might find ModelSim issues more errors in the command window: these are semantic errors; problems with the meaning of your source code. Common errors at this point include connecting ports of modules together which are the wrong size or the wrong type, misnaming ports or connecting them in the wrong order. Recap on the lecture notes about the rules by which wire and reg connections can be use as input and output if in doubt.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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In this case there were no errors and ModelSim correctly instantiated the alu_cmp, alu_exe and alu_test modules. Finally, we are ready to simulate the design; in order to inspect the signals being sent to and from our modules, we use the wave window. First open the signals window using the View\Signals menu item. This gives a list of all the inspectable signals within a given module. Select all the signals and use the Add\Wave\Selected Signals menu item to add them to the wave window.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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When the wave window appears, it is empty because we have not yet started to run the design. The wave window charts the value of signals within the design against time. This allows you inspect the value of various signals in relation to one another, and check if their behaviour matches what you expect. The left hand pane holds the signal name and next to that the signal value at the current time: the yellow line on the actual waveform sets the current time.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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First, restart the simulation so we are sure that any residual state is cleared and we are starting afresh.

Now use the run button to start the simulation; ModelSim will simulate the circuit for a given time period and then break ready for more commands: if you want to continue simulation after this, you need to issue more run commands. At first, the waveform may be too squashed up to see. Use the zoom tools and scrollbars to inspect the part of the waveform that is of interest. Here we can see that the output signals from the alu_exe module match what we expect. For example, when the operator is set for addition and we feed in the values three and seven, the output is ten. Note that you can change the radix of the values in the wave window by right clicking on them and using the Radix menu item: this make interpreting binary values easier ! Also note that as well as the value bubbles, red lines indicate undefined values while blue lines indicate high impedance values: seeing where and when these values occur can be vital in determining why a design doesn't work.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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Finally, note that since we included a $monitor system task in our source code, ModelSim has also printed out various values for us in the command window. This mirrors the output in the wave window and simply offers a faster way to inspect the values in a textual rather than graphical manner.

SIR PADAMPAT SINGHANIA UNIVERSITY, Udaipur Lab Manual Department of E & C Engineering

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