e200z7 Power Architecture Core Reference Manual · 2016-11-23 · e200z7 Power Architecture Core...

e200z760n3 Power Architecture®Core Reference Manual

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e200z760RMRev. 2

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e200z7 Power Architecture Core Reference Manual, Rev. 2

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ContentsParagraphNumber Title

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Contents

About This Book

Audience ...................................................................................................................... xxxixOrganization....................................................................................................................... xlSuggested Reading............................................................................................................ xli

General Information...................................................................................................... xliAcronyms and Abbreviations .......................................................................................... xliiTerminology Conventions............................................................................................... xliii

Chapter 1 e200z7 Core Complex Overview

1.1 e200z7 Overview ............................................................................................................. 1-11.1.1 Features........................................................................................................................ 1-21.2 Programming Model ........................................................................................................ 1-31.2.1 Register Set .................................................................................................................. 1-31.2.2 Instruction Set .............................................................................................................. 1-61.2.2.1 VLE Category.......................................................................................................... 1-91.2.3 Interrupts and Exception Handling .............................................................................. 1-91.2.3.1 Interrupt Handling ................................................................................................... 1-91.2.3.2 Interrupt Classes .................................................................................................... 1-101.2.3.3 Interrupt Types....................................................................................................... 1-101.2.3.4 Interrupt Registers ................................................................................................. 1-111.3 Microarchitecture Summary .......................................................................................... 1-131.3.1 Instruction Unit Features ........................................................................................... 1-141.3.2 Integer Unit Features ................................................................................................. 1-141.3.3 Load/Store Unit (LSU) Features................................................................................ 1-151.3.4 L1 Cache Features ..................................................................................................... 1-151.3.5 Memory Management Unit (MMU) Features ........................................................... 1-161.3.6 System Bus (Core Complex Interface) Features........................................................ 1-161.3.7 Nexus 3+ Module Features ........................................................................................ 1-16

Chapter 2 Register Model

2.1 Power ISA Embedded Category Registers ...................................................................... 2-42.2 e200-Specific Special Purpose Registers......................................................................... 2-72.3 e200-Specific Device Control Registers.......................................................................... 2-82.4 Special-Purpose Register Descriptions ............................................................................ 2-92.4.1 Machine State Register (MSR) .................................................................................... 2-92.4.2 Processor ID Register (PIR) ...................................................................................... 2-11


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2.4.3 Processor Version Register (PVR)............................................................................. 2-112.4.4 System Version Register (SVR)................................................................................. 2-122.4.5 Integer Exception Register (XER)............................................................................. 2-132.4.6 Exception Syndrome Register ................................................................................... 2-132.4.6.1 Power ISA VLE Mode Instruction Syndrome....................................................... 2-152.4.6.2 Misaligned Instruction Fetch Syndrome................................................................ 2-152.4.7 Machine Check Syndrome Register (MCSR)............................................................ 2-162.4.8 Timer Control Register (TCR)................................................................................... 2-182.4.9 Timer Status Register (TSR)...................................................................................... 2-202.4.10 Debug Registers......................................................................................................... 2-202.4.11 Hardware Implementation Dependent Register 0 (HID0)......................................... 2-212.4.12 Hardware Implementation Dependent Register 1 (HID1)......................................... 2-232.4.13 Branch Unit Control and Status Register (BUCSR).................................................. 2-242.4.14 L1 Cache Control and Status Registers (L1CSR0, L1CSR1).................................... 2-252.4.15 L1 Cache Configuration Registers (L1CFG0, L1CFG1)........................................... 2-252.4.16 L1 Cache Flush and Invalidate Registers (L1FINV0, L1FINV1) ............................. 2-252.4.17 MMU Control and Status Register (MMUCSR0) ..................................................... 2-252.4.18 MMU Configuration Register (MMUCFG) .............................................................. 2-252.4.19 TLB Configuration Registers (TLB0CFG, TLB1CFG)............................................. 2-262.5 SPR Register Access...................................................................................................... 2-262.5.1 Invalid SPR References ............................................................................................. 2-262.5.2 Synchronization Requirements for SPRs................................................................... 2-262.5.3 Special Purpose Register Summary........................................................................... 2-272.6 Reset Settings................................................................................................................. 2-31

Chapter 3 Instruction Model

3.1 Unsupported Instructions and Instruction Forms............................................................. 3-13.2 Implementation Specific Instructions .............................................................................. 3-13.3 Power ISA Embedded Category Instruction Extensions ................................................. 3-23.4 Memory Access Alignment Support................................................................................ 3-23.5 Memory Synchronization and Reservation Instructions.................................................. 3-23.6 Branch Prediction ............................................................................................................ 3-43.7 Interruption of Instructions by Interrupt Requests........................................................... 3-43.8 New e200 Functionality................................................................................................... 3-43.9 ISEL instruction............................................................................................................... 3-53.10 Enhanced Debug .............................................................................................................. 3-53.10.1 Debug Notify Halt Instructions.................................................................................... 3-73.11 Machine Check .............................................................................................................. 3-103.12 WAIT Instruction ........................................................................................................... 3-12


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3.13 Enhanced Reservations .................................................................................................. 3-133.14 Volatile Context Save/Restore Unit ............................................................................... 3-163.15 Unimplemented SPRs and Read-Only SPRs ................................................................. 3-243.16 Invalid Forms of Instructions......................................................................................... 3-243.16.1 Load and Store with Update instructions................................................................... 3-243.16.2 Load Multiple Word (lmw, e_lmw) instruction......................................................... 3-243.16.3 Branch Conditional to Count Register Instructions................................................... 3-253.16.4 Instructions With Reserved Fields Non-Zero ............................................................ 3-253.17 Instruction Summary...................................................................................................... 3-25

Chapter 4 Instruction Pipeline and Execution Timing

4.1 Overview of Operation .................................................................................................... 4-24.1.1 Control Unit ................................................................................................................. 4-34.1.2 Instruction Unit ............................................................................................................ 4-34.1.3 Branch Unit.................................................................................................................. 4-34.1.4 Instruction Decode Unit............................................................................................... 4-44.1.5 Exception Handling ..................................................................................................... 4-44.2 Execution Units................................................................................................................ 4-44.2.1 Integer Execution Units ............................................................................................... 4-44.2.2 Load/Store Unit............................................................................................................ 4-44.2.3 Embedded Floating-point Execution Units.................................................................. 4-44.3 Instruction Pipeline .......................................................................................................... 4-54.3.1 Description of Pipeline Stages ..................................................................................... 4-64.3.2 Instruction Prefetch Buffers and Branch Target Buffer ............................................... 4-74.3.3 Single-Cycle Instruction Pipeline Operation ............................................................. 4-104.3.4 Basic Load and Store Instruction Pipeline Operation................................................ 4-114.3.5 Change-of-Flow Instruction Pipeline Operation........................................................ 4-114.3.6 Basic Multicycle Instruction Pipeline Operation....................................................... 4-134.3.7 Additional Examples of Instruction Pipeline Operation for Load and Store............. 4-144.3.8 Move to/from SPR Instruction Pipeline Operation.................................................... 4-164.4 Control Hazards ............................................................................................................. 4-184.5 Instruction Serialization................................................................................................. 4-184.5.1 Completion Serialization ........................................................................................... 4-184.5.2 Dispatch Serialization ................................................................................................ 4-194.5.3 Refetch Serialization.................................................................................................. 4-194.6 Concurrent Instruction Execution.................................................................................. 4-194.7 Instruction Timings ........................................................................................................ 4-204.8 Operand Placement on Performance.............................................................................. 4-25


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Chapter 5 Embedded Floating-Point Unit

5.1 Nomenclature and Conventions....................................................................................... 5-15.2 EFPU Programming Model ............................................................................................. 5-15.2.1 Signal Processing Extension/Embedded Floating-Point Status and Control Register

(SPEFSCR) .............................................................................................................. 5-25.2.2 GPRs and Power ISA Embedded Category Instructions ............................................. 5-55.2.3 SPE/EFPU Available Bit in MSR................................................................................ 5-55.2.4 Embedded Floating-point Exception Bit in ESR......................................................... 5-55.2.5 EFPU Exceptions......................................................................................................... 5-55.2.5.1 EFPU Unavailable Exception .................................................................................. 5-65.2.5.2 Embedded Floating-point Data Exception............................................................... 5-65.2.5.3 Embedded Floating-point Round Exception ........................................................... 5-65.2.6 Exception Priorities...................................................................................................... 5-75.3 Embedded Floating-Point Unit Operations...................................................................... 5-75.3.1 Floating-point Data Formats........................................................................................ 5-85.3.1.1 Single-Precision Floating-point Format .................................................................. 5-85.3.1.2 Half-Precision Floating-point Format...................................................................... 5-95.3.2 IEEE 754 Compliance ............................................................................................... 5-105.3.3 Floating-Point Exceptions.......................................................................................... 5-115.3.4 Embedded Scalar Single-Precision Floating-Point Instructions................................ 5-115.3.5 EFPU Vector Single-precision Embedded Floating-Point Instructions..................... 5-445.4 Embedded Floating-point Results Summary ................................................................. 5-925.5 EFPU Instruction Timing............................................................................................. 5-1075.5.1 EFPU Single-Precision Vector Floating-Point Instruction Timing.......................... 5-1085.5.2 EFPU Single-precision Scalar Floating-Point Instruction Timing .......................... 5-1095.6 Instruction Forms and Opcodes ....................................................................................5-111

Chapter 6 Signal Processing Extension (SPE)

6.1 Nomenclature and Conventions....................................................................................... 6-16.2 SPE Programming Model ................................................................................................ 6-26.2.1 GPR Registers.............................................................................................................. 6-26.2.2 Accumulator Register .................................................................................................. 6-36.2.3 SPE Status and Control Register (SPEFSCR) ............................................................. 6-46.2.3.1 Context Switch......................................................................................................... 6-66.2.4 GPRs and Power ISA Instructions............................................................................... 6-66.2.5 SPE Available Bit in MSR........................................................................................... 6-66.2.6 SPE Exception Bit in ESR........................................................................................... 6-6


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6.2.7 Data Formats................................................................................................................ 6-76.2.7.1 Integer Format ......................................................................................................... 6-76.2.7.2 Fractional Format..................................................................................................... 6-76.2.8 Computational Operations ........................................................................................... 6-76.2.8.1 Simple Vector Arithmetic Instructions .................................................................... 6-86.2.8.2 Vector Logical Instructions.................................................................................... 6-156.2.8.3 Vector Shift/Rotate Instructions............................................................................. 6-156.2.8.4 Vector Compare and Vector Set Instructions ......................................................... 6-166.2.8.5 Vector Select Instructions ...................................................................................... 6-166.2.8.6 Vector Data Arrangement Instructions .................................................................. 6-176.2.8.7 Multiply and accumulate instructions.................................................................... 6-216.2.8.8 Dot product instructions ........................................................................................ 6-236.2.8.9 Miscellaneous Vector Instructions......................................................................... 6-246.2.9 Load and Store Instructions ....................................................................................... 6-256.2.9.1 Addressing Modes—Non-Update forms ............................................................... 6-256.2.9.1.1 Base + Scaled Immediate Addressing—Non-Update Form.............................. 6-256.2.9.1.2 Base + Index Addressing................................................................................... 6-256.2.9.2 Addressing Modes—Update forms ....................................................................... 6-266.2.9.3 Addressing Modes—Modify forms....................................................................... 6-266.2.9.3.1 Linear Addressing Update Mode....................................................................... 6-266.2.9.3.2 Circular Addressing Modify Mode.................................................................... 6-276.2.9.3.3 Bit-Reversed Addressing Modify Mode............................................................ 6-276.2.9.4 Vector Load and Store Instruction Summary......................................................... 6-286.2.10 SPE Exceptions.......................................................................................................... 6-306.2.10.1 SPE/Embedded Floating-point Unavailable Exception......................................... 6-306.2.10.2 SPE Vector Alignment Exception.......................................................................... 6-306.2.11 Exception Priorities.................................................................................................... 6-316.3 SPE Instruction Timing.................................................................................................. 6-316.3.1 SPE Simple Vector Arithmetic Instructions Timing.................................................. 6-316.3.2 SPE Complex Integer Instruction Timing.................................................................. 6-346.3.3 SPE Vector Logical Instruction Timing..................................................................... 6-346.3.4 SPE Vector Shift/Rotate Instruction Timing.............................................................. 6-356.3.5 SPE Vector Compare and Vector Set Instruction Timing .......................................... 6-356.3.6 SPE Vector Select Instruction Timing ....................................................................... 6-366.3.7 SPE Vector Data Arrangement Instruction Timing ................................................... 6-366.3.8 SPE Multiply and Multiply/Accumulate Instruction Timing .................................... 6-396.3.9 SPE Dot Product Instruction Timing ......................................................................... 6-396.3.10 SPE Misc. Vector Instruction Timing ........................................................................ 6-396.3.11 SPE Load and Store Instruction Timing .................................................................... 6-39


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Chapter 7 Interrupts and Exceptions

7.1 e200 Interrupts ................................................................................................................. 7-27.2 Exception Syndrome Register ......................................................................................... 7-47.3 Machine State Register .................................................................................................... 7-67.3.1 Machine Check Syndrome Register (MCSR).............................................................. 7-87.4 Interrupt Vector Prefix Registers (IVPR)....................................................................... 7-127.5 Interrupt Vector Offset Registers (IVORxx) .................................................................. 7-127.6 Interrupt Definitions ...................................................................................................... 7-137.6.1 Critical Input Interrupt (IVOR0)................................................................................ 7-147.6.2 Machine Check Interrupt (IVOR1)............................................................................ 7-147.6.2.1 Machine Check Causes.......................................................................................... 7-157.6.2.1.1 Error Report Machine Check Exceptions .......................................................... 7-157.6.2.1.2 Nonmaskable Interrupt Machine Check Exceptions ......................................... 7-207.6.2.1.3 Asynchronous Machine Check Exceptions ....................................................... 7-207.6.2.2 Machine Check Interrupt Actions.......................................................................... 7-277.6.2.3 Checkstop State ..................................................................................................... 7-287.6.3 Data Storage Interrupt (IVOR2) ................................................................................ 7-287.6.4 Instruction Storage Interrupt (IVOR3) ...................................................................... 7-297.6.5 External Input Interrupt (IVOR4) .............................................................................. 7-307.6.6 Alignment Interrupt (IVOR5).................................................................................... 7-317.6.7 Program Interrupt (IVOR6) ....................................................................................... 7-317.6.8 Floating-Point Unavailable Interrupt (IVOR7).......................................................... 7-327.6.9 System Call Interrupt (IVOR8).................................................................................. 7-337.6.10 Auxiliary Processor Unavailable Interrupt (IVOR9)................................................. 7-347.6.11 Decrementer Interrupt (IVOR10) .............................................................................. 7-347.6.12 Fixed-Interval Timer Interrupt (IVOR11).................................................................. 7-347.6.13 Watchdog Timer Interrupt (IVOR12) ........................................................................ 7-357.6.14 Data TLB Error Interrupt (IVOR13) ......................................................................... 7-367.6.15 Instruction TLB Error Interrupt (IVOR14)................................................................ 7-367.6.16 Debug Interrupt (IVOR15) ........................................................................................ 7-377.6.17 System Reset Interrupt............................................................................................... 7-407.6.18 SPE/EFPU Unavailable Interrupt (IVOR32)............................................................. 7-417.6.19 Embedded Floating-Point Data Interrupt (IVOR33) ................................................. 7-417.6.20 Embedded Floating-Point Round Interrupt (IVOR34) .............................................. 7-427.6.21 Performance Monitor Interrupt (IVOR35) ................................................................ 7-437.7 Exception Recognition and Priorities ............................................................................ 7-437.7.1 Exception Priorities.................................................................................................... 7-457.8 Interrupt Processing ....................................................................................................... 7-487.8.1 Enabling and Disabling Exceptions........................................................................... 7-49


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7.8.2 Returning from an Interrupt Handler ......................................................................... 7-507.9 Process Switching .......................................................................................................... 7-50

Chapter 8 Performance Monitor

8.1 Overview.......................................................................................................................... 8-18.2 Performance Monitor Instructions ................................................................................... 8-28.3 Performance Monitor Registers ....................................................................................... 8-38.3.1 Invalid PMR References.............................................................................................. 8-48.3.2 References to Read-only PMRs................................................................................... 8-48.3.3 Global Control Register 0 (PMGC0) ........................................................................... 8-58.3.4 User Global Control Register 0 (UPMGC0)................................................................ 8-68.3.5 Local Control A Registers (PMLCa0–PMLCa3) ........................................................ 8-68.3.6 User Local Control A Registers (UPMLCa0–UPMLCa3) .......................................... 8-78.3.7 Local Control B Registers (PMLCb0–PMLCb3) ........................................................ 8-78.3.8 User Local Control B Registers (UPMLCb0–UPMLCb3)........................................ 8-128.3.9 Performance Monitor Counter Registers (PMC0–PMC3)......................................... 8-128.3.10 User Performance Monitor Counter Registers (UPMC0–UPMC3) .......................... 8-138.4 Performance Monitor Interrupt ...................................................................................... 8-138.5 Event Counting .............................................................................................................. 8-148.5.1 MSR-based Context Filtering .................................................................................... 8-148.6 Examples........................................................................................................................ 8-158.6.1 Chaining Counters ..................................................................................................... 8-158.6.2 Thresholding .............................................................................................................. 8-158.7 Event Selection .............................................................................................................. 8-15

Chapter 9 L1 Cache

9.1 Overview.......................................................................................................................... 9-19.2 16-KB Cache Organization.............................................................................................. 9-39.3 Cache Lookup .................................................................................................................. 9-39.4 Cache Control .................................................................................................................. 9-59.4.1 L1 Cache Control and Status Register 0 (L1CSR0) .................................................... 9-59.4.2 L1 Cache Control and Status Register 1 (L1CSR1) .................................................... 9-99.4.3 L1 Cache Configuration Register 0 (L1CFG0) ......................................................... 9-109.4.4 L1 Cache Configuration Register 1 (L1CFG1) ......................................................... 9-119.5 Data Cache Software Coherency ................................................................................... 9-129.6 Address Aliasing............................................................................................................ 9-129.7 Cache Operation ............................................................................................................ 9-12


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9.7.1 Cache Enable/Disable ................................................................................................ 9-139.7.2 Cache Fills ................................................................................................................. 9-139.7.3 Cache Line Replacement ........................................................................................... 9-149.7.4 Cache Miss Access Ordering..................................................................................... 9-149.7.5 Cache-Inhibited Accesses .......................................................................................... 9-159.7.6 Guarded Accesses ...................................................................................................... 9-159.7.7 Cache-Inhibited Guarded Accesses ........................................................................... 9-159.7.8 Cache Invalidation ..................................................................................................... 9-159.7.9 Cache Flush/Invalidate by Set and Way .................................................................... 9-169.7.9.1 L1 Flush/Invalidate Register 0 (L1FINV0) ........................................................... 9-169.7.9.2 L1 Flush/Invalidate Register 1 (L1FINV1) ........................................................... 9-179.8 Cache Parity and EDC Protection.................................................................................. 9-189.8.1 Cache Error Action Control....................................................................................... 9-199.8.1.1 L1CSR0[DCEA]/L1CSR1[ICEA] = 00, Machine Check Generation on Error .... 9-199.8.1.2 L1CSR0[DCEA]/L1CSR1[ICEA] = 01, Correction/Auto-invalidation on Error . 9-209.8.1.2.1 Instruction Cache Errors .................................................................................... 9-209.8.1.2.2 Data Cache Errors.............................................................................................. 9-219.8.1.2.3 Data cache line flush or invalidation due to reservation instructions (l[b,h,w]arx,

st[b,h,w]cx.)................................................................................................... 9-229.8.2 Parity/EDC Error Handling for Cache Control Operations and Instructions ............ 9-229.8.2.1 L1FINV0/L1FINV1 Operations ............................................................................ 9-239.8.2.2 Cache touch instructions (dcbt, dcbtst, icbt).......................................................... 9-239.8.2.3 icbi instructions...................................................................................................... 9-239.8.2.4 dcbi instructions..................................................................................................... 9-239.8.2.5 dcbst instructions ................................................................................................... 9-249.8.2.6 dcbf Instructions ................................................................................................... 9-249.8.2.7 dcbz Instructions.................................................................................................... 9-259.8.2.8 Cache Locking Instructions (dcbtls, dcbtstls, dcblc, icbtls, icblc)......................... 9-259.8.3 Cache Inhibited Accesses and Parity/EDC Errors..................................................... 9-269.8.4 Snoop Operations and Parity/EDC Errors ................................................................. 9-269.8.5 EDC Checkbit/Syndrome Coding Scheme Generation—Icache............................... 9-269.8.6 EDC Checkbit/Syndrome Coding Scheme Generation—Dcache ............................. 9-289.8.7 Cache Error Injection................................................................................................. 9-289.8.8 Cache Error Cross-Signaling ..................................................................................... 9-299.9 Push and Store Buffers................................................................................................... 9-299.10 Cache Management Instructions.................................................................................... 9-309.10.1 Instruction Cache Block Invalidate (icbi) Instruction................................................ 9-309.10.2 Instruction Cache Block Touch (icbt) Instruction ..................................................... 9-309.10.3 Data Cache Block Allocate (dcba) Instruction .......................................................... 9-309.10.4 Data Cache Block Flush (dcbf) Instruction ............................................................... 9-309.10.5 Data Cache Block Invalidate (dcbi) Instruction ........................................................ 9-31


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9.10.6 Data Cache Block Store (dcbst) Instruction .............................................................. 9-319.10.7 Data Cache Block Touch (dcbt) Instruction .............................................................. 9-319.10.8 Data Cache Block Touch for Store (dcbtst) Instruction............................................. 9-319.10.9 Data Cache Block set to Zero (dcbz) Instruction....................................................... 9-319.11 Touch Instructions.......................................................................................................... 9-329.12 Cache Line Locking/Unlocking Unit............................................................................. 9-329.12.1 Overview.................................................................................................................... 9-329.12.2 Instruction Details...................................................................................................... 9-349.12.3 Effects of Other Cache Instructions on Locked Lines ............................................... 9-419.12.4 Flash Clearing of Lock Bits ....................................................................................... 9-419.13 Cache Instructions and Exceptions ................................................................................ 9-429.13.1 Exception Conditions for Cache Instructions ............................................................ 9-429.13.2 Transfer Type Encodings for Cache Management Instructions................................. 9-439.14 Sequential Consistency .................................................................................................. 9-449.15 Self-Modifying Code Requirements .............................................................................. 9-449.16 Page Table Control Bits ................................................................................................. 9-459.16.1 Write-through Stores.................................................................................................. 9-459.16.2 Cache-Inhibited Accesses .......................................................................................... 9-459.16.3 Memory Coherence Required.................................................................................... 9-459.16.4 Guarded Storage ........................................................................................................ 9-459.16.5 Misaligned Accesses and the Endian (E) Bit............................................................. 9-459.17 Reservation Instructions and Cache Interactions........................................................... 9-469.18 Effect of Hardware Debug on Cache Operation ............................................................ 9-469.19 Cache Memory Access For Debug/Error Handling....................................................... 9-469.19.1 Cache Memory Access via Software ......................................................................... 9-469.19.2 Cache Memory Access Through JTAG/OnCE Port .................................................. 9-489.19.3 Cache Debug Access Control Register (CDACNTL) ............................................... 9-489.19.3.1 Cache Debug Access Data Register (CDADATA) ................................................ 9-499.20 Hardware Debug (Cache) Control Register 0................................................................ 9-509.21 Hardware Debug (Cache) Coherency ............................................................................ 9-519.21.1 Coherency Protocol.................................................................................................... 9-529.21.2 Snoop Command Port................................................................................................ 9-539.21.3 Snoop Request Queue................................................................................................ 9-549.21.4 Snoop Lookup Operation........................................................................................... 9-559.21.5 Snoop Errors .............................................................................................................. 9-559.21.6 Snoop Collisions ........................................................................................................ 9-559.21.7 Snoop Synchronization .............................................................................................. 9-569.21.7.1 Synchronization Port Request................................................................................ 9-569.21.7.2 Snoop Command Port Request .............................................................................. 9-569.21.8 Starvation Control...................................................................................................... 9-569.21.9 Queue Flow Control................................................................................................... 9-57


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9.21.10 Snooping in Low Power States .................................................................................. 9-57

Chapter 10 Memory Management Unit

10.1 Overview........................................................................................................................ 10-110.2 Effective to Real Address Translation ........................................................................... 10-110.2.1 Effective Addresses ................................................................................................... 10-110.2.2 Address Spaces .......................................................................................................... 10-210.2.3 Process ID.................................................................................................................. 10-210.2.4 Translation Flow ........................................................................................................ 10-210.2.5 Permissions ................................................................................................................ 10-410.2.6 Restrictions on 1-KB and 2-KB Page Size Usage ..................................................... 10-510.3 Translation Lookaside Buffer ........................................................................................ 10-510.4 Configuration Information ............................................................................................. 10-610.4.1 MMU Configuration Register (MMUCFG) .............................................................. 10-610.4.2 TLB0 Configuration Register (TLB0CFG) ............................................................... 10-710.4.3 TLB1 Configuration Register (TLB1CFG) ............................................................... 10-810.5 Software Interface and TLB Instructions....................................................................... 10-910.5.1 TLB Read Entry Instruction (tlbre) ........................................................................... 10-910.5.2 TLB Write Entry Instruction (tlbwe) ....................................................................... 10-1010.5.3 TLB Search Instruction (tlbsx) ................................................................................ 10-1010.5.4 TLB Invalidate (tlbivax) Instruction........................................................................ 10-1110.5.5 TLB Synchronize Instruction (tlbsync) ................................................................... 10-1210.6 TLB Operations ........................................................................................................... 10-1210.6.1 Translation Reload ................................................................................................... 10-1210.6.2 Reading the TLB...................................................................................................... 10-1310.6.3 Writing the TLB....................................................................................................... 10-1310.6.4 Searching the TLB................................................................................................... 10-1310.6.5 TLB Miss Exception Update ................................................................................... 10-1310.6.6 IPROT Invalidation Protection ................................................................................ 10-1310.6.7 TLB Load on Reset.................................................................................................. 10-1410.6.8 The G bit .................................................................................................................. 10-1410.7 MMU Control Registers .............................................................................................. 10-1410.7.1 Data Exception Address Register (DEAR).............................................................. 10-1510.7.2 MMU Control and Status Register 0 (MMUCSR0) ................................................ 10-1510.7.3 MMU Assist Registers (MAS) ................................................................................ 10-1610.7.4 MAS Register Updates ............................................................................................ 10-2110.8 TLB Coherency Control .............................................................................................. 10-2110.9 Core Interface Operation for MMU Control Instructions............................................ 10-2210.9.1 Transfer Type Encodings for MMU Control Instructions ....................................... 10-22


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10.10 Effect of Hardware Debug on MMU Operation .......................................................... 10-2310.11 External Translation Alterations for Realtime Systems............................................... 10-23

Chapter 11 External Core Complex Interfaces

11.1 Signal Index ................................................................................................................... 11-211.2 Signal Descriptions ...................................................................................................... 11-1011.2.1 e200 Processor Clock (m_clk)................................................................................. 11-1011.2.2 Reset-related Signals................................................................................................ 11-1011.2.2.1 Power-on Reset (m_por).......................................................................................11-1111.2.2.2 Reset (p_reset_b) ..................................................................................................11-1111.2.2.3 Watchdog Reset Status (p_wrs[0:1]) ....................................................................11-1111.2.2.4 Debug Reset Control (p_dbrstc[0:1]) ...................................................................11-1111.2.2.5 Reset Base (p_rstbase[0:29]) ............................................................................... 11-1211.2.2.6 Reset Endian Mode (p_rst_endmode) ................................................................. 11-1211.2.2.7 Reset VLE Mode (p_rst_vlemode)...................................................................... 11-1211.2.2.8 JTAG/OnCE Reset (j_trst_b) ............................................................................... 11-1211.2.3 Address and Data Buses .......................................................................................... 11-1211.2.3.1 Address Bus (p_d_haddr[31:0], p_i_haddr[31:0]) .............................................. 11-1211.2.3.2 Read Data Bus (p_d_hrdata[63:0], p_i_hrdata[63:0]) ......................................... 11-1211.2.3.3 Write Data Bus (p_d_hwdata[63:0]).................................................................... 11-1311.2.4 Transfer Attribute Signals........................................................................................ 11-1311.2.4.1 Transfer Type (p_d_htrans[1:0], p_i_htrans[1:0]) ............................................... 11-1411.2.4.2 Write (p_d_hwrite, p_i_hwrite) ........................................................................... 11-1411.2.4.3 Transfer Size (p_d_hsize[1:0], p_i_hsize[1:0]) ................................................... 11-1411.2.4.4 Burst Type (p_d_hburst[2:0], p_i_hburst[2:0]) ................................................... 11-1511.2.4.5 Protection Control (p_d_hprot[5:0], p_i_hprot[5:0]) .......................................... 11-1511.2.4.6 Data Transfer Error (p_d_htrans_derr) ................................................................ 11-1711.2.4.7 Globally Coherent Access—(p_d_gbl)................................................................ 11-1711.2.4.8 Cache Way Replacement (p_d_wayrep[0:1], p_i_wayrep[0:1]) ......................... 11-1711.2.5 Byte Lane Specification........................................................................................... 11-1711.2.5.1 Unaligned Access (p_d_hunalign, p_i_hunalign)................................................ 11-1711.2.5.2 Byte Strobes (p_d_hbstrb[7:0], p_i_hbstrb[7:0])................................................. 11-1811.2.6 Transfer Control Signals .......................................................................................... 11-2811.2.6.1 Transfer Ready (p_d_hready, p_i_hready) .......................................................... 11-2811.2.6.2 Transfer Response (p_d_hresp[2:0], p_i_hresp[1:0]) .......................................... 11-2811.2.6.3 Bus Stall Global Write Request (p_stall_bus_gwrite) ......................................... 11-2911.2.7 AHB Clock Enable Signals...................................................................................... 11-2911.2.7.1 Instruction AHB Clock Enable (p_i_ahb_clken)................................................. 11-2911.2.7.2 Data AHB Clock Enable (p_d_ahb_clken).......................................................... 11-29


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11.2.8 Master ID Configuration Signals............................................................................. 11-3011.2.8.1 CPU Master ID (p_masterid[3:0]) ....................................................................... 11-3011.2.8.2 Nexus Master ID (nex_masterid[3:0])................................................................. 11-3011.2.9 Coherency Control Signals ...................................................................................... 11-3011.2.9.1 Snoop Ready (p_snp_rdy) ................................................................................... 11-3011.2.9.2 Snoop Request (p_snp_req)................................................................................. 11-3011.2.9.3 Snoop Command Input (p_snp_cmd_in[0:1]) ..................................................... 11-3111.2.9.4 Snoop Request ID Input (p_snp_id_in[0:3]) ....................................................... 11-3111.2.9.5 Snoop Address Input (p_snp_addr_in[0:26]) ...................................................... 11-3111.2.9.6 Snoop Acknowledge (p_snp_ack) ....................................................................... 11-3111.2.9.7 Snoop Request ID Output (p_snp_id_out[0:3])................................................... 11-3211.2.9.8 Snoop Response (p_snp_resp[0:4]) ..................................................................... 11-3211.2.9.9 Cache Stalled (p_cac_stalled).............................................................................. 11-3211.2.9.10 Data Cache Enabled (p_d_cache_en) .................................................................. 11-3211.2.10 Memory Synchronization Control Signals .............................................................. 11-3311.2.10.1 Synchronization Request In (p_sync_req_in)...................................................... 11-3311.2.10.2 Synchronization Request Acknowledge Out (p_sync_ack_out) ......................... 11-3311.2.10.3 Synchronization Request Out (p_sync_req_out) ................................................. 11-3311.2.10.4 Synchronization Request Acknowledge In (p_sync_ack_in) .............................. 11-3411.2.11 Interrupt Signals....................................................................................................... 11-3411.2.11.1 External Input Interrupt Request (p_extint_b)..................................................... 11-3411.2.11.2 Critical Input Interrupt Request (p_critint_b)...................................................... 11-3411.2.11.3 Nonmaskable Input Interrupt Request (p_nmi_b) ............................................... 11-3411.2.11.4 Interrupt Pending (p_ipend)................................................................................. 11-3511.2.11.5 Auto-vector (p_avec_b) ....................................................................................... 11-3511.2.11.6 Interrupt Vector Offset (p_voffset[0:15]) ............................................................ 11-3511.2.11.7 Interrupt Vector Acknowledge (p_iack) .............................................................. 11-3511.2.11.8 Machine Check (p_mcp_b).................................................................................. 11-3611.2.12 Lockstep Enable Signal (p_lkstep_en) .................................................................... 11-3611.2.13 Cache Error Cross-signaling Signals ....................................................................... 11-3611.2.13.1 Cache Tag Error Out (p_[d,i]_cache_tagerr_out) ................................................ 11-3611.2.13.2 Cache Data Error Out (p_[d,i]_cache_dataerr_out)............................................. 11-3711.2.13.3 Cache Push Data Error Out (p_d_pusherr_out)................................................... 11-3711.2.13.4 Cache Error Address Out (p_[d,i]_cerraddr_out[0:31]) ...................................... 11-3711.2.13.5 Cache Tag Error Way(s) Out (p_[d,i]_tagerrway_out[0:3]) ................................ 11-3711.2.13.6 Cache Dirty Error Way(s) Out (p_d_drterrway_out[0:3]) ................................... 11-3711.2.13.7 Cache Lock Error Way(s) Out (p_[d,i]_lkerrway_out[0:3])................................ 11-3811.2.13.8 Cache Data Error In (p_[d,i]_cache_dataerr_in) ................................................. 11-3811.2.13.9 Cache Push Data Error In (p_d_pusherr_in) ....................................................... 11-3811.2.13.10 Cache Tag Error In (p_[d,i]_cache_tagerr_in)..................................................... 11-3811.2.13.11 Cache Tag Error Way(s) In (p_[d,i]_tagerrway_in[0:3])..................................... 11-38


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11.2.13.12 Cache Dirty Error Way(s) In (p_d_drterrway_in[0:3])........................................ 11-3911.2.13.13 Cache Lock Error Way(s) in (p_[d,i]_lkerrway_in[0:3])..................................... 11-3911.2.14 External Translation Alteration Signals................................................................... 11-3911.2.14.1 External PID Enable (p_extpid_en)..................................................................... 11-3911.2.14.2 External PID In (p_extpid[6:7])........................................................................... 11-3911.2.15 Timer Facility Signals.............................................................................................. 11-4011.2.15.1 Timer Disable (p_tbdisable) ................................................................................ 11-4011.2.15.2 Timer External Clock (p_tbclk) ........................................................................... 11-4011.2.15.3 Timer Interrupt Status (p_tbint) ........................................................................... 11-4011.2.16 Processor Reservation Signals ................................................................................. 11-4011.2.16.1 CPU Reservation Status (p_rsrv)......................................................................... 11-4011.2.16.2 CPU Reservation Clear (p_rsrv_clr).................................................................... 11-4011.2.17 Miscellaneous Processor Signals ............................................................................. 11-4111.2.17.1 CPU ID (p_cpuid[0:7]) ........................................................................................ 11-4111.2.17.2 PID0 outputs (p_pid0[0:7]).................................................................................. 11-4111.2.17.3 PID0 Update (p_pid0_updt) ................................................................................ 11-4111.2.17.4 System Version (p_sysvers[0:31]) ....................................................................... 11-4111.2.17.5 Processor Version (p_pvrin[16:31])..................................................................... 11-4111.2.17.6 HID1 System Control (p_hid1_sysctl[0:7])......................................................... 11-4211.2.17.7 Debug Event Outputs (p_devnt_out[0:7]) ........................................................... 11-4211.2.18 Processor State Signals ............................................................................................ 11-4211.2.18.1 Processor Mode (p_mode[0:3]) ........................................................................... 11-4211.2.18.2 Processor Execution Pipeline Status (p_pstat_pipe0[0:5], p_pstat_pipe1[0:5]).. 11-4211.2.18.3 Branch Prediction Status (p_brstat[0:1]) ............................................................. 11-4411.2.18.4 Processor Exception Enable MSR Values (p_msr_EE, p_msr_CE, p_msr_DE,

p_msr_ME)...................................................................................................... 11-4411.2.18.5 Processor Return from Interrupt (p_rfi, p_rfci, p_rfdi, p_rfmci)......................... 11-4411.2.18.6 Processor Machine Check (p_mcp_out) .............................................................. 11-4411.2.19 Power Management Control Signals ....................................................................... 11-4511.2.19.1 Wait, Halt, Stop Signals ....................................................................................... 11-4511.2.19.2 Low-Power Mode Signals (p_doze, p_nap, p_sleep) .......................................... 11-4511.2.19.3 Wakeup (p_wakeup) ............................................................................................ 11-4511.2.20 Performance Monitor Signals .................................................................................. 11-4611.2.21 Debug Event Input Signals ...................................................................................... 11-4711.2.21.1 Unconditional Debug Event (p_ude) ................................................................... 11-4711.2.21.2 External Debug Event 1 (p_devt1) ...................................................................... 11-4711.2.21.3 External Debug Event 2 (p_devt2) ...................................................................... 11-4711.2.21.4 14.2.22 Debug Event Output Signals (p_devnt_out[0:7]) ................................... 11-4811.2.22 Debug/Emulation (Nexus 1/OnCE) Support Signals............................................... 11-4811.2.22.1 OnCE Enable (jd_en_once) ................................................................................. 11-4811.2.22.2 Debug Session (jd_debug_b)............................................................................... 11-48


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11.2.22.3 Debug Request (jd_de_b) .................................................................................... 11-4911.2.22.4 DE_b Active High Output Enable (jd_de_en)..................................................... 11-4911.2.22.5 Processor Clock On (jd_mclk_on)....................................................................... 11-4911.2.22.6 Watchpoint Events (jd_watchpt[0:26])................................................................ 11-4911.2.23 Debug Lockstep Cross-signaling Signals ................................................................ 11-4911.2.23.1 Debug Request EDM In (p_dbgrq_edm_in)........................................................ 11-5011.2.23.2 Debug Go Request In (p_dbg_go_in).................................................................. 11-5011.2.23.3 Debug Request EDM Out (p_dbgrq_edm_out) ................................................... 11-5011.2.23.4 Debug Go Request Out (p_dbg_go_out) ............................................................. 11-5011.2.24 Development Support (Nexus 3) Signals................................................................. 11-5011.2.25 JTAG Support Signals ............................................................................................. 11-5111.2.25.1 JTAG/OnCE Serial Input (j_tdi) .......................................................................... 11-5111.2.25.2 JTAG/OnCE Serial Clock (j_tclk) ....................................................................... 11-5111.2.25.3 JTAG/OnCE Serial Output (j_tdo) ...................................................................... 11-5111.2.25.4 JTAG/OnCE Test Mode Select (j_tms) ............................................................... 11-5211.2.25.5 JTAG/OnCE Test Reset (j_trst_b) ....................................................................... 11-5211.2.25.6 TAP Controller State Indicator Signals ............................................................... 11-5211.2.25.7 Register Select (j_gp_regsel) ............................................................................... 11-5311.2.25.8 Enable Once Register Select (j_en_once_regsel) ................................................ 11-5311.2.25.9 External Nexus Register Select (j_nexus_regsel)................................................ 11-5311.2.25.10 External LSRL Register Select (j_lsrl_regsel) .................................................... 11-5411.2.25.11 Serial Data (j_serial_data) ................................................................................... 11-5411.2.25.12 Key Data In (j_key_in) ........................................................................................ 11-5511.2.26 JTAG ID Signals ...................................................................................................... 11-5611.2.26.1 JTAG ID Sequence (j_id_sequence[0:1]) ............................................................ 11-5611.2.26.2 JTAG ID Sequence (j_id_sequence[2:9]) ............................................................ 11-5611.2.26.3 JTAG ID Version (j_id_version[0:3]) .................................................................. 11-5711.3 Timing Diagrams ......................................................................................................... 11-5711.3.1 AHB Clock Enable and the Internal HCLK ............................................................ 11-5711.3.2 Processor Instruction/Data Transfers ....................................................................... 11-5811.3.2.1 Basic Read Transfer Cycles ................................................................................. 11-6011.3.2.2 Read Transfer with Wait State ............................................................................. 11-6211.3.2.3 Basic Write Transfer Cycles ................................................................................ 11-6311.3.2.4 Write Transfer with Wait States ........................................................................... 11-6511.3.2.5 Read and Write Transfers .................................................................................... 11-6611.3.2.6 Misaligned Accesses............................................................................................ 11-7011.3.2.7 Burst Accesses ..................................................................................................... 11-7311.3.2.8 Error Termination Operation ............................................................................... 11-7611.3.3 Memory Synchronization Control Operation .......................................................... 11-8011.3.4 Cache Error Cross-signaling Operation................................................................... 11-8411.3.4.1 Cross-signaling with Machine Check Operation Selected .................................. 11-85


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11.3.4.2 Cross-signaling with Auto-invalidation Operation Selected ............................... 11-8611.3.5 Cache Coherency Interface Operation................................................................... 11-10111.3.5.1 Stop Mode Entry/Exit and Snoop Ready Signaling .......................................... 11-10611.3.6 Debug Lockstep Cross-signaling Operation .......................................................... 11-10911.3.6.1 Debug Entry Cross-signaling..............................................................................11-11011.3.6.2 Debug Exit Cross-signaling................................................................................11-11311.3.6.3 Update_DR State Cross-signaling ......................................................................11-11611.3.7 Power Management ................................................................................................11-11811.3.8 Interrupt Interface ...................................................................................................11-11811.3.9 Time Base Interface ............................................................................................... 11-12211.3.10 JTAG Test Interface ............................................................................................... 11-122

Chapter 12 Power Management

12.1 Power Management ....................................................................................................... 12-112.1.1 Active State................................................................................................................ 12-112.1.2 Waiting State .............................................................................................................. 12-112.1.3 Halted State................................................................................................................ 12-212.1.4 Stopped State ............................................................................................................. 12-212.1.5 Power Management Pins ........................................................................................... 12-312.1.6 Power Management Control Bits............................................................................... 12-412.1.7 Software Considerations for Power Management using Wait Instructions ............... 12-412.1.8 Software Considerations for Power Management using Doze, Nap, or Sleep .......... 12-412.1.9 Debug Considerations for Power Management ......................................................... 12-5

Chapter 13 Debug Support

13.1 Overview........................................................................................................................ 13-113.1.1 Software Debug Facilities.......................................................................................... 13-113.1.1.1 Power ISA Embedded Category Compatibility..................................................... 13-213.1.2 Additional Debug Facilities ....................................................................................... 13-213.1.3 Hardware Debug Facilities ........................................................................................ 13-213.1.4 Software/Hardware Debug Resource Sharing ........................................................... 13-313.1.4.1 Simultaneous Hardware and Software Debug Event Handing.............................. 13-313.2 Software Debug Events and Exceptions ........................................................................ 13-413.2.1 Instruction Address Compare Event .......................................................................... 13-513.2.2 Data Address Compare Event.................................................................................... 13-613.2.2.1 Data Address Compare Event Status Updates....................................................... 13-713.2.3 Linked Instruction Address and Data Address Compare Event .............................. 13-17


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13.2.4 Trap Debug Event .................................................................................................... 13-1713.2.5 Branch Taken Debug Event ..................................................................................... 13-1713.2.6 Instruction Complete Debug Event.......................................................................... 13-1813.2.7 Interrupt Taken Debug Event................................................................................... 13-1813.2.8 Critical Interrupt Taken Debug Event...................................................................... 13-1813.2.9 Return Debug Event................................................................................................. 13-1913.2.10 Critical Return Debug Event.................................................................................... 13-1913.2.11 Debug Counter Debug Event................................................................................... 13-1913.2.12 External Debug Event.............................................................................................. 13-1913.2.13 Unconditional Debug Event..................................................................................... 13-1913.3 Debug Registers ........................................................................................................... 13-2013.3.1 Debug Address and Value Registers........................................................................ 13-2013.3.2 Debug Counter Register (DBCNT) ......................................................................... 13-2113.3.3 Debug Control and Status Registers ........................................................................ 13-2213.3.3.1 Debug Control Register 0 (DBCR0).................................................................... 13-2213.3.3.2 Debug Control Register 1 (DBCR1).................................................................... 13-2513.3.3.3 Debug Control Register 2 (DBCR2).................................................................... 13-2713.3.3.4 Debug Control Register 3 (DBCR3).................................................................... 13-3013.3.3.5 Debug Control Register 4 (DBCR4).................................................................... 13-3613.3.3.6 Debug Control Register 5 (DBCR5).................................................................... 13-3713.3.3.7 Debug Control Register 6 (DBCR6).................................................................... 13-3913.3.3.8 Debug Status Register (DBSR) ........................................................................... 13-4013.3.4 Debug External Resource Control Register (DBERC0).......................................... 13-4313.3.5 Debug Event Select Register (DEVENT)................................................................ 13-5013.3.6 Debug Data Acquisition Message Register (DDAM) ............................................. 13-5113.4 External Debug Support............................................................................................... 13-5113.4.1 External Debug Registers ........................................................................................ 13-5213.4.1.1 External Debug Control Register 0 (EDBCR0)................................................... 13-5313.4.1.2 External Debug Status Register 0 (EDBSR0)...................................................... 13-5313.4.1.3 External Debug Status Register Mask 0 (EDBSRMSK0) ................................... 13-5613.4.2 OnCE Introduction................................................................................................... 13-5713.4.3 JTAG/OnCE Pins ..................................................................................................... 13-6013.4.4 OnCE Internal Interface Signals .............................................................................. 13-6013.4.4.1 CPU Debug Request (dbg_dbgrq) ....................................................................... 13-6013.4.4.2 CPU Debug Acknowledge (cpu_dbgack)............................................................ 13-6113.4.4.3 CPU Address, Attributes ..................................................................................... 13-6113.4.4.4 CPU Data ............................................................................................................. 13-6113.4.5 OnCE Interface Signals ........................................................................................... 13-6113.4.5.1 OnCE Enable (jd_en_once) ................................................................................. 13-6113.4.5.2 OnCE Debug Request/Event (jd_de_b, jd_de_en) .............................................. 13-6113.4.5.3 e200 OnCE Debug Output (jd_debug_b) ............................................................ 13-62


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13.4.5.4 e200 CPU Clock On Input (jd_mclk_on) ............................................................ 13-6213.4.5.5 Watchpoint Events (jd_watchpt[0:29])................................................................ 13-6213.4.6 e200 OnCE Controller and Serial Interface............................................................. 13-6313.4.6.1 e200 OnCE Status Register ................................................................................. 13-6313.4.6.2 e200 OnCE Command Register (OCMD)........................................................... 13-6413.4.6.3 e200 OnCE Control Register (OCR) ................................................................... 13-6813.4.7 Access to Debug Resources..................................................................................... 13-7013.4.8 Methods of Entering Debug Mode .......................................................................... 13-7213.4.8.1 External Debug Request During RESET............................................................. 13-7213.4.8.2 Debug Request During RESET ........................................................................... 13-7213.4.8.3 Debug Request During Normal Activity ............................................................. 13-7313.4.8.4 Debug Request During Waiting, Halted, or Stopped State.................................. 13-7313.4.8.5 Software Request During Normal Activity ......................................................... 13-7313.4.8.6 Debug Notify Halt Instructions ........................................................................... 13-7313.4.9 CPU Status and Control Scan Chain Register (CPUSCR) ...................................... 13-7413.4.9.1 Instruction Register (IR) ...................................................................................... 13-7413.4.9.2 Control State Register (CTL)............................................................................... 13-7513.4.9.3 Program Counter Register (PC)........................................................................... 13-7813.4.9.4 Write-Back Bus Register (WBBR[low], WBBR[high])...................................... 13-7913.4.9.5 Machine State Register (MSR) ............................................................................ 13-7913.4.9.6 Exiting Debug Mode and Interrupt Blocking ...................................................... 13-7913.4.10 Instruction Address FIFO Buffer (PC FIFO)........................................................... 13-8013.4.10.1 PC FIFO............................................................................................................... 13-8013.4.11 Reserved Registers (Reserved) ................................................................................ 13-8213.5 Watchpoint Support ..................................................................................................... 13-8213.6 MMU and Cache Operation During Debug................................................................. 13-8413.7 Cache Array Access During Debug............................................................................. 13-8513.8 Basic Steps for Enabling, Using, and Exiting External Debug Mode ......................... 13-8513.9 Parallel Signature Unit................................................................................................. 13-8613.9.1 Parallel Signature Control Register (PSCR)............................................................ 13-8813.9.2 Parallel Signature Status Register (PSSR)............................................................... 13-8913.9.3 Parallel Signature High Register (PSHR)................................................................ 13-8913.9.4 Parallel Signature Low Register (PSLR) ................................................................. 13-8913.9.5 Parallel Signature Counter Register (PSCTR)......................................................... 13-9013.9.6 Parallel Signature Update High Register (PSUHR) ................................................ 13-9013.9.7 Parallel Signature Update Low Register (PSULR).................................................. 13-90

Chapter 14 Nexus 3 Module

14.1 Introduction.................................................................................................................... 14-1


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14.1.1 Terms and Definitions................................................................................................ 14-114.1.2 Feature List ................................................................................................................ 14-214.1.3 Functional Block Diagram......................................................................................... 14-414.2 Enabling Nexus 3 Operation.......................................................................................... 14-414.3 TCODEs Supported ....................................................................................................... 14-514.4 Nexus 3 Programmer’s Model ..................................................................................... 14-1014.4.1 Client Select Control (CSC) .................................................................................... 14-1214.4.2 Port Configuration Register (PCR)—reference only............................................... 14-1314.4.3 Nexus Development Control Register 1 (DC1)....................................................... 14-1414.4.4 Nexus Development Control Register 2 (DC2)....................................................... 14-1514.4.5 Nexus Development Control Register 3 (DC3)....................................................... 14-1814.4.6 Nexus Development Control Register 4 (DC4)....................................................... 14-1914.4.7 Development Status Register (DS) .......................................................................... 14-2114.4.8 Watchpoint Trigger Registers (WT, PTSTC, PTETC, DTSTC, DTETC) ............... 14-2114.4.9 Nexus Watchpoint Mask Register (WMSK)............................................................ 14-2714.4.10 Nexus Overrun Control Register (OVCR)............................................................... 14-2814.4.11 Data Trace Control Register (DTC)......................................................................... 14-2914.4.12 Data Trace Start Address Registers (DTSA1–4) ..................................................... 14-3014.4.13 Data Trace End Address Registers (DTEA1–4) ...................................................... 14-3114.4.14 Read/Write Access Control/Status (RWCS) ............................................................ 14-3214.4.15 Read/Write Access Data (RWD) ............................................................................. 14-3314.4.16 Read/Write Access Address (RWA) ........................................................................ 14-3514.5 JTAG/OnCE Nexus 3 Register Access ........................................................................ 14-3514.6 Nexus Message Fields ................................................................................................. 14-3614.6.1 TCODE Field........................................................................................................... 14-3614.6.2 Source ID Field (SRC)............................................................................................. 14-3614.6.3 Relative Address Field (U-ADDR).......................................................................... 14-3614.6.4 Full Address Field (F-ADDR) ................................................................................. 14-3714.6.5 Address Space Indication Field (MAP) ................................................................... 14-3714.7 Nexus Message Queues ............................................................................................... 14-3814.7.1 Message Queue Overrun.......................................................................................... 14-3814.7.2 CPU Stall ................................................................................................................. 14-3814.7.3 Message Suppression............................................................................................... 14-3814.7.4 Nexus Message Priority ........................................................................................... 14-3914.7.5 Data Acquisition Message Priority Loss Response ................................................. 14-4014.7.6 Ownership Trace Message Priority Loss Response................................................. 14-4014.7.7 Program Trace Message Priority Loss Response..................................................... 14-4014.7.8 Data Trace Message Priority Loss Response........................................................... 14-4014.8 Debug Status Messages................................................................................................ 14-4114.9 Error Messages ............................................................................................................ 14-4114.10 Ownership Trace .......................................................................................................... 14-41


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14.10.1 Overview.................................................................................................................. 14-4114.10.2 Ownership Trace Messaging (OTM) ....................................................................... 14-4214.11 Program Trace.............................................................................................................. 14-4214.11.1 Branch Trace Messaging Types ............................................................................... 14-4314.11.1.1 e200 Indirect Branch Message Instructions......................................................... 14-4314.11.1.2 e200 Direct Branch Message Instructions ........................................................... 14-4414.11.1.3 BTM Using Branch History Messages ................................................................ 14-4414.11.1.4 BTM using Traditional Program Trace Messages ............................................... 14-4414.11.2 BTM Message Format

e200z7 Power Architecture Core Reference Manual · 2016-11-23 · e200z7 Power Architecture Core...

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