E-Voting Machine - Design Presentation

• Group M1• Bohyun Jessica Kim• Jonathan Chiang• Chi Ho Yoon• Donald Cober

Mon, Nov 17ExtractedRC simulation More Layout

Secure Electronic Voting Terminal

Data Bus

Machine Init FSM

User ID FSM

Selection FSM

ConfirmationFSM Display

User ID SRAM

Message ROM

Card Reader

Fingerprint Scanner

Encryption Key SRAM

User Input

Write-in SRAM

Choice SRAM

TX_Check

Selection Counter

Key Register

XOR

8 bit Full Adder

8 bit Full Adder

8 bit Full Adder

8 bit Full Adder

XOR

8 bit MUX0 1

8 bit MUX0 1

8 bit MUX0 1

16 bit Add/Sub

0 18 bit MUX

16bitREG

8-bitREG

COMMS Register

Shift Registe

r In

Shift Register Out

constant init

COMMSExtracted RC Simulations functioning

Buffering added to fix glitches

Unbuffered Simulation

Buffered Simulation

FSMExtraceted RC simulations work

33% of the layout still needs to be cleaned up

FSM Layout

FSM Encoder Layout

Set/ Reset Flip Flop

6 state encoder

10 state encoder

12 state encoder

2 Bit Counter

Extended Counters

D Flip Flop Layout

“!J” Toggle / Reset flip flop

2bit CounterLayout

6bit Counter Layout

FSM Simulation (extractedRC)

SRAMRow decoders: Complete and LVSingSRAM layout: Complete and LVSing

ExtractedRC Simulation In Progress Next time: More Simulation for ExtractedRC

6 bitDecoder ExtractedRC Rise Time

6 bit Decoder ExtractedRC Fall Time

SRAM Cell Write ExtratedRC Simulation

SRAM Cell Write ExtratedRC Rise Time

SRAM Cell Write ExtratedRC Fall Time

SRAM Plus 2 bit Decoder with Tristate Buffers

Area: 48.74 by 17.15 Transistor: 306Density: 0.366

SRAM Plus 3 bit Decoder with Tristate Buffers

Area: 50.94 by 22.86 Transistor: 518Density: 0.445

Extra BlocksSelection counter finished an simulated

Selection Counter

Seleection Counter Simulation

TODO:

Merge Our Cadence Directories

Finish Layout cleanup

Layout: User Input, Key Register, Message ROM

Global Inter connects

Simulations