(I)- Signal, Frequency Spectrum, - Amplifiers, - Frequency Response of Amplifiers, - Logic Inverters
Chap. 2 Diodes - I-V Characteristics, - Physical Operation, - Analysis Diode Ckts, - Small-signal Model and Applications, - Rectifier, Limiter, Clamper, - SPICE Model and Simulation
Chap. 3 BJT - Physical Structure and Mode of Operation - I-V Characteristics at Active mode - Circuit Symbols and Conventions - Analysis of Transistor Circuit at DC - Transistor as a Switch-Cutoff and Saturatiojn - BJT Logic Inverter
Chap. 4 BJT - Small-Signal Equivalent Circuit Model - BJT Amplifier Configurations - Ebers-Moll Model - Internal Capacitances and Second-Order Effects - SPICE Model and Simulation
Chap. 5 MOSFET - Physical Structure and Mode of Operation - I-V Characteristics of the Enhancement MOSFET - Circuit Symbols and Conventions - MOSFET Circuit at DC - CMOS Digital Logic Inverter
Chap. 6 MOSFET - Small-Signal Equivalent Circuit Model - MOSFET Amplifier Configurations - Internal Capacitances and Second-Order Effects - SPICE Model and Simulation
1
Chap. 1 Introduction
What is microelectronics?
Microelectronics refers to the IC technology which is capable of producing ckts that contain
millions of components in a small piece of silicon (chip).
In this course, we shall study
1. the electronic devices that can be used singly (in the discrete ckts) or as components of an
IC chip.
2. the design and analysis of interconnections of these devices
3. the available IC Chips and their application
In this chapter, we will introduce some basic concepts and terminology.
1.1 Signals
Signal is a time-varying quantity that contains information about a variety of things and
activities. The information content of the signal is represented by the changes in its magnitude
as time processes. To extract required information from a set of signals, one needs to process
the signals in some predetermined manner. The signal processing is usually performed by
electronic systems, therefore, the signal must be converted into an electronic signals, e.g., a
voltage or a current.
1.2 Frequency Spectrum of Signals
A signal can be represented either by the manner in which its waveform varies with time (time
domain) or in terms of its frequency spectrum (frequency domain). Frequency Spectrum is a useful
way to characterize a signal, which is obtained through the mathematical tools of Fourier
transform.
Consider a square wave signal of amplitude V and of period T.
Fig. 1.5 Frequency spectrum of the square wave.
After the Fourier transformation, the square-wave signal can be expressed as
( ) T
,tttVtv oooo πωωωω
π 25sin3sinsin4)( 5
1 3 1 =⋅⋅⋅+++=
ωo is the fundamental frequency. The sinusoidal components in the above equation constitute the
frequency spectrum of the square-wave signal.
Fourier transform can be applied to a nonperiodic signal and provides its frequency spectrum as a
continuous function of frequency.
3
The essential parts of the spectra of the signals are usually confined to relatively short segments of
the frequency axis, which is very useful in the processing of such signals.
1.3 Analog and Digital Signals
Analog signal: the magnitude of this signal may have any value, that is, the amplitude may vary
continuously w.r.t time. Electronic circuits that process such signals are called analog circuits.
Examples: most of signals in the real world are analog, such as voice communications and music.
The amplification of such signals is a large part of electronics, and little or No distortion is a
major concern.
4
Digital signal: the signal amplitude is not continuous, but is quantized or digitized at two distinct
levels (binary number system: 0 and 1). The resulting signal then is a sequence of numbers that
represent the magnitudes of the successive signal samples. Since digital circuits deal exclusively
with binary signals, their design is simpler than that of analog circuits.
1.4 Amplifiers
Signal amplification is needed for the processed signals those are too small for reliable processing.
The functional block that accomplishes this task is the signal amplifier.
The requirement of an amplifier is the linearity: the output signal of the amplifier is an exact
replica of that at the input, except for having larger magnitude. That is any change in waveform is
considered to be nonlinear distortion and is undesirable.
Amplifier circuit symbol:
5
Consider a linear amplifier accepts an input signal vI(t) and provides at the output, across a load
resistance RL, an output signal vO(t).
The voltage gain of the amplifier is defined by Av ≡ vO(t)/ vI(t).
The current gain of the amplifier is defined as Ai ≡ iO(t)/ iI(t).
An amplifier also increases the signal power, an important feature that distinguishes an amplifier
from a transformer. For a transformer, the voltage delivered to the load could be greater than the
input voltage, but the power delivered is less than or equal to the power supplied by the signal
source. In the case of amplifier, it has power gain and is defined as
iv II
)(power input )(power load)(gain Power
The amplifier gain could be expressed with a logarithmic measure (decibels).
Specifically, the voltage gain Av can be expressed as 20 logAv dB
the current gain Ai can be expressed as 20 logAi dB
the power gain AP can be expressed as 20 logAP dB
A negative signal gain means that there is a 180o phase difference between input and output signals;
it does not imply that the amplifier is attenuating the signal.
Amplifier Power Supplies
Recall that the amplifier has power gain, which seems to conflict to the principle of energy
6
conservation. The answer is found by observing that amplifiers need dc power supplies for their
operation. The dc sources supply the extra power delivered to the load as well as any power that
might be dissipated in the internal circuit of the amplifier.
The dc power delivered to the amplifier from the dc power supply is
2211 IVIVPdc += , the power drawn from the signal source is PI, and the power dissipated in the
amplifier ( in the form of heat) is denoted Pdiss, then according to the conversation of energy,
dissLIdc PPPP +=+
then, the power efficiency of the amplifier is defined by
(%) 100x(%) 100x dc
Amplifier Saturation
Practically speaking, the amplifier remains linear transfer over a limited range of input and output
voltages. The transfer characteristic is shown as follows. To avoid distorting the output signal, the
input signal swing must be within the linear range of operation. vv A
L IA
L v +− ≤≤
vi(t): incremental signal quantity (lowercase symbol with a lowercase subscript)
vI(t): total instantaneous quantity (lowercase symbol with a uppercase subscript)
Biasing
If the transfer characteristic of an amplifier is nonlinear as shown below. We can use a bias
technique to operate the circuit at a point near the middle of the transfer characteristic. This is
achieved by applying a dc voltage VI and the operating point (also called bias point, quiescent
point) is labeled Q and the corresponding dc voltage at the output is VO. The time-varying signal to
be amplified, vi(t), is then superimposed on the dc bias voltage VI, therefore, the total input vI(t),
vI(t)= VI+ vi(t), varies around VI, the instantaneous operating point moves up and down around the
operating point. The resulting output signal vO(t), vO(t)= VO+ vo(t) with vo(t) = Av vi(t) where Av is
8
the slope of the linear segment of the transfer curve, atQI
O v dv
dvA =
In this manner, linear amplification is achieved with the limitation that the input signal must be
kept sufficiently small.
1.5 Circuit Models for Amplifiers
To be able to apply the resulting amplifier circuit as a building block in a system, one must be able
to characterize, or model, its terminal behavior.
Voltage Amplifiers
The model consists of a voltage-controlled voltage source having a gain factor Avo (voltage gain of
the unloaded amplifier or the open-circuit voltage gain), an input resistance Ri that accounts for the
amplifier draws an input current from the signal source, and an output resistance Ro that accounts
for the change in output voltage as the amplifier is called upon to supply output current to a load.
Consider a signal source vs with a series resistance Rs is fed into the amplifier and connected
at the output to a load resistance RL.
Using the voltage-divide rule, we obtain oL
L ivoo RR
Thus, the voltage gain of this amplifier is given by
oL
+ =≡
It is found that in order not to lose gain in coupling the amplifier output to a load, the output
resistance should be much smaller than the load, i.e., Av→Avo, if Ro << RL.
9
At the input stage, the finite input resistance Ri introduce another voltage-divide action at the input,
with the result that only a fraction of the source signal vs actually reaches the input terminal of the
amplifier; si
=
Again, in order not to lose gain, the input resistance must be much larger than the series resistance
(Ri >> Rs).
L
si
++ =≡
Example: Consider an amplifier composed of a cascade of three stages:
At the Source stage, 909.0 k 100M 1
M 11 = +
v v
At the Stage 1, the voltage gain, 9.9 k 1k 100
k 10010 1
vA
At the Stage 2, the voltage gain, 9.90 k 1k 10
k 10100 2
At the Stage 3, the voltage gain, 909.0 10 010
0 101 3
3 = +
vA
The total gain of the three stages, dB 58.3or 818321 1
==≡ vvv i
s
M 1
100 6
1
==≡ ii
oL
I
1.6 Frequency Response of Amplifiers
We can measure the frequency response of a linear amplifier by
The transfer function T(ω) is defined by ( ) i
o
v vT =ω , At the test frequency ω, the amplifier gain is
characterized by its magnitude |T(ω)| = Vo/Vi, and phase φ =∠ T(ω)
11
RCj sRC
sCR sC
v v
T i
1 )(
Then, the frequency response of this RC circuit is expressed in Bode Plots as shown:
12
RCj sRC
)(
Then, the frequency response of this RC circuit is expressed in Bode Plots as shown:
This is so-called high pass filter,
13
1.7 The Digital Logic Inverter
A logic inverter inverts the logic value of the input signal. Thus for a logic 0 input, the output will
be a logic 1, and vice versa. Consider a possible voltage transfer characteristic (VTC) of an
inverter shown in Fig. 1.29.
As vI < VIL, ⇒ vo = VOH output high level (Logic “1”)
As vI > VIH, ⇒ vo = VOL output low level (Logic “0”)
For VIL < vI < VIH, transition region
Noise Margin:
The insensitivity of the inverter output to the exact value of vI within allowed regions is a great
advantage that digital circuits have over analog circuits. Consider an inverter is driving another
similar inverter, if the output of the driving inverter is high at VOH, we see that we have a “safety
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margin” equal to |VOH - VIH|, that is, if a disturbing signal (“noise”) is superimposed on the output
of the driving inverter, the driven inverter would not be bothered as long as this noise does not
decrease the voltage at its input below VIH.
Thus, the noise margin for high input: NMH≡|VOH - VIH|
Similarily, the noise margin for low input: NML≡|VIL – VOL|
Example:
Logic “1”
Logic “0”
in = 0.5 V logic “0”
1.8 Homework
17, 35
Chap 2 Diodes
In the following chapters, we’ll introduce some basic devices which are generally used in
electronic circuit design, such as diodes, BJTs, and MOSFETs.
2.1 The ideal Diode
The ideal diode may be considered the most fundamental nonlinear circuit element. It is a
two-terminal, nonlinear device having the circuit symbol and I-V characteristic as shown.
15
The I-V characteristic of an ideal diode is highly nonlinear that could be used as a switch, a
rectifier, a clamper, …
Consider the example as shown in Fig. 3.2a:
the diode is obviously conducting, thus its voltage drop is zero
and the current through it will be determined by the voltage supply
and the series resistance, mA 10 k 1
V 10 =
Consider the example as shown in Fig. 3.2b:
The diode is obviously cut off, thus its current will be zero, which means
that the entire 10 V supply will appear as reverse bias across the diode.
Rectifier ()Application:
A rectifier circuit consists of the series connection of a diode D and a resisto
the input voltage vI is a sinusoid wave with the peak voltage of Vp.
r
16
(i) if vI > 0, the diode D is conducting and current flows
through the diode in the forward direction and the voltage
drop across the diode vD= 0. Thus the circuit will have
the equivalent shown in Fig. 3.3c and the output voltage vo = vI
(ii) if vI < 0, the diode D cuts off and the circuit will have the
equivalent shown in Fig. 3.3d, and vo = 0, vD = vI.
The input vI, output vo, and vD wave forms
Transfer characteristic vo versus vI
Thus the circuit rectifies the signal (only positive signal passes and negative signal is blocked) and
hence is called a rectifier. It could be used to generate dc from ac.
Example 1: Fig. 3.4(a) shows a circuit for charging a 12V battery. If vs = 24sinωt, find
(a) the fraction of each cycle during which the diode conducts.
(b) The peak value of the diode current
(c) The max. reverse-bias voltage that appears across the diode.
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Solution:
(i) the diode conducts only when vs = 24sinωt > 12 V, ⇒ sinωt > 1/2, ⇒ π/6 <ωt< 5π/6,
so the conduction range is 5π/6 -π/6=2π/3, ⇒the conducting cycle is 3 1
2 3
(ii) the peak current is given by AId 12.0 100
1224 =
− = ;
(iii) Max. reverse voltage across the diode occurs when vs is at its negative peak =24+12=36 V
Diode Logic Gates Application
Diodes together with resistors can be used to implement digital logic functions.
Example: Find
Y = A
the values of I and V in the following circuit. + B + C “OR” Y= A•B•C “AND”
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Solution: (a)
Assume D1 is “ON”, then the voltage at node B, VB = 0 V,
then D2 is “ON”⇒ V=0 V and 0mA 1 k10
010 2 >=
)10(0 2 >=⇒
So the final result: I = 1 mA and V = 0V
Solution: (b)
Again, Assume D1 is “ON”, then the voltage at node B, VB = 0 V,
then D2 is “ON”⇒ V=0 V and mA 2 k5
010 2 =
The KCL at node B: )assumption (wrong 0mA 1 k10
)10(0 2 <−=⇒
⇒ V3.333.1x1010 mA, 33.1 k 15
)10(10 2 +=+−==
= BD VI =V
⇒the voltage across the diode D1 is –3.3 V, D1 is reverse-biased., so I = 0.
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2.2 Terminal Characteristics of Junction Diode
The real diodes could be fabricated by semiconductor junction, such as Si.
20
1
2
Forward-Bias Region:
. The I-V relationship is closely approximated by )1( / −= TnVv S eIi
Is is called the saturation current, which is a function of the diode geometry and operating temperature (T↑, Is↑). (on the order of 10-13 - 10-15 A)
VT is called the thermal voltage, cut-in voltage or threshold voltage. qkTV /=T
where k = Boltzmann’s constant = 1.38x10-23 J/Kelvin T= the absolute temperature in kelvins q = 1.6x10-19 coulomb at room temperature 25o C, VT = 25.9 mV.
n is the ideality factor, 1≤ n ≤ 2: depends on the fabrication. For an ideal diode, n = 1
. In forward region, if i >> Is (i.e., v ≥ VT), then , the current i increase rapidly as the TnVv SeIi /=
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voltage across the diode changes a little bit. Thus, for a “fully conducting” diode, the voltage drop
lies in a narrow range, approximately 0.6-0.8V. For simplicity, a simple model is set by assuming
that a conducting diode has approximately a 0.7V drop.
Reverse-Bias Region
The reverse current, i ≈ -Is, is mainly due to the leakage effects. The reverse current also increases
with the increase in magnitude of the reverse voltage. As the voltage < -VZK, breakdown voltage,
the diode goes into breakdown region, and the current increases dramatically and loses control.
2.3 Analysis of Diode Circuits
Consider a simple diode circuit
Assume the diode is “ON”
Using Kirchhoff’s Loop Rule:
I
How to do it?
(1) Graphical Analysis
eq. 2 or )1( / −= kTV sD
DeI )1ln( s
D D I
tions to solve the two unknown quantities ID and VD.
n: (1) graphical analysis (2) iterative analysis.
-load line Eq. 2 )1( / −= kTV sD
DeII
Iteration 1: initial guess:
mA 3.41 2 =
We can approximate the I-V curves of a p-n dio
relationship; VD0: cut-in voltage, rD forward di
Approximation: iD = 0 f
(4) Constant-Voltage-Drop Model
As the diode is forward-conducting, vD = VD0 =
ID1
ID2
VD1
ate)
ode resistance
0.7 V
2.4 Small-Signal Model and its Application
For some applications, a diode is biased to operate at a point on the forward i-v characteristic and a
small-ac signal is superimposed on the dc quantities. We can use the small-signal model to do ac
circuit analysis.
If a dc voltage VD is applied to the diode and a time-varying signal vd(t) is superimposed on
the dc voltage. Then, the dc current ID induced by the dc voltage VD is TD nVV SD eII /=
The total instantaneous diode voltage is given by vD(t) = VD + vd(t) , and the corresponding
current iD(t) is given by TD nVv SD eIti /)( =
24
nVvV SD eIeIti //()( == +
d DD nV
+≅ 1)( , where id is the time-varying current signal related to
the signal vd(t) by d T
D d v
nV Ii = and
nV i vr == is the diode small-signal resistance.
The slope rd is equal to the slope of the i-v curve at the operating point Q, therefore, the total
current iD could be approximated by )(1 DoD
d D Vv
r i −= , then the equivalent circuit model for a
diode for small changes around a bias point Q is given by
The Diode High-Frequency Model
If the diode is operated in high-frequency regime, then, the capacitance effect has to be taken into
consideration. Cj: depletion-layer capacitance and Cd: depletion capacitance.
25
2.5 Operation in the Reverse Breakdown Region-Zener Diode
The diode operating in the breakdown region can be used in the design of voltage regulators. Such
diodes are called zener diodes. A zener diode has a 6.8 V voltage drop at a specified test current of
10 mA. We can approximate the I-Vcharacteristic of the zener diode by VZ = VZ0 + rzIz when VZ >
VZ0, where rz is the dynamic resistance of the zener.
Example:
I
Question (
Solution:
an have the Vo =
b): Find the chang
Note: small varia
uit with the parameters: VZ = 6.8 V at IZ = 5 mA
upply voltage V+ is nominally 10 V but can va
o load and with V+ at its nominal value.
t the value of VZ0 of the zener diode model.
o VZ0 = 6.7 V. According to the equivalent circ
VZ0 + IZrz= VZ0 + z
0 rz= 6.83 V
e in VO resulting from the ±1 V change in V+.
0 rz 5.38±= +
, rz = 20 , and
ry by ±1 V.
uit,
n)
26
Question (C): Find VO when a load resistance RL = 0.5 kis connected .
Solution: when RL = 0.5 k, assume zener diode is “on” ⇒Vo~6.8 V, then the current flows through RL, IL = 6.8/0.5=13.6 mA. (impossible) since I=(V+-Vo)/R=6.4 mA < IL. Therefore, the assumption is not correct, zener diode must be cut off.
Then Vo is determined by R and RL. 5= +
= +
Design of the Zener Shunt Regulator
The function of a regulator is to provide an output voltage VO that is as const
of the ripple in Vs and the variations in the load current IL. Two parameters us
well the regulator is performing its function: the line regulation and the load
Line regulation S
)(0 R rI
Z
2.6 Rectifier Circuits
Rectification is a process of converting an alternating (ac) voltage into o
one polarity. (such as the power supply is fed from the 120 V (rms) 60 Hz ac
dc voltage Vo to the load). Rectification is classified as “half-wave” or “full w
ant as possible in spite
ed to measure how
ave” rectifications.
Half-Wave Rectifier
For vs < VD0, the diode is nonconducting ⇒ iD = 0, vo = 0.
For vs > VD0, the diode is “on” ⇒ vs = VD0+iD (rD + R) and vo =i
If a capacitor is added in parallel with the resistor to form a sim
transform the half-wave sinusoidal output into a dc voltage. Since th
portion of the sinusoidal signal, it’s also called a “filter capacitor”.
DR.
e capacitor “filters” out a large
28
For 0 < t < T/4, and |vs| > VD0,
⇒ the diode is “on” ⇒ RC circuit is charging until vo = vs – VD0
For T/4 < t > T/2, vs is decreasing
⇒ vo is decreasing (C is discharging through R with the time constant: RC )
(Q = Qoe-t/RC ⇒ vo(t) = RCto e C Q /− , Qo = C(Vp-VD0); i.e., vo(t)= RCt
Dp eVV / 0 )( −−
⇒ diode is off gradually until vs > vo again.
If the time constant RC >> T, then the discharge time t’~ T, the ripple voltage Vr
Vr ≡ Vp - VD0 - vo(T) = fRC
VV RC TVVeVV Dp
=⋅−≅−⋅− −
So we can determine the capacitor value required for a particular ripple voltage.
*We can determine the conducting time t of diode by (if t << T) by
( ) [ ]2 2 1
)( 21
)( 2
ω ω
*We can also determine the average diode current during conduction, iDav, by the charge supplied
to the capacitor through the diode is Qsupply = iCavt,
the charge lost by the capacitor during the discharge time is Qlost = CVr
at equilibrium, Qsupply = Qlost r
ppr Cav V

+


≅⇒
2 1 π
*the peak value of the diode current, iDmax, could be determined by iDmax = iCmax + iRav,
R V
pp D i
Full Wave Rectifier
Consider a full wave rectifier consists of a center-tapped transformer () with two diodes
and a resistor.
If vs > VD0, D1 is “ON” and D2 is “OFF”, ⇒ vo = vs –VD0
If vs < VD0, D1 is “OFF” and D2 is “ON”, ⇒ vo = -vs –VD0
Bridge Rectifier (Full wave rectifier)
If vs > VD0, D1, D2 are “ON” and D3, D4 are “OFF”, ⇒ V3 – V2 = VD0
V2 – V0 = vo
V0 – V4 = VD0 vs ≡ V3 – V4 = 2 VD0+ vo ⇒ vo = vs - 2 VD0
If vs < VD0, D1, D2 are “OFF” and D3, D4 are “ON” ⇒ -vs = 2 VD0+ vo, vo = vs - 2 VD0
30
fCR V
2.7 Limiter (Clipper) and Clamper
A clipper circuit is used to eliminate portions of a signal that are above or below a specified level.
Limiters find applications in a variety of signal-processing systems, such as in limiting the voltage
between the two input terminals of an op amplifier to a value lower than the breakdown voltage of
the transistors that make up the input stage of the op circuit. The general transfer characteristic for
a limiter circuit is shown o
as vI > L+/K vO = L+
as L-/K < vI < L+/K vO = K vI
as vI < L-/K vO = L-
Diodes can be combined with resistors to
Consider the following circuits, based on
(a) as vI < 0.7 V, D is “OFF”, open c
as vI ≥ 0.7 V, D is “ON”, then v
(b) as vI < -0.7 V, D is “ON, then vo
as vI ≥- 0.7 V, D is “OFF”, ope
i
the constant-voltage model wit
i
v
v
31
v
(c) as vI ≥ 0.7 V, D1 “ON”, D2 “OFF”, vo = vD1 = 0.7V as -0.7 V < vI < 0.7 V, D1, D2 “OFF”, ⇒ vo = vI
as vI < -0.7 V, D1 “OFF”, D2 “ON”, vo = -vD2 = -0.7V
(d) as vI < 5.7 V, D is “OFF”, open ckt ⇒ vo = vI
as vI ≥ 5.7 V, D is “ON”, then vo = vD + 5 = 5.7V (d) as vI >0.7+VZ2, Z1 in forward and Z2 in breakdown,
⇒ vo = 0.7+VZ2
as –(VZ1+0.7) < vI < VZ2+0.7, Z1, Z2 OFF, ⇒ vo = vI as vI <–(VZ1+0.7), Z1 in breakdown and Z2 in forward, ⇒ vo = –(VZ1+0.7)
A clamper circuit is used to shift the entire signal by a dc le
According to the KVL: vI + vC = vo. If vI = -6 V, D is “ON”, the capacitor is charging and vc
If vI = -6 V→+4 V, D is reverse-biased. ⇒ vo = vI + vc
Voltage doubler: a clamp formed by C1 and D1, and a peak r Assume D1 and D2 are ideal diodes with VD0 = 0 V. (i) As vI increases from zero to +Vp, D1 is “ON”, D2 is (ii) As vI decreases from Vp to -Vp, D1 OFF, D2 “ON”, time is very long), the voltage across the C1 is still +Vp
(iii) as vI increases from -Vp to +Vp, D1 is forward bias
vel. Consider the circuit:
=+6V, vo = 0. =+10 V, (vo shifts from vI by +6V)
ectifier formed by D2 and C2.
“OFF”, ⇒vo = 0, C1 charges to +Vp, C1 discharges (assume the discharge , ⇒ vo = vD1 = -Vp –Vpsin ωt ed “ON”, ⇒vo = 0
32
2.8 SPICE MODEL and Simulation
The use of computer aids to simulate the operation of electronic circuits is an essential step in the circuit design process. Among the various circuit-simulation program available, SPICE (Simulation Program with Integrated Circuit Emphasis) is by far the most extensively used, which was developed at the UC Berkeley. SPICE can analysze the operation of an electronic circuit containing diodes, transistors, resistors, capacitors, etc. Using user-specified device-model parameters, SPICE can perform a dc analysis to determine the dc bias or operating point of each device, can use these to compute the small-signal model parameters of the devices, and use these in turn to compute voltage gain, frequency response, etc. A nonlinear transient response of a circuit, e.g., a logic-gate circuit, can also be performed. In order for SPICE to perform the simulation of a given circuit, the user must provide it the following: (a) Circuit description: a complete description of the circuit to be analyzed; its elements and the
dc- and signal-sources present, and how they are connected together. (b) Analysis requests: the types of analysis, e.g., dc, small-signal, transient, etc., (c) Output requests: the type of output required, e.g., a table of dc bias currents and voltages, a
plot of the VTC of a logic gate, etc.
Circuit description:
Element statement: containing the element name, the circuit nodes to which it is connected, and the electrical parameter value(s).
SYNTAX of ELEMENT STATEMENTS
Component Name Nodes Value Resistor Rxxxxx N+ N- value Capacitor Cxxxxx N+ N- value Inductor Lxxxxx N+ N- value Voltage source Vxxxxx N+ N- Qualifier (dc or transient) Current Source Ixxxxxx N+ N- Qualifier (dc or transient) Voltage controlled current source
Gxxxxx N+ N- NC+ NC- value
Voltage controlled voltage source
Current controlled current source
Current controlled voltage source
33
Example:
R1 4 5 6.8K (resistor “R1” = 6.8 K is connected between node 4 and 5) C1 3 4 1.0U IC=5 (a 1.0 µF capacitor connected between node 3 and 4,
and having an initial dc voltage of 5 V) EOUT 3 0 2 1 100K (a voltage-controlled voltage source whose output
R1 C1
terminal is at node 3 and 0 (ground), whose input terminals are at nodes 1 and 2, and whose control ratio is 105 V/V)
Element Statements for Semiconductor Devices
Device Name Nodes and Models Diode Dxxxxx N+ N- Name Area BJT Qxxxx NC NB NE NS Name Area MOSFET Mxxxx ND NG NS NB Name L W
Syntax of Model Statements
Device Model Statement Diode .Model Name D(IS= … n= … ,etc) BJT .Model Name NPN (or PNP)(IS= … βF= …, etc) MOSFET .Model Name NMOS (or PMOS) (kP = ….Vt0= …, etc)
Analysis Requests
Main-Analysis Commands
Analysis Requests SPICE Command Operating-point .OP DC sweep .DC source_name start_value stop_-value step_value AC frequency response
.AC DEC points_per_decade freq_start freq_stop
.AC OCT points_per_octave freq_start freq_stop
.AC LIN totsl points freq_start freq_stop Transient response .TRAN time_step time_stop
SPICE Output Requests
Output Requests SPICE Command Print data points .PRINT DC output_variables
.PRINT AC output_variables
.PRINT TRAN output_variables Plot data points .PLOT DC output_variables [(lower limit, upper limit)]
.PLOT AC output_variables [(lower limit, upper limit)]
.PLOT TRAN output_variables [(lower limit, upper limit)]
2.9 The DIODEL MODEL
Exercise 3.33 *** A Voltage Doubler Circuit” ** Circuit Description ** Vi 1 0 sin (0 10V 1kHz) C1 1 2 1u C2 3 0 1u D1 2 0 D1N4148 D2 3 2 D1N4148 *diode model statement .model D1N4148 D (Is= 0.1pA Rs=16 CJO= 2p Tt= ** Analysis Requests ** .Tran 100u 10m 0m 100u
12n Bv=100 Ibv=0.1p)
35
2.10 Homework 3.17, 3.26, 3.65, 3.72, 3.111
Chap. 3 Bipolar Junction Transistors (BJTs)
Motivation: Diodes are useful in electronic switching and waveshaping circuits. However, they are
not capable of amplifying currents or voltages. “Transistor”, a three-terminal device, can amplify
current and voltage in conjunction with other circuit elements.
Two major types of transistors are BJT: switch, digital circuit, amplifying device
FET: ?
36
3.1 Basic Bipolar Junction Transistor
Two pn junctions in the BJT device, four possible bias combinations may be applied:
VBC
2. Inverse-active mode: E/B reverse, B/C forward ⇒ digital circuit
3. Saturation mode: E/B and B/C are forward ⇒ transistor in saturation
4. Cut-off mode: E/B and B/C are reverse-biased ⇒ transistor “OFF”
3.2 Operation of the npn BJT in the Forward-Active Mode
37
Since E/B junction is forward biased, electrons from the emitter are injected across the E/B
junction into the base, creating an excess minority carrier in base. Since the B/C junction is reverse
biased, the electron concentration at the edge of the B/C junction is approximately zero. (electrons
are attracted across the B/C junction due to the reverse E-field)
Ideally, all the electrons injected from the emitter will be swept into the collector without
recombining with holes in base⇒electron concentration is a linear function of distance across the
base. However, carrier recombination “does” occur in the base, the e- conc. will deviate from the
linear curve. To minimize recombination effects, the width of the neutral base must be smaller than
the minority carrier diffusion length.
Collector Current
The # of electrons reaching the collector per time ∝ #. of e- injected into the base, which is a
function the B/E voltage and is indep. of B/C voltage. ∴IC ∝ dn/dt ∝ eVBE/KT
⇒ collector current is controlled by the B/E voltage; kTV SC
BEeII /=
Base Current
B/E is forward/biased, holes from the base flow across B/E junction into the emitter.
The base current iB1 ∝ the # of holes flowing into the emitter ∝ eV BE
/kT
38
A few electrons recombine with majority carrier hole in the base,. This “recombination current iB2
∝ #. of e- injected from the emitter ∝ eV BE
/kT
/kT, (Recall ) kTV SC
(100~200): Common-Emitter Current Gain,
βF is affected by two factors: base width (W) and the relative dopings of the base region and the emitter region (nE / nB)
1. Usually nE ~ 1019, nB ~ 1017, nC ~ 1015, ∴ the e- conc. in emitter >> the h+ conc. in base
⇒ no. of e- injected into base >> no. of h+ injected into the emitter. ∴iE >> iB1
2. if the base width is small ⇒ iB2 ↓↓⇒βF ↑↑
Emitter Current
Since the current enters a transistor should leave it, ⇒ iE = iB + iC,
Recall: iC =βF iB, ⇒ iE = iB + iC = (βF +1) iB = αF iC,
αF: common base current gain= 1+F
F
1− =
F
Arrows: 1. specify the e 2. indicate the
of the emitte
In Forward-Bias Condition:
40
Early Effec
junction and
CE
t: at a given value of vBE, increasing vCE increases the reverse-bias voltage on the C/B
thus increases the width of the depletion region in the base. This in turn results in a
he effective base width. Recalling Is ∝ (1/WB),
Is ↑ ⇒ ic ↑
slope of the iC – vCE lines indicates that the output resistance ro is finite.
C
A
vCE
of the BJT circuits at DC
1 Consider the following circuit with βF =100 and a vBE =0.7V. Find IE, IB, and IC.
41
(1) QVBE = 0.7 V ⇒ VE = -0.7 V (QVB= 0 V) ⇒ mA R
V I
−− =
(2) assume this BJT in forward-active mode, QIE = IC + IB, IC = βFIB
(3) ⇒ AmA
I I
mA, 0.91II
== +
=
= +
×= +
=
(4) Q IC = 0.91 mA ⇒ VC = 10-ICRC = 5.44 V ⇒ VCE = VC - VE = 6.14 V > VCE(Sat) = 0.3 V (Right Assumption)
Example 4.2 Example 4.4
(1) QV can
(2) Fo rev
(3) ⇒
Assume in forward-active mode, ∴VBE = 0.7 V, ⇒ to proof VCE > VCE(Sat)
(1) QVBE = 0.7 V ⇒ VE = VB –0.7=5.3V
⇒ mA K
F EC
848.2 45.27.410
1100 10093.0
1β β
Not in forward-active mode! In fact, this BJT is in saturation!
Example 4
.7
B = 0 V ⇒ B/E junction not conduct! ⇒ IE = 0 A
r B/C junction, erse-biased ⇒ IC = 0 A
IB = 0 A ∴BJT is cut-off!
Assume in forward-active mode, ∴VBE = 0.7 V, ⇒ to proof VCE > VCE(Sat)
(6) QVE = 0 V ⇒ VB = VBE =0.7V
⇒ A K
=== −+
Assume in forward-active mode, ∴VBE = 0.7 V, ⇒ to proof VCE > VCE(Sat)
(3) VBB = IB ⋅ RBB + VBE +IE ⋅ RE (4) ⇒ 5 = IB⋅ 33.3 + 0.7 +101 IB⋅ 3
( ) Am ImAII A, I CBFEB 28.1,29.1178.12 ==+== βµ (5) V V RIRIV EECCCE 3.067.415 >=⋅−⋅−=⇒
Right assumption!
Example 4.8
(1) Biasing circuit is the same as in Example 4.7 ⇒ IB1 = 12.78 µA ~ 0.012 mA.
VV , VV
R V
=+⇒ −
=+⇒
(2) QVB1 =4.57V >>0.7V, assume BJT1 is in forward-active mode ⇒ to prove VCE > VCE(sat) ⇒ IE1 = (βF +1)IB1 = 1.29 mA, VE1 = IE1⋅ RE1 = 3.87 V ⇒ IC1 = βF IB1 = 1.28 mA, ⇒ VC1 = ??? determined by Q2 and RC1
(3) For Q2, VC1 = VB2, VE2 = VB2+0.7 (assume Q2 is ON & in forward-active mode)
2 )7.0(1515 1
E E
V R
V I
(4) For node C1, B2, KCL: IRC1 + IB2 = IC1 mA VV CC 28.1
2 )7.0(15
+− +
− ⇒
⇒ VC1 = 8.74 V, IRC1 = 1.252 mA, IB2 = 0.0275 mA, IE2 = 2.78 mA, IC2 = 2.75 mA ⇒ VE2 = 9.44 V, VC2 = 7.43 V, VB2 = 8.74 V, ⇒ VEC2 = 2.01 > 0.3 = VEC(sat)
⇒ VCE1 = 8.74-3.87 = 4.87 > 0.3 = VCE(sat)
∴Q1 & Q2 in forward-active mode, right assumption!
3.6 Transistor as an Amplifier
To operate as an amplifier a transistor must be biased in the active region. That is establishing a
constant dc current in the emitter (or the collector). This bias current should be predictable and
insensitive to variations in temperature, value of β, and so on.
Load Line and Modes of Operation
A graphical analysis is illustrative to view the operation of a simple transistor amplifier circuit.
43
Consider the circuit of the following figure, a graphical analysis could be performed as follows:
1. Determination of the dc bias current of the transistor: that is to determine the dc base current IB (or VBE).
2. Sketch the load line vCE = VCC – iCRC ⇒the intercept point of the load line and the iC-vCE curve is the Q point.
If a s vBE =
sponding, the col
the collector cur
conductance gm is
pplied to the base, the total instantaneous base-emitter voltage vBE becomes
lector current becomes kTv C
kTvV S
kTv SC
bebeBEBE eIeIeIi //)(/ === +
cC be
kT vII
kT v
+=+=+ ) ----small-signal approximation
rent is composed of the dc bias value IC and a signal component ic. The
defined by kT I
The Base Current and the input Resistance at the Base
Recall bB be
ββ
The small-signal input resistance between base and emitter, looking into the base is defined by
Bm
F
b
be
The Emitter current and the input resistance at the Emitter
The total emitter current iE can be determined by eE be
F
Therefore, the small-signal input resistance between base and emitter, looking into the emitter
is defined by ( ) eF Em
F
e
Voltage Gain
A small signal vbe applied, ⇒ small current signals ib, ic, ie⇒the total collector voltage vC will
be cCCcCCcCCCCCCCC vVRiVRiIVRiVv −=−=−−=−= )(
Therefore, the voltage gain of the amplifier is Cm be
C Rg v v
3.7 Small-Signal Equivalent Circuit Models
The analysis in the previous section indicates that every current and voltage in the amplifier circuit
is composed of two components: a dc component and a signal component. We can use
superposition principle to do the dc and ac analysis separately, and then sum up.
The right figure shows the expression for the
current increments ib, ic,and ie obtained when
a small signal vbe is applied.
= IC/VT = β /gm
A equivalent circuit hybrid-π model for the BJT is shown.
This model represents the BJT as a voltage-controlled
current source, gmvbe, and includes the input resistance,
looking into the base rπ. This model can be used to carry
out small-signal analysis of all transistor circuits.
This model yields the correct expression ib, ic and ie.
T model
This model represents the BJT as a voltage-controlled current source and includes the input
resistance, looking into the emitter, re. This model yields the correct expression ic and ie.
46
Application of the small-signal equivalent circuits
The availability of the small-signal BJT circuit models makes the analysis of transistor amplifier
circuits a systematic process.
The process consists of the following:
1. Determine the dc Q point and in particular the dc collector current IC.
2. Calculate the values of the small-signal model parameters:
gm = IC/kT, rπ=β /gm, and re = gm/(β+1)
3. Eliminate the dc sources by replacing each dc voltage source with a short circuit and
each dc current source with an open circuit.
4. Replace the BJT with one of its small-signal equivalent circuit models.
5. Analyze the resulting circuit to determine the required quantities.
Example: 4.9 Determine the voltage gain the BJT amplifier.
Solution: Assume β = 100. VBE(on) = 0.7 V.
1. The dc Q point is determined by setting the small-signal
source=0 and assume in the forward-active mode:
023.0 100
VVI mA, IC = βIB = 2.3 mA
VC = VCC – ICRC = +3.1 V ⇒ VCB >0 and VCE>VCE(sat). (right assumption)
VCC = +10V
= +
β π π
3. Draw the small-signal equivalent circuit by the hybrid-π model.
4. , Cbemo Rvgv −= π
47
There is a constraint on the maximum amplitude that vi is allowed to have i.e., to ensure the BJT still operates in forward-active mode. Consider that if the peak amplitude of vbe,
= 10 mV. ⇒ the peak amplitude of the input signal beV 91.0ˆˆ = +
= π
π
bei V
⇒the peak amplitude of the collector voltage vc: V 77.204.391.0ˆˆ =×== ivC VAV
⇒the collector voltage reaches a minimum of 3.1-2.77=0.33 V<the base voltage~0.71 V
Thus, the BJT is not in the forward-active mode with vi having a peak value of 0.91 V.
We can easily determine the maximum value of the peak of the input signal such that the BJT
remains in forward-active mode by finding the value of that corresponds to the minimum
value of the collector voltage being equal to the base voltage, which is ~0.7V.
iV
Thus the maximum =3.1-0.7=2.4 V ⇒ the maximum cV 79.0 ˆˆ ==
v
Modified hybrid-π model to account for the Early Effect.
The Early effect causes the collector current to depend on vBE and vCE. Therefore, we have to
include the finite output resistance ro in the hybrid-π model. Then, the output voltage will become
vo = -gmvbe(RC//ro)~ -gmvbeRC if ro >> RC. In general, the ro in the M, which is much larger than
RC ~ k.
Effects of Bias-Point on Allowable Signal Swing
The location of the dc bias point in the iC-vCE curve plane significantly affects the maximum
allowable signal swing at the collector.
Consider the QA point: this corresponds to a low value of RC and results in the vCE very close to
VCC. Thus, the positive swing of vCE will be severely limited. On the other hand, the bias point QB
corresponds to a large value of RC and results in the vCE too low. Thus, the negative swing of vCE
will be severely limited by the proximity to the saturation region. We have to bias the BJT
carefully to have the maximum input swing as an amplifier.
49
The voltage d
values of R
in a loweri
in this par
for some r
ivider network is the most commonly used for biasing a transistor amplifier is only a
supply is available.
= FBE
VVI β
and RE >> RB/(βF+1), then IE is insensitive to temperature, VBE, and βF.
here is a limit on how large VBB can be:
IE↑ ⇒ Ic↑ ⇒ VCB = VCC – ICRC – VB ~ VCC – ICRC – VBB ↓
⇒ VCE = VCC – ICRC – VE ~ VCC – ICRC – VBB +VBE ↓
e want VCB and VCE to be large to provide a large signal swing before the BJT cutoff
tion. Therefore, there is a compromise between high VBB and VCB/ VCE. As a rule of
ne designs for VBB ≈ CCV1 3 , VCB (or VCE) ≈ CCV1
3 , and ICRC ≈ CCV1 3
insensitive to βF, a smaller RB is needed. A smaller RB is achieved by using low
1 and R2, which means that a higher current drain from the power supply and results
ng of the input resistance of the amplifier (undesired), which is the trade-off involved
t of the design problem. Smaller R1 and R2 also mean that the base voltage is
solely by the voltage divider and is indep. of βF. Typically, one selects R1 and R2
eir current is about 0.1IE ~ IE.
emitter provides a negative feedback action to stabilize the bias current. Consider that
eason IE↑⇒ VE = IERE ↑, since VB ~ constant⇒ VBE ↓⇒ IE ↓
50
Using Two power Supplies
A simpler bias arrangement is possible if two power supplies are available. In this case,
( )1/ ++ −
= FBE
EI β
VVI β
To obtain an IE insensitive to βF, we select RB/(βF+1)<<RC. However, the value of RB determines
the allowable signal swing at the collector since VCB = IBRB =IERB/(βF+1)
Biasing using a Current Source
51
The emitter current is independent of the values of βF and RB. Thus RB can be made large to
increase the input resistance at the base without adversely affecting bias stability.
Consider a current source circuit as shown: assume Q1, Q2 are matched.
⇒ I R
stant-current source is assumed to have a high output resistance.
pass capacitor connecting the emitter and ground is assumed to be sufficiently large
its resistance, 1/jωCE, is small at all signal frequencies of interest. In effect, CE
rcuits the emitter to ground as far as signals are concerned.
ut signal vs is fed into the base, the output signal vo is taken at the collector, and the
is common-grounded. We wish to analyze the CE amplifier to determine its input
ce Ri, voltage gain Av, current gain Ai s, and the output resistance Ro.
ce: Ri ≡ vi/ ii = vπ/ ib =rπ
vo = -gmvπ(RC//ro); vπ =vs ⇒ + SRr r
π
if RS << rπ, ( ) ( )oCm oC
v rRg r
rRA //// −=−=⇒
π
β ;
52
for discrete circuits, RC << ro, Cmv RgA −=⇒ for IC amplifiers, maximum possible gain is interested, so RC is set ∞
kT V
I V
Current gain: ⇒== +
output resistance oc vx
since vπ = 0 due to vs is set to 0.
Common-Emitter amplifier with RE in the emitter Fig. 4.44 (a)
Ri
Including s resistance between emitter and ground can lead to significant changes in the amplifier characteristics. 1. Input resistance Ri ↑ by a factor of (1+gmRe) 2. Av ↓, but is less sensitive to β. 3. large voltage swing at input signal, because only small fraction of input signals at the base
appears between base and emitter. (by a factor of 1+gmRe)
Input resistance: Ri ≡ ( ) )(1)( ee
b
eee
b
e
b
e
e
ee
ei
C
R Rβ− , gain is lower but less sensitive to β.
Input Voltage Swing: emee
+ ≅
+ =
1 1π , thus for the same vπ, the input signal can be
greater than that for the CE amplifier by the factor (1+gmRe) without incurring nonlinear distortion. Common-Base Amplifier
RO
Ri
e r i v
= (very small ~25 at a bias current of 1 mA)
Voltage Gain: ( )es
α ,
indep. of β, but depends critically on Rs. if Rs>>re, Av ≈ RC/Rs; (more common) if RC<<re, Av ≈ gmRC; (very rare since re is very small)
Current Gain: αα =
Output resistance: Co RR =
Comment: Since the input resistance is very small, the CB circuit alone is not attractive as a voltage amplifier. It is more suitable as a unity-gain current amplifier or current buffer. The most significant advantage of the CB circuit is its excellent high-frequency response.
Common-Collector Amplifier or Emitter Follower
54
Applications in the design of amplifiers, both small-signal and large-signal and in digital circuits. The input signal is applied to the base and the output is taken from the emitter.
S
In
++= )+ =≡ β
the case ( ) LioLe RRrRr 1+≅⇒<<<< β The CC amplifier exhibits a relatively large input resistance.
oltage gain:
ary:
55
1. high input resistance 2. low output resistance: useful as the last stage or output stage in a multistage amplifier. 3. voltage gain→1 4. large current gain→β+1 Comment: It is suited for applications in which a high-resistance source is to be connected to a low-resistance load, namely as a voltage buffer amplifier. 3.10 BJT as a Switch – Cutoff and Saturation Cutoff Region: If vI < 0.5 V, the BJT is in the cutoff mode, iB = iE = iC = 0, vC = VCC
Active Region
To turn the BJT on, vBE should be about 0.7 V and vI >0.7 V.
B
I B R
vi 7.0− = , iC = βiB, vC = VCC - iCRC and then check whether vCB ≥ 0.
Saturation Region
Saturation occurs when we attempt to force a current in the collector higher than the collector circuit can support while maintaining active-mode operation. In saturation, the base voltage is higher than the collector voltage by about 0.4 to 0.6 V, that is vCE ≈ 0.1 ~ 0.3 V ( set VCEsat ≈ 0.2 V).
C
EOSB II ≥)( to ensure the BJT in saturation. Normally, IB
is higher than IB(EOS) by a factor of 2 to 10. So in saturation, the ratio of IC/IB is called forced
56
npn
Thus the BJT is operated at a forced β of βforced = IC/IB = 0.96/0.64 = 1.5 < βF
57
Ebers-Moll Model: a general large-signal model for the BJT The Transistor Terminal Curre
Basic BJT Logic Inverter
If the input voltage vI is “ The BJT is conducting and sa appropriate choice of RB and R ⇒ vO = VCEsat =0.2 V “Low”
If the input voltage vI is “ The BJT is cutoff, iC = 0, and Comment: The choice of cut circuit is motivated by
1. low power dissipation: transistor is very small (VC
2. The output voltag forward-active mode, vO =
nts
high”, say vI = VCC,
vO
vO = VCC “high”
off and saturation as the two modes of operation of the BJT logic
the currents in cutoff region are all zero and the voltage across the Esat) in saturation
e-levels (VCC and VCEsat) are well defined. If operating in the VCC – iCRC = VCC - βiBRC, highly dependent on β.
58
Voltage Transfer Characteristics If RB = 10 k, RC = 1 k, β=50, and VCC = 5 V
1. At vI = VOL =VCEsat =0.2 V, ⇒vO = VOH =VCC =5 V 2. vI = VIL, BJT is “on” thus, VIL ≈ 0.7 V 3. For VIL < vI < VIH, BJT in forward-active mode,
The small-signal gain is 5−≈ +
−=≡ π
o v V/V
4. At vI = VIH, the BJT enters the saturation region. VIH is the value of vI that results in
( ) β
− ==
IB(EOS) = 0.096 mA, ⇒VIH = IB(EOS)RB +VBE =1.66 V 5. For vI = VOH = 5V, BJT in saturation with vO =VCEsat = 0.2 V 6. The noise margin:
NMH=VOH – VIH = 3.34 V NML = VIL – VOL = 0.5 V
Complete Static Characteristics and Second-Order Effec
Common-Base Characteristics
Cutoff Conside (That is
Frequenc r the CE , no load i
y short-circuit current gain, hfe, in which the collector is shorted to the emitter. s connected).
60
At node C, the short-circuit collector current Icis given by Ic = (gm-sCµ)Vπ
While, the relation ship between Vπ and Ib is given by µππ
µπππ sCsCr I
CCrIV b b ++
)////(
Therefore, the CE short-circuit current gain, hfe, can be obtained: ; )(1 µππ
µ
− =≡
if gm >> ωCµ, we can neglect the sCµ term and then
πµππµπ
The 3dB frequency ( ) ππµ βω
rCC + =
1 ;
Recall, C C
m I kT I
g ∝= , but only part of Cπ is directly proportional to IC.
So at low IC current, fT ∝ gm ∝ IC. At high IC current, fT drops due to the decrease of β0 at high currents. At mid IC current, fT is almost constant since Cπ is dominated by the diffusion part. Typically, fT is in the range of 100 MHz to hundreds of GHz. And the value of fT can be used to determine Cπ + Cµ
61
62
Low Frequency Response
Figure 5.73 Analysis of the low-frequency response of the CE amplifier: (a) amplifier circuit with dc sources removed; (b) the effect of CC1 is determined with CE and CC2 assumed to be acting as perfect short circuits;
64
Figure 5.73 (Continued) (c) the effect of CE is determined with CC1 and CC2 assumed to be acting as perfect short circuits; (d) the effect of CC2 is determined with CC1 and CE assumed to be acting as perfect short circuits; SPICE BJT MODEL
65
66
Chap 5. Field-Effect Transistor FET: the current is controlled by an electric field applied perpendicular to the semiconductor surface and to the direction of current. Metal-Oxide-Semiconductor (MOSFET) Metal-Semiconductor FET (MESFET) 5.1 Structure
* Two-Terminal MOS structure with S/D grounded VG < 0 (1) apply a negative bias to the gate with respect to the substrate, ⇒ induce an E-field with direction ↑.
Negative charges will exist on top of the gate plate. In Si substrate, the majority HOLEs will move toward SiO2/Si interface due to E-field appliction.
⇒Holes accumulate near the SiO2/Si interface, “Accumulation” (2) Apply a positive bias to the gate wrs the Si substrate. ⇒ induce an E-field with direction ↓.
Positive charges will exist on top of the metal plate. In Si substrate, the majority HOLEs will repel from SiO2/Si
VG > 0
interface and leave negatively charged ions. (depletion) ⇒As VGS ↑, E-field ↑, minority Electrons are attracted to SiO2/Si interface, “Inversion” Threshold Voltage (VTH): defined as the applied gate voltage needed to create an inversio in which the charge density = the conc. of majority carriers in Si substrate. In other words,
E
E
E
67
the gate voltage required to “turn on” the transistor. For nMOS, if VTH >0, enhancement mode; if VTH <0, depletion mode For pMOS, if VTH>0, depletion mode; if VTH >0, enhancement mode,
* Transistor Structure For VGS > 0 inversion layer is formed underneath the SiO2/Si interface ⇒ n- channel region is formed and Connects the n+ source and n+ drain. . If VDS > 0, ⇒ a current can be generated between S and D. Since the carriers moving in the channel are electrons, the MOSFET is called nMOS. Similary, for PMOS, the carriers moving in the channel are “Holes” ⇒ n-Si substrate, P+ Source and Drain. (a) if VDS << VGS -VTH,
⇒ the channel layer is almost constant ⇒ ID ∝ VDS
(b) as VDS ↑, the voltage drop across the oxide
near the drain ↓ ⇒ the inversion charge density near the drain ↓ ⇒ the incremental conductance at the drain ↓ ⇒ the slope of ID versus VDS ↓ (c) As VDS ↑ to VDS(sat) = VGS -VTH
⇒the inversion charge density near the drain= 0 ⇒ the conductance at the drain =0 ⇒ the slope of ID versus VDS =0 (saturation)
(d) if VDS > VDS(sat), the point of zero inversion charg moves toward Source ⇒electrons enter the channel at the source, travel through the channel toward the drain, and then are injected into the depletion region, where they
e
68
are swept by the E-field to drain⇒” Saturation” I-V Characteristics
If VGS < VTH, “CUT OFF” IF VGS > VTH, “ON”,
For VDS < VDS(sat), “Nonsaturation”, ( )[ ]22 DSDSTHGSnD VVVVkI −−= where L CWk oxn
n 2 µ
For VDS > VDS(sat), “Saturation” [ ]2THGSnD VVkI −= independent of VDS
Note: the geometry, (W, L, or dox) is a variable in the design of MOSFETs *Ckt Symbols and Conventions nMOSFET:
enhancement mode: VTH >0, a channel can be formed when VGS > VTH>0 depletion mode: VTH <0, a channel exists even at VGS = 0, so a negative voltage must be
applied to th edepletion mode-nMOSFET to turn it off. Large sign
enhanced mode depletion mode
Body Effect
If Vsub-source = 0, VTH is a constant. If Vsub-source ≠ 0, VTH is dependent on Vsub-sourc by
[ ]FSBFTHoTH VVV φφγ 22 −++= For VSB = 0 V
Body effect parameter Related to the doping concentration of the substrate
√ iDSubthreshold Conduction
For an ideal MOSFET, ID = 0 when VGS < VTH. In reality, ID ≠ 0 as VGS < VTH, and it is called
“ subthreshold conduction”. ⇒ It is significant for IC since it will cause extra “Power” dissipation.
Breakdown
“Punchthrough” occurs when the drain voltage is large enough for the depletion region around the drain extend completely to the source terminal ⇒ ID increase rapidly (Breakdown) Table Summary of Important MOSFET equations
70
Common Source Circuit
Solution: (1)
V RR
"assumption Wrong n, saturatioin Not VVVRIVVV
mAVVkI
satDSDDDSSD
THSGpD
""" 7.1655.05
578.0
V RR
R VV
[ ]
( )
R VVI Recall ,VVkI
=⇒
=>=⇒ =−=⇒
− =−=⇒
• A source resistor RS is usually used to stabilize the Q-point of MOSFET against variation in
transistor parameters: (L, W, Cox, VTH).
Solution:
(1)
SDS
DDG
RIV
[ ] [ ] ( )
VVVVVVVV mAII
71
An enhancement load (VTH > 0 for nMOS and VTH < 0 for pMOS) If an enhancement load device is connected with a MOSFET driver, this circuit can be used as an amplifier or as an inverter. If an enhancement load is connected with G & D shorting
⇒VG = VD ⇒VGS = VDS ⇒ VDS > VGS – VTH = VDS(sat)
⇒ transistor must be in “saturation” if it is on.
Solution: (iii) VI = 5 V,
⇒ VGSD = 5 V, VDSD(sat) = VGSD –VTHD = 5-1 = 4V.
(iii) If MD is in saturation ⇒ VDSD> VDSD(sat) = 4V ⇒ Possibility is “LOW”
(ii) Assume in MD “Nonsaturation”, (ML is known in “Sat”) Q MD and ML are in series, ∴IDD = IDL.
⇒ IDD=knD[2(VGSD – VTHD
= VDSL =VDD – VO = 5- VO
(iii) ⇒ knD[2(VI – VTHD ) VO – VO
2] = IDL = knL(VDD – VTHL
⇒ 3 VO 2 – 24VO + 8 = 0
⇒ VO = 7.65 V (→←, Q VO must < 5 V) or 0.349 V ⇒ VO = 0.349 V = VDSD < 4 V (Right assumption) ⇒ ID = 133 µA
(2) if VI = 1.5 V, ⇒ VGSD
= 5 V > VTHD, MD is ON and VDSD(sat) = VGSD - VTHD = 0.5V
∴MD is very possible in “Saturation”, while ML is known in “Sat” (3) ⇒ IDD= IDL.
⇒ IDD=knD(VGSD - VTHD
)2 = knL(VGSL - VTHL
)2
⇒ VO = 3.64 V = VDSD > 0.5 V = VDSD(sat), “Right assumption” ⇒ ID = 12.5 µA
“1” VI = 5 V, ⇒ VO = 0.349 V “0” “0” VI = 1.5 V, ⇒ VO = 3.64 V “1”
• Depletion Load (VTH < 0 for nMOS and VTH > 0 for pMOS)
VGS = 0 > VTH, Q VTH < 0 ∴ transistor ML is always “ON”
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⇒ VGSD = 5 V, VDSD(sat) = VGSD –VTHD = 5-1 = 4V.
(i) Assume in MD “Nonsaturation” and ML is in “Sat” Q MD and ML are in series, ∴IDD = IDL. ⇒ 5 VO
2 - 40VO + 4 = 0 ⇒ VO = 7.9 V (→←, Q VO must < 5 V) or 0.1 V ⇒ VO = 0.1 V = VDSD < 4 V = VDSD(sat) (Right
assumption) ⇒ ID = ID = 40 µA
D L
• Constant-current source Biasing
Solution: (1) M2, M3, and M4 form the const-current source! (2) M4 :
VG4 = VD4, ∴ VDS4 = VGS4 > VGS4 – VTH4
⇒ M4 is in “Saturation” (3) M3 : in “Saturation” for the same reason (4) ID3 = ID4 = Iref
⇒ kn3 (VGS3 - VTH3)2 = kn4(VGS4 - VTH4)2 equation (A) (5) Q VGS3 +VGS4 = 0 – V- = 5V equation (B)
⇒ [ ] S
n
n
+−
=
(6) Q VGS3 = VGS2, assume M2 in “Saturation” ⇒ IQ= kn2(VGS3 - VTH2)2 =0.225 mA
(7) for M1 : ID1 = IQ (assume in Saturation) (7) ⇒ ID1 = 0.225 = kn1 (VGS1 - VTH1)2
⇒ VGS1 = 2.06, VDS2 = VS1 – VS2 = 2.94 > VDS2(sat)
(Right assumption)
• • Digital Logic Gate:
(1) NMOS Inverter
(8) If VI < VTH, ⇒ M1 is “OFF” ⇒ ID = 0, VO = VDD. (9) If VI > VTH, ⇒ M1 is “ON” ⇒ VO = VDD - ID RD
As VI ↑, ID ↑ ⇒ VO↓ (3)∴ VI “0” ⇒ VO “1”
VI “1” ⇒ VO “0” ⇒ “Inverter”
Power Dissipation Consider the power dissipation in a MOSFET inverter with VDD = 5 V, RD = 10 , VTH = 0.8 V,
kn =0.3 A/V2. If VI < VTH =0.8 V, ⇒ ID = 0, VO = VDD = 5V. ⇒ Power dissipated in the transistor is “zero”. If VI = VTH =0.8 V, assume M1 is in “Nonsaturation” ⇒ VO = VDD – knRD[2(VI – VTH)VO – VO
2] ⇒ 3 VO
2 –26.2 VO + 5 = 0 ⇒ VO = 0.195 or 8.54 (→←, Q VO must be less than VDD) ⇒ ID = (VDD - VO)/RD = 0.48 A
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∴the power dissipated in the MOSFET is PT = ID • VDS = 0.48 x 0.195 = 93.6 mW ∴the power delivered to RD is PRD = I2
D • RD = 2.34 mW Digital Logic Gate
Amplifer Consider an NMOS, To get a linear amplification (Vo/Vi : linear), the MSOFET should be biased in saturation mode.
vGS = VGSQ (dc component) + vi (ac component) ⇒ iD = kn(VGS – VTH)2 = kn(VGSQ + vi – VTH)2 = kn[(VGSQ – VTH) + vgs]2
⇒ iD = kn(VGSQ – VTH)2+ 2kn(VGSQ – VTH)vi + knvi 2
Generally, vi << 2(VGSQ – VTH) ∴vi 2 is much smaller and could be neglected
⇒ iD = kn(VGSQ – VTH)2+ 2kn(VGSQ – VTH)vi
IDQ ⇒ The small-signal drain curren
id =2kn(VGSQ – VTH)vgs ≡ gmvgs
V1 V2 VO
0V 0V “1” 5V 0V “0” 0V 5V “0” 5V 5V “0”
onductance gm :
)/(2)(2
Note: 1. With the Q point in the saturation region, the transistor operates as a constant current
source that is linearly controlled by vgs. 2. The gm of MOSFETs tends to be small compared to that of BJTs. However, the
advantages of MOSFETs are: (A) high input impedance (B) Small size (high packing density) (C) Low power consumption
AC equivalent circuit of Common-Source amplifier
If R1 and R2 are biased the MOSFET in saturation mode, and the signal frequency is large enough for CC acts as a short circuit, the ac equivalent circuit becomes:
Example:
⇒ Av = vo/vi = -gm (ro//RD) Ri ≡ vi/ii = R1//R2
Ro = vo/io |vi = 0 = ro //RD
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Source-Follower Amplifier (Output is taken from the source terminal) (1) vo = gmvgs (RS//ro),
vi = vgs + vo = vgs [1+gm(RS//ro)] ⇒ 1 )//(1
)//( <
+ ==
A
(2) Rin = R1//R2 (3) Ro = vo/io |vi = 0 ⇒ vg = 0, ∴vgs = -vS = -vo
(4) S moSm
)//()//( =
+ =≡⇒+=−=
Note: although the voltage gain Av of a source follower < 1, bu small compared to that of a common-source circuit. A small Ro is as an ideal voltage source a drive a load circuit without suffering lo similar to Emitter-follower Common-Gate configuration (Input: source, gate: grounded)
RG is used to prevent the buildup of static charge on the gate.
(1) vo = gmvgs (RD// RL), vgs = -vi , ⇒ )//( LDm i
o V RRg
=0
,1
or/
t its output resistance Ro is very desired when the circuit is to act ading effects.
76
77
Configuration Voltage gain Current gain Rin Ro
Common-Source AV > 1 ∞ Source-Follower AV ≤ 1 ∞ Low Common-Gate AV > 1 Ai ~ 1 Low (1/gm) CMOS Common-Source Amplifier
Small-Signal Equivalent Circuit:
CMOS Common-Gate Amplifier Source Follower
(1) Replacing Q2 with its output resistance ro2 (2) For Q1, the source is not grounded,
∴a current source gm1vbs1 is included, vbs1 = -vi
(1) (2)
( ) ( )21 1
11 2
11 1
//1 oo
o mbm
( )

+
+ =⇒
78
C
(1
MOS Inverter
(1) vo = gm1vgs1 RS vi = vgs1 + vo = vgs1 [1+gm RS ]
⇒ 1 1
⇒ 21 21
////1//1 oo
P P
(ii) kn = kp (that is, kn’(W/L)n = kp’(W/L)p)⇒ p
n
n
P
I
o
“triode” region, QP in “Saturation” region.
( ) ( )
( )
( )
( ) ( )
:follows as determined benow can margins noise The 23
Nonsat."" in is and Sat."" in is by determine can weSimilarly, 25get can we, ngSubstituti
2
2 1,
−−=−−⇒−==Q
81
Dynamic Operation To determine the propagation delay of the inverter. Assume a capacitor C (load) is connected between the output of the inverter and ground. Here C represents the sum of the internal capacitors of next stages QN and QP. Assume the cir time of the outp (1) C is charge (2) C is discha
cuit is symmetric (i.e., NMOS and PMOS are matched), ⇒ the rise time and fall ut waveform should be equal.
d through QP from VDD (vI = 0, QN is OFF)
rged through QN to ground when vI is high, QP is OFF.
( )



− +
−−

'
t : is the time required for C to discharge from V to V /2.
PHL DD DD
We know that in every cycle, ½CVDD
2 of energy is dissipated in QN and ½CVDD 2 dissipated in QP.
So if the inverter is witched at a frequency f ⇒ the dynamic power dissipated will be PD = f CVDD
2. A figure of merit of a particular circuit technology is the “delay-power” product DP = PD • tP
It is observed that tP↑, PD↓, DP ~ constant. MOSFET as an Analog Switch
+ vO
A CMOS Transm
As vC is low, the MOSFET is OFF, ⇒ Switch is “open” As vC is high, the MOSFET is ON, ⇒ Switch is “closed”
ission Gate
As the Gate is “Closed”
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