E-Cal Readout Boards
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Transcript of E-Cal Readout Boards
E-Cal Readout Boards
- 8 Boards total-Design & Fabrication at Jlab- Assembly at Orsay
Nick Nganga HPS Collaboration Oct 18-19 2011 - Jlab
Nick Nganga HPS Collaboration Oct 18-19 2011 - Jlab
MotherBoard
• Each Signal trace has Ground guard traces • Signal trace 8mil space 8 mil• Stackup verified in BoardSim• Crosstalk simulated for longest traces• **Board layers for Full Experiment.
• 4 Boards (2-Identical)•16- layers • 6 signal layers• 2 High Voltage• 2 Low Voltage• 6 Ground
Nick Nganga HPS Collaboration Oct 18-19 2011 - Jlab
Amplifier Connections1. GND (2 pins)2. High Voltage (1 Pin)
APD Connections (2 pins)1. Anode2. Cathode
Connection Boards • 4 Boards (2 similar) 2 Layers 2 Connectors (No traces)
Nick Nganga HPS Collaboration Oct 18-19 2011 - Jlab
Ecal Grouping
Each grouping requires its own High Voltage Connection
Nick Nganga HPS Collaboration Oct 18-19 2011 - Jlab
SI - SimulationCharacteristic Amplifier Output (DVCS 2005)
Tested on Longest Trace ~ 22inchesEquivalent to 4ns prop. delay.
Longest Trace Highlighted for Signal Integrity Analysis
Nick Nganga HPS Collaboration Oct 18-19 2011 - Jlab
Simulation
Setup:CMOS Driver with 0.8V/ns slew rate.Termination: 50-ohm.
Result:Less than 2% reflection (40mV on 2V scale)
Nick Nganga HPS Collaboration Oct 18-19 2011 - Jlab
Crosstalk Threshold set to 15mV (only one trace affected)
Crosstalk Threshold set to 20mV (Two traces affected)
CROSSTALK SIMULATION
Nick Nganga HPS Collaboration Oct 18-19 2011 - Jlab
Board Status (design)• Connection Boards ~1.5 Days– Bottom Right ~0.5 days– Top Right ~ 0.5 days– Bottom Left, Top Left ~ 0.5-day
• MotherBoards ~2.5 Days– Bottom Right ~1 day– Top Right ~ 1 days– Bottom Left, Top Left ~ 0.5-days