Journal of the Chinese Institute of Engineers, Vol. 32, No. 4, pp. 543-554 (2009) 543

*Corresponding author. (Tel: 886-6-2785123 ext. 6158; Fax:886-6-2785167; Email: jllin@mail.njcu.edu.tw)

S. P. Yang and S. F. Tang are with the Department of Engineer-ing Science, National Cheng Kung University, Tainan 701, Taiwan,R.O.C. S. P. Yang is currently at Department of ElectricalEngineering, Kun Shan University, Tainan 710, Taiwan, R.O.C.

J. L. Lin is with the Department of Engineering Science, Na-tional Cheng Kung University, Tainan 701, Taiwan, R.O.C. and iscurrently at Department of Computer Science and InformationEngineering, Chang Jung Christian University, Tainan 711, Taiwan,R.O.C.

DYNAMICAL ANALYSIS OF A NOVEL

ZERO-VOLTAGE-SWITCHING-PWM DC-DC HALF-BRIDGE

CONVERTER

Sung-Pei Yang, Jong-Lick Lin*, and Shuo-Fu Tang

ABSTRACT

In this work, based on the duty-cycle-shifted-PWM half-bridge converter, a zero-voltage-switching-PWM (ZVS-PWM) half-bridge converter is proposed. Both mainswitches of the proposed converter achieve zero-voltage-switching and the converteruses constant-frequency operation. The small-signal mathematical model for the ZVS-PWM half-bridge converter is derived. Notably, it is verified that the dynamical be-havior of the ZVS-PWM half-bridge converter is better than that of the conventionalPWM half-bridge converter from a system point of view. The accuracy of theoreticalresults is verified by simulation and experimental results. A classical controller isthen designed to achieve fast output voltage regulation despite variations in line volt-age and load resistance.

Key Words: zero-voltage-switching (ZVS), half-bridge, duty-cycle-shifted-PWM,small-signal model.

I. INTRODUCTION

The half-bridge (HB) dc-dc converter is an at-tractive topology for middle power level applicationsdue to its simplicity. The main drawback of the con-ventional symmetric control is that both primaryswitches in the converter operate using hard switch-ing conditions, which causes switching losses.Moreover, during the off-time period of the twoswitches, the oscillation between the transformer leak-age inductor and switch junction capacitor results inenergy dissipation and electromagnetic interference.Resistive snubbers are necessarily added to suppressthe ringing of the oscillation, and thus energy is sig-nificantly dissipated. The efficiency of half-bridge

dc-dc converters is thereby degraded.In order to achieve zero-voltage-switching

(ZVS) for both primary switches, the quasi-resonanttechnique has been employed for half-bridge convert-ers in (Jovanovic et al., 1989). An external inductorand capacitor can be added to decrease the resonantfrequency. The main drawback of the half-bridgezero-voltage-switched quasi-resonant converter (HBZVS-QRC) is variable-frequency operation. An out-put filter for variable-frequency operation is not easyto design.

The phase-shifted zero-voltage-switching full-bridge (Chen et al., 1995; Redl et al.,1991) is widelyused because all the switches operate at ZVS by uti-lizing a transformer leakage inductor and a switchjunction capacitor without adding any components.However, the full-bridge topology is more complexbecause of its large switch count and complicatedcontrol and driving. A simple and effective duty-cycle-shifted PWM control scheme for dc-dc convert-ers to achieve ZVS operation was employed in (Maoet al., 2003; Mao et al.; 2004, Deng et al., 2005). Byshifting one of the symmetric PWM driving signals,ZVS is achieved for one of the switches without add-ing extra components. However, the converter oper-ates at a constant- frequency and the other switch still

544 Journal of the Chinese Institute of Engineers, Vol. 32, No. 4 (2009)

operates under hard-switching condition.Based on the duty-cycle-shifted-PWM control

scheme, the ZVS-PWM technique (Barbi et al., 1990;Liu et al., 1987; Bodur and Bakan, 2002; Hua and Lee,1995; Lakshminarasamma and Ramanarayanan, 2007;Mezaroba et al., 2007) is applied to propose a novelZVS-PWM half-bridge converter. By adding an aux-iliary switch and a diode to the conventional half-bridgeconverter, both main switches achieve ZVS and theproposed converter operates at constant-frequency.

In addition, the small-signal model of the pro-posed half-bridge converter is derived for dynamicalanalysis. Notably, it is verified that the proposed con-verter exhibits better dynamical behavior than a con-ventional half-bridge converter. Based on the derivedmodel, a voltage feedback controller is designed foroutput voltage regulation despite variations in linevoltage and load resistance.

II. OPERATING PRINCIPLE

The proposed ZVS-PWM half-bridge dc-dc con-verter is depicted in Fig. 1. An auxiliary switch Sa

and a diode Da are added inside the dotted line. Usingthe duty-cycle-shifted control scheme, the driving signalof the main switch S1 is shifted and becomes close tothe driving signal of the main switch S2.

When S2 is turned off, the junction capacitor CS1

of S1 is discharged by the leakage current iLk. After

the voltage vC1 across the drain-source of S1 drops to

zero, the anti-parallel DS1 of S1 conduct current. Dur-

ing this conduction period, S1 may be turned on forZVS operation.

When S1 is turned off, the conduction of the aux-iliary switch Sa and diode Da makes the voltage acrossthe drain-source of S2 be clamped at Vi /2. Before themain switch S2 is turned on, the auxiliary switch Sa isturned off and thus the resonance between switchjunction capacitors (CS1

, CS2) and transformer leak-

age inductor Lk occurs. Hence the ZVS condition forS2 is achieved, and the proposed converter is operat-ing at constant-frequency.

Some assumptions about the proposed converterare made before the circuit is analyzed.(1) The output filter inductor Lo is sufficiently large

to be approximated by a current source with avalue equal to output current Io = Vo /R.

(2) The large-valued capacitors C1 and C2, with C1 =C2, could be approximated by a voltage sourcewith a value equal to Vi /2.

(3) Switches S1 and S2 are identical with equal junc-tion capacitances, CS1

= CS2 = C, where C is the

average capacitance of the switches.Based on the switching of switches and diodes,

the circuit operation in one switching period Ts canbe divided into nine linear stages. The stages 1-4 are

the process of commutation under ZVS at turn-on forthe main switch S1. The stages 5-9 are the process ofcommutation under ZVS at turn-on for the mainswitch S2. Each stage is related to an equivalent lin-ear circuit depicted in Fig. 2. The detailed analysisof the operating principle is described as follows.

Stage 1. [t0, t1] (S1: off, S2: off, D2: off, D3: on; Sa:off, Da: off): The main switch S2 is turned off at t =t0. The constant primary current iLk

= –nIo chargescapacitor CS2

and discharges capacitor CS1. As a

result, voltage across CS2 increases linearly and the

voltage across CS1 decreases at the same rate. The

total load current still flows through the rectifier D3.This stage terminates at t = t1, when voltage vC1

de-creases to Vi /2. The capacitor voltage and inductorcurrent are described by

vC1(t) = Vi –

nIo2C (t – t0) , (1)

vC2(t) =

nIo2C (t – t0) , (2)

iLk (t) = –nIo (3)

in this stage, and the period of this stage is given by

T1 := t1 – t0 =CVi

nI0. (4)

Stage 2. [t1, t2] (S1: off, S2: off, D2: on, D3: on; Sa:off,Da: off): At t = t1, the voltage across the transformerprimary becomes positive and the rectifier D2 beginsto conduct. The switch junction capacitors (CS1

, CS2)

and transformer leakage inductor Lk form a series-reso-nant circuit. The voltage vS1

continues to decrease be-low Vi /2 in a resonant manner. Since a positive volt-age is applied to Lk, the primary current iLk

starts toincrease. To maintain constant output current Io, bothrectifiers D2 and D3 conduct simultaneously and thetransformer secondary is shorted. The capacitor volt-age and inductor current are described by

vC1(t) =

Vi2 – nIoZnsinωr(t – t1) , (5)

vC2(t) =

Vi2 + nIoZnsinωr(t – t1) , (6)

Fig. 1 Proposed ZVS-PWM half-bridge converter

1 : n

n

Co RVo

D2

D3

i2

i3

vxIo

v2

v3

Lo

Vi

Vi

2

Vi

2

C1

C2

Sa

Da

va

S2

S1

DS2

vC2

vC1

CS2

DS1CS1

iLk

Lk

v1

Ii

S. P. Yang et al.: Dynamical Analysis of a Novel Zero-Voltage-Switching-PWM DC-DC Half-Bridge Converter 545

1 : n 1 : n

1 : n

1 : n

1 : n

S1

S1

S1

S1

S2

S2

S2

S2

n

Co Co

Co

Co

Co

RVo Vo

Vo

Vo

Vo

D2 D2

D2

D2

D2

D3

D3

D3

D3

i2 i2

i2

i2

i2

i3

D3

i3

i3

i3

i3

vx vx

vx

vx

Io Io

Io

Io

Io

v2 v2

v2

v2

v2

vx

v3 v3

v3

v3

v3

Vi Vi

Vi

Vi

Vi

Vi2

Vi2

Vi2

Vi2

Vi2

Vi2

Vi2

Vi2

Vi2

Vi2

C1

C1

C1

C1

C2

C2

C2

C2

C1

C2

Vi

Vi2

Vi2

C1

C2

Vi

Vi2

Vi2

Vi2

Vi2

C1

C2

Vi

C1

C2

Sa Sa

Sa

Sa

Sa

Da

S1

S2

Da

Sa

S1

S2

Da

Sa

Sa

S1

S2

Da

S1

S2

Da

Vi2

Vi2

Vi

C1

C2

Sa

S1

S2

Da Lk

Da

Da

Da

va va

va

va

va

va

va

va

va

DS2

vC2vC2

vC2

vC2

vC2

CS2DS2

CS2

vC2

DS2CS2

vC2

DS2CS2

vC2

DS2CS2

vC2

DS2CS2

DS2CS2

DS2CS2

DS2CS2

DS1CS1

DS1CS1

DS1CS1

DS1CS1

DS1CS1

iLkiLk

iLk

iLk

iLk

iLk

iLk

iLk

iLk

Lk Lk

Lk

Lk

Lk

Lk

Lk

Lk

vC1vC1

DS1CS1

vC1

DS1CS1

vC1

DS1CS1

vC1

DS1CS1

vC1

vC1

vC1

vC1

v1 v1

1 : n

CoVo

D2

i2

D3

i3

vxIo

v2

v3

v1

1 : n

CoVo

D2

i2

D3

i3

vxIo

v2

v3

v1

1 : n

Co

Co

Vo

Vo

D2

i2

D3

i3

vx

vx

Io

Io

v2

v3

1 : n D2

i2

D3

i3

v2

v3

v1

v1

v1

v1

v1

n

R

(a) Stage 1: [t0, t1]

(c) Stage 3: [t2, t3]

(e) Stage 5: [t4, t5]

(g) Stage 7: [t6, t7]

(b) Stage 2: [t1, t2]

(d) Stage 4: [t3, t4]

(f) Stage 6: [t5, t6]

(h) Stage 8: [t7, t8]

(i) Stage 8: [t8, t0 + Ts]

n

R

n

R

n

R

n

R

n

R

n

R

n

R

Fig. 2 Equivalent circuits in one switching period Ts

546 Journal of the Chinese Institute of Engineers, Vol. 32, No. 4 (2009)

iLk(t) = –nIocosωr(t – t1) (7)

in this stage, and the period of this stage is given by

T2 := t2 – t1 = 1ωr

sin– 1 Vi

2ZnnIo, (8)

where ωr = 1/ 2LkC is the angular resonance fre-quency and Zn := Lk/2C is the characteristicimpedance. This stage ends when voltage vS1

becomeszero and voltage vS2

becomes Vi. Subsequently, themain switch S1 should be turned on in the next stageto achieve ZVS operation. Notably, one can see fromEq. (5) that the ZVS operation can be achieved if

nIo ⋅ Zn >Vi2 . (9)

Stage 3. [t2, t3] (S1: off → on, S2: off, D2: on, D3: on;Sa: off, Da: off): When vC1

becomes zero at t = t2, theanti-parallel diode DS1

starts conducting. A constantvoltage Vi /2 is applied to Lk and the primary currentiLk

increases linearly. The main switch S1 should beturned on for ZVS before the primary current beginsto flow in the positive direction. The stage termi-nates at t = t3, when iLk

becomes equal to nIo. Thecapacitor voltage and inductor current are describedby

vC1(t) = 0, (10)

vC2(t) = Vi, (11)

iLk(t) = – (nIo)2 – (

Vi

2Zn)2 + 1

Lk

Vi

2 (t – t2) (12)

in this stage, and the period of this stage is given by

T3 := t3 – t2 =2Lk

VinIo + (nIo)2 – (

Vi

2Zn)2 .

(13)

Stage 4. [t3, t4] (S1: on, S2: off, D2: on, D3: off; Sa: off→ on, Da: off): At t = t3, the rectifier D3 is turned offand output current Io flows through rectifier D2.Therefore, the constant primary current iLk

= nIo flowsthrough main switch S1. The capacitor voltage vC1

becomes zero, while vS2 is equal to Vi. This stage

ends when S1 is turned off. In this stage, the auxil-iary switch Sa can be turned on at any time. The ca-pacitor voltage and inductor current are described by

vC1(t) = 0, (14)

vC2(t) = Vi, (15)

iLk(t) = nIo (16)

in this stage, and the period of this stage is given by

T4 := t4 – t3 = dTs –2LkVi

nIo + (nIo)2 –Vi

2Zn

2

.

(17)

Stage 5. [t4, t5] (S1: off, S2: off, D2: on, D3: off; Sa:on, Da: off): S1 is turned off at t = t4, and the constantprimary current iLk

= nIo charges CS1 and discharges

CS2. As a result, the voltage across CS1

increaseslinearly, and voltage across CS2

decreases at the samerate. The load current still flows through rectifierD2. This stage terminates at t = t5, when voltage vS2decreases to Vi /2. The capacitor voltage and induc-tor current are described by

vC1(t) =

nIo2C (t – t0) , (18)

vC2(t) = Vi –

nIo2C (t – t0) , (19)

iLk(t) = nIo (20)

in this stage, and the period of this stage is given by

T5 := – t5 – t4 =CVinIo

. (21)

Stage 6. [t5, t6] (S1: off, S2: off, D2: on, D3: off; Sa:on, Da: on): At t = t5, the voltage across the trans-former primary becomes negative and the auxiliarydiode Da begins to conduct. The conduction of theauxiliary diode Da makes the voltage vS2

be clampedat Vi /2. As a result, the resonance paused. This stageends when Sa is turned off. The capacitor voltageand inductor current are described by

vC1(t) =

Vi

2 , (22)

vC2(t) =

Vi

2 , (23)

iLk(t) = nIo (24)

in this stage, and the period of this stage is given by

T6 := t6 – t5 = (12 – d)Ts – T5 – T7 . (25)

Stage 7. [t6, t7] (S1: off, S2: off, D2: on, D3: on; Sa:off, Da: off): The auxiliary switch Sa is turned off at t= t6. The capacitors (CS1

, CS2) and leakage inductor

Lk form a series-resonant circuit. The voltage vC2 con-

tinues to decrease below Vi /2 in a resonant manner.Since a negative voltage is applied to Lk, the primarycurrent iLk

starts to decrease. To maintain constantoutput current Io, both rectifiers D2 and D3 conductsimultaneously and the transformer secondary is

S. P. Yang et al.: Dynamical Analysis of a Novel Zero-Voltage-Switching-PWM DC-DC Half-Bridge Converter 547

shorted. The capacitor voltage and inductor currentare described by

vC1(t) =

Vi

2 + nIoZnsinωr(t – t1) , (26)

vC2(t) =

Vi

2 – nIoZnsinωr(t – t1) , (27)

iLk(t) = nIocosωr(t – t1) (28)

in this stage, and the period of this stage is given by

T7 := t7 – t6 = 1ωr

sin– 1 Vi2ZnnIo

. (29)

Stage 8. [t7, t8] (S1: off, S2: off → on, D2: on, D3: on;Sa: off, Da: off): When vS2

becomes zero at t = t7, theanti-parallel diode DS2

starts conducting. A constantvoltage –Vi /2 is applied across Lk and the primary cur-rent decreases linearly. The switch S2 should beturned on for ZVS operation before the primary cur-rent begins to flow in the negative direction. TheZVS operating condition for S2 is the same as that forS1 in (9). The stage terminates at t = t8, when i1 be-comes equal to –nIo. The capacitor voltage and in-ductor current are described by

vC1(t) = Vi, (30)

vC2(t) = 0, (31)

iLk(t) = (nIo)2 – (

Vi2Zn

)2 – 1Lk

Vi2 (t – t2) (32)

in this stage, and the period of this stage is given by

T8 :=2LkVi

nIo + (nIo)2 – (Vi

2Zn)2 . (33)

Stage 9. [t8, t0 + ts] (S1: off, S2: on, D2: off, D3: on;Sa: off, Da: off): At t = t8, the rectifier D2 is turnedoff and output current Io flows through rectifier D3.Therefore, the primary current iLk

= –nIo flows throughswitch S2. The capacitor voltage vS1

becomes zero,while vS2

is equal to Vi. The capacitor voltage andinductor current are described by

vC1(t) = Vi, (34)

vC2(t) = 0, (35)

iLk(t) = –nIo (36)

in this stage, and the period of this stage is given by

T9 := dTs –2LkVi

nIo + (nIo)2 – (Vi

2Zn)2 . (37)

According to the above operating analysis, thekey waveforms over one switching period Ts are sche-matically depicted in Fig. 3. The driving signal ofthe switch S1 is shifted close to the driving signal ofthe switch S2, and thus the ZVS operation is achievednaturally for the switch S1. Moreover, when the switchS1 is turned off, the conduction of the auxiliary switchSa and diode Da makes the resonance pause in the periodT6. Before the switch S2 is turned on, the auxiliaryswitch Sa is turned off and thus the resonance occurs.The ZVS operation for the switch S2 is also achieved.

Moreover, the state portraits of (vC1, iLk

) and (vC2,

iLk) for the proposed half-bridge converter are pre-

sented in Fig. 4, which illustrates the resonances andZVS operations for both main switches.

III. MATHEMATICAL MODEL DERIVATION

In this section, the averaging method is used toderive the small-signal model for the proposed half-bridge converter. As shown in Fig.1, the variable vx

denotes the input voltage of the output filter. It canbe easily computed from Fig. 3 and stage periods inEqs. (4), (17), (21) and (37) that:

vx(t) = 1Ts

vx(τ)dτti

ti + 1Σi = 0

8

= 1Ts

12

nvi2 T1 +

nvi2 T4 + 1

2nvi2 T5 +

nvi2 T9

=nvi2Ts

CSvi2nio

+ 2dTs –4Lknio

vi

–4Lkvi

(nio)2 – (vi

2Zn)2

=: f (vi, d, io). (38)

Fig. 3 Key waveforms of the proposed half-bridge converter

t

S1(t)

v1(t)

S2(t)

Sa(t)

vx(t)

dTs

dTsTs

Vi

t

t

t

t

t

t

tnVi/2

–Vi/2

–nIo

nIo

Vi/2

Vi/2

Vi/2Vi

T1 T2 T3 T4 T5 T7T6 T8 T9t0 t1 t2 t4 t5 t6 t7 t8 t0 + Tst3 Ts

vC1(t)

vC2(t)

iLk(t)

548 Journal of the Chinese Institute of Engineers, Vol. 32, No. 4 (2009)

Notably, the moving average –vx(t) is a nonlinear functionof input voltage vi, duty ratio d and output current io.

To proceed, a small-signal model linearizedaround the operating point Q is derived as follows.Small perturbations: –vx = Vx + ~vx, vi = Vi + ~vi, d = D +~d, and io = Io +

~io, with Vx >> ~vx, Vi >> |~vi|, D >> |~d|

and Io >> |~io| are introduced into Eq. (38), yieldingthe linearized small-signal model given by

vx =∂ f∂vi Q

vi +∂ f∂d Q

d +∂ f∂io Q

i o(39)

=: kv~vi + kd

~d – r

~i.

The parameters are defined as

k v =CSVi2TsIo

+ nD +nViLk

2TsZn2 (nIo)2 – (

Vi2Zn

)2– 1

2,

k d = nVi ,

r =CSVi

2

4TsIo2 +

2n2LkTs

+2n3LkIo

Ts(nIo)2 – (

Vi2Zn

)2– 1

2.

(40)

One sees from Eq. (40) that r > 0 because of the ZVSoperating condition in Eq. (9).

Based on Eq. (39) and the output filter depicted inFig. 1, the dynamics of the proposed converter canbe represented by the block diagram depicted in Fig. 5.

It follows directly from Fig. 5 that the transferfunctions from line voltage to output and duty ratioto output are given by

vo(s)vi(s) d = 0

=k v

1LoCo

(s2 + 1RCo

s + 1LoCo

) + rR( R

Los + 1

LoCo)

, (41)

vo(s)d(s) vi = 0

=k d

1LoCo

(s2 + 1RCo

s + 1LoCo

) + rR( R

Los + 1

LoCo)

. (42)

Interestingly, the expression inside the first pa-renthesis of the denominator, on the right hand sidesof Eqs. (41) and (42), is the pole polynomial of theconventional half-bridge converter.

IV. MODEL VALIDATION

In this section, experimental measurements areused to validate the accuracy of the derived math-ematical model. The design specifications and com-ponent values of the proposed converter are listed inTable 1. A 115.2 W prototype based on the topologydepicted in Fig. 1 is built and tested to verify its op-erating principle.

Substituting the design specifications and com-ponent values listed in Table 1 into Eq. (40) yields

kv = 0.355, kd = 139.5, r = 2.18. (43)

Together with the component values listed in

Fig. 4 State portraits: (a) vC1 and iLk

, (b) vC2 and iLk

iLk iLk

S1 : turn on (ZVS)

S1 : turn off

Pause point

S1 : turn off

Pause point

S2 : turn off

S2 : turn off

Zn . nIo Zn . nIo

(0, nIo)

(0, i1(t2))

(0, 0) (0, 0)

(Vi, –nIo)

(Vi, nIo)

(Vi, i1(t2))

(0, –nIo)

(Vi, i1(t7)) (0, i1(t7))

(Vi, 0) (Vi, 0)vC1

vC2

Sa : turn on

Sa : turn off

Sa : turn on

Sa : turn off

Vi

2( , nIo)

Vi

2( , nIo)

Vi

2( , –nIo)

Vi

2( , –nIo)

Vi

2( , 0)

Vi

2( , 0)

(a) (b)

S2 : turn on (ZVS) S2 : turn on (ZVS)

S1 : turn on (ZVS)

nIo

Fig. 5 Block diagram of the proposed half-bridge converter

1sLo

io~

d~

vi~

vx~

vo~

r

R1 + sRCo

kv

kd

S. P. Yang et al.: Dynamical Analysis of a Novel Zero-Voltage-Switching-PWM DC-DC Half-Bridge Converter 549

Table 1, the transfer functions in Eqs. (41) and (42)are given by

vo(s)vi(s) = 1.42 × 106

(s + 7401)(s + 599), (44)

vo(s)d(s)

= 5.58 × 108

(s + 7401)(s + 599). (45)

Let the small-signal gain of the PWM be givenby kPWM

∆=

~d(s)/~vctrl(s) = 1/2Vp =1/20 where Vp de-

notes the peak modulation signal used in PWM. Thenthe transfer function from the control signal to theoutput voltage is

vo(s)vctrl(s) = 1

20 ⋅ 5.58 × 108

(s + 7401)(s + 599). (46)

Bode plots of the transfer function ~vo(s)/~vctrl(s)are presented in Fig. 6. The curve (1) is the theoreti-cal plot of Eq. (46) and curve (2) is the measurementresult of the implemented converter. Fig. 6 revealsthat the derived small-signal model accurately pre-dicts the dynamical characteristics of the proposedconverter.

V. DYNAMICS COMPARISON WITHCONVENTIONAL HALF-BRIDGE

CONVERTER

The pole polynomial D(s) of the transfer

functions in Eqs. (41) and (42) is given by

D(s) = (s2 + 1RCo

s + 1LoCo

) + rR( R

Los + 1

LoCo)(47)

and thus, the following implication holds

D(s) = 0 ⇔r

Lo(s + 1

RCo)

s2 + 1RCo

s + 1LoCo

=

rLo

(s + 1RCo

)

Do(s)

= – 1 , (48)

where D0(s) = s2 + s/RCo + 1/LoCo. Notably, the rootsof Do(s) = 0 are the poles of the conventional half-bridge converter.

The root locus plot of D(s) = 0 for r > 0 is plot-ted in Fig. 7. The root loci migrate toward the left-half s-plane as r increases from zero. The poles ofthe conventional half-bridge converter are located onthe root loci corresponding to r = 0. This reveals,from a system point of view, that the ZVS-PWMhalf-bridge converter exhibits better dynamical be-havior than the conventional PWM half-bridgeconverter.

For the design specifications in Table 1 with loadR = 20 Ω, the poles of the conventional half-bridgeconverter at s = –25 ± j2000 with damping ratio ζ =0.0125 are corresponding to pole locations on the rootloci at r = 0. With r = 2.18 in Eq. (43), the poles ofthe proposed ZVS-PWM half-bridge converter lie ats = –7401 and s = –599 with damping ratio ζ = 2.

Table 1 Design specifications and component values of the proposed converter

Input voltage Vi 150 V Dividing capacitors (C1, C2) 470 µFOutput voltage Vo 48 V Output capacitor Co 1000 µFDuty ratio D 0.38 Magnetizing inductor Lm 4.3 mHTurns ratio 29:27:27 Output inductor Co 250 µHLoad resistance R 20 Ω Junction capacitors (CS1

, CS2) 180 pF

Switching frequency fs 50 kHz Leakage inductor Lk 12.4 µH

Fig. 6 Bode plot of ~vo(s)/ ~vctrl(s)

20

10

0

-10

-20

0

-50

-100

-150

mag

(dB

)ph

ase

(deg

ree)

(1)(2)

101 102 103 104

101 102 103 104

frequency (rad/sec)

(1)

(2)

Fig. 7 The root loci plot of D(s) = 0

Root Locus

Real Axis

Imag

Axi

s

-3500 -3000 -2500 -2000 -1500 -1000 -500 0

2000

1500

1000

500

0

-500

-1000

-1500

-2000

r = 2.18s = -7401

= 2ζ

r = 0s = -25 + j2000

= 0.0125ζr = 0.5s = -1020 + j1740

= 0.506ζ

r = 1s = -2020 + j303

= 0.989ζ r = ∞s = -50

= 1ζr = 2.18s = -599

= 2ζ

r = 1s = -2010 – j316

= 0.988ζ

r = 0s = -25 – j2000

= 0.0125ζ

r = 0.5s = -1020 – j1740

= 0.506ζ

550 Journal of the Chinese Institute of Engineers, Vol. 32, No. 4 (2009)

Interestingly, the damping ratio of the proposedhalf-bridge converter is much larger than that of theconventional half-bridge converter. Bode plots of thetransfer function ~v(s)/

~d(s) are presented in Fig. 8. The

curves (1) and (2) are Bode plots of the conventionaland ZVS-PWM half-bridge converters, respectively.It reveals that the proposed converter exhibits betterdynamical behavior than that of the conventional half-bridge converter.

VI. SIMULATION AND EXPERIMENTALRESULTS

In this section, the IsSpice simulation and experi-mental results of the proposed converter are presented.The results verify the accuracy of the theoretical analysis.Fig. 9 presents the waveforms of the voltage vDS acrossthe drain-source of the switch. As shown in Fig. 1,the voltage vDS is equal to the voltage across the switch

Fig. 8 Bode plots of ~v(s)/~d(s) for the conventional and ZVS-PWM half-bridge converters

Bode diagram

Frequency (rad/sec)

Phas

e (d

eg)

Mag

nitu

de (

dB)

60

40

20

0

-20

-40

-600

-45

-90

-135

-180102 103 104 105

(2)

(1)

(1)

(2)

Fig. 9 (a) Simulation: vDS1 and gating signal vGS1

of switch S1, (b) experiment: vDS1 and gating signal vGS1

of switch S1, (c) simulation: vDS2 and

gating signal vGS2 of switch S2, (d) experiment: vDS2

and gating signal vGS2 of switch S2 (vDS: 50 V/div.; vGS: 5 V/div.; time scale: 0.1 µs/div.)

vDS1

vGS1

S1 : turn-on

ZVS

(a)

vDS2

vGS2

ZVS

(c)

S2 : turn-on

ZVS

vDS1

vGS1

S1 : turn-on

ZVS

(b)

vDS2

vGS2

(d)

S2 : turn-on

ZVS

S. P. Yang et al.: Dynamical Analysis of a Novel Zero-Voltage-Switching-PWM DC-DC Half-Bridge Converter 551

junction capacitor. That is vDS1 = vC1

and vDS2 = vC2

.The gating signal of the main switch is denoted byvGS. Simulation results are shown in Fig. 9(a) and Fig.9(c). Experimental results are shown in Fig. 9(b) andFig. 9(d). These results reveal that both main switchescommute under ZVS operations at turn-on. This co-incides with the analysis of the operating principle.

To compare with the simulation results pre-sented in Fig. 10(a), the experimental results of theswitch voltages, vDS1

and vDS2, are depicted in Fig.

10(b). Moreover, the simulations and experimentalresults regarding the state responses of the capacitorvoltage vC1

and inductor current iLk are presented in

Fig. 11. The capacitor voltage vC2 is neglected be-

cause of vC2 = Vi – vC1

.

VII. CONTROLLERS DESIGN

In this section, based on the derived small-sig-nal model, a classical controller is designed for theproposed half-bridge converter to regulate the outputvoltage despite variations in line voltage and loadresistance.

The root-locus method is applied to design a

classical controller. First, an integrator is added toeliminate the steady-state error, and then a zero at s =–1000 is added to improve the stability margin. Theroot locus of the closed-loop system with the classicalcontroller K(s) = k(s + 1000)/s is plotted in Fig. 12(a).Interestingly, the gain chosen as k = 3.25 is an opti-mal design with critical damping ζ = 1. Two repeatedroots lie at s = -1890. The step responses of the closed-loop system with various gains k are presented in Fig.12(b). It also shows that the closed-loop system withgain k = 3.25 is a critically damping system.As a result, a classical PI controller is given by

K(s) = 3.25(s + 1000)s . (49)

The implemented circuit of the PI controller isschematically depicted in Fig. 13.

Figure 14(a) presents the step response of theoverall system under variations in load resistance andinput voltage. The load R is initially set to 40 Ω andthe input voltage Vi is set to 150 V at t = 0 sec, andchanged to a heavy load R = 15 Ω at t = 0.01 sec, andthen changed to a lower input Vi = 140 V at t = 0.02sec. Notably, the simulation results in Fig. 14(a)

Fig. 10 Waveforms of vDS1(t) and vDS2

(t): (a) simulation (vertical: 35 V/div., horizontal: 5 µs/div.), (b) experiment (vertical: 50 V/div.,horizontal: 5 µs/div.)

vDS1

vDS2

(a)

vDS1

vDS2

(b)

Fig. 11 State responses of capacitor voltage vC1(t) and inductor current iLk

(t): (a) simulation (vertical: 35 V/div., 2 A/div., horizontal: 5 µs/div.), (b) experiment (vertical: 50 V/div., 2 A/div., horizontal: 5 µs/div.)

vC1

iLk

vC1

iLk

(a) (b)

552 Journal of the Chinese Institute of Engineers, Vol. 32, No. 4 (2009)

Real axis

(a)

Root locusIm

ag a

xis

-7000 -6000 -5000 -4000 -3000 -2000 -1000 0

Time [sec]

(b)

0 1 2 3 4 5 6 7 8

1

0.5

0

-0.5

-1

× 104

s = -7401

k = 3.25s = -4220

k = 3.25s = -1890

s = -1000

s = -599

s = 0

70

60

50

40

30

20

10

0

Vo [V]

× 10–3

k = 3.25

k = 20

k = 1k = 5

Fig. 12 (a) Root loci with respect to k > 0, (b) output step response for various gains k

Fig. 13 Implemented circuit of PI controller

ve

vctrl

1 kΩ1 kΩ

1 µF2.25 kΩ

Fig. 14 (a) Step response under variations in load resistance and line voltage, (b) time response of control signal vctrl(t) applied to PWM ofthe converter

60

50

40

30

20

10

0

vo [V]

0 0.005 0.01 0.015

Time [sec]

(a)

0.02 0.025 0.03

30

25

20

15

10

5

vctrl [V]

0 0.005 0.01 0.015

Time [sec]

(b)

0.02 0.025 0.03

Vi = 150 VR = 40 Ω

Vi = 150 VR = 15 Ω

Vi = 150 VR = 40 Ω

Vi = 150 VR = 15 Ω

Vi = 140 VR = 15 Ω

Vi = 140 VR = 15 Ω

reveal that the output voltage can be tightly regulateddespite the variations of load resistance and input voltage.

Moreover, Fig. 14(b) presents the response ofthe control signal vctrl(t) applied to PWM of the half-bridge converter. From an energy conservation pointof view, the average output power <Po>Ts

= Vo2/R is

equal to the average input power <Pi>Ts = ViIi. If the

output voltage Vo is fixed, the average output power<Po>Ts

increases as the load R decreases. The averageinput current Ii thereby increases for a fixed inputvoltage Vi. Hence the duty ratio D must increase,

and thus the control voltage vctrl necessarily increasesas shown in Fig. 14(b). On the other hand, if Vo andR are fixed and Vi decreases, and average input cur-rent Ii will increase to maintain the constant averagepower. As mentioned before, the control voltage vctrl

thereby increases.The output responses under load variations R =

40 → 15 Ω and input line voltage variations 150 →140 V are depicted schematically in Fig. 15(a) andFig. 15(b), respectively. It is worth noting from theabove experimental results that the proposed con-

S. P. Yang et al.: Dynamical Analysis of a Novel Zero-Voltage-Switching-PWM DC-DC Half-Bridge Converter 553

verter with PI controller can regulate the output volt-age in the presence of variations in load resistanceand input voltage. Moreover, from the control pointof view, the most serious disturbance to the overallsystem is the line voltage variation. However, Fig.15(b) reveals that the output voltage variation ~vo is50 mV and the line voltage variation ~vin is 10 V(150→ 140). It shows that the magnitude |~vo /~vi| is 0.005.As a result, the disturbance of the converter with feed-back control can be well rejected. Fig. 16 presentsthe measured efficiency at various load currents forthe proposed ZVS-PWM half-bridge converter. It re-veals that the efficiency of the proposed converter isabout 90% at middle load or full load current Io =3.5 A with output voltage 48 V. The efficiency atlow load current is below 88% because the ZVS op-eration condition in (9) is not satisfied, and thus themain switches cannot commute under soft switching.

VIII. CONCLUSION

In this work, a novel ZVS-PWM half-bridgeconverter is proposed. Its operating principle andsmall-signal mathematical model are presented. Bothmain switches achieve ZVS operation so switchinglosses are significantly reduced. Moreover, it is verifiedthat the dynamics of the ZVS-PWM half-bridge con-verter are better than those of the conventional half-bridge converter. Accordingly, the controller can bedesigned easily. Therefore, the proposed half-bridgeconverter is suitable for high switching frequency andmiddle power level applications. The simulationand experiment results also confirm the theoreticalanalysis.

ACKNOWLEDGMENTS

The authors would like to thank the NationalScience Council of the Republic of China, Taiwan,for supporting this research under Contract No.NSC96-2221-E-006- 317.

NOMECLATURE

C1, C2 dividing capacitorCS1

, CS2junction capacitors of main switches

C0 output capacitord duty ratioD2, D3 rectifier diodesDa the diode in the auxiliary circuitDS1

, DS2anti-parallel diodes of main switches

fs switching frequencyio output load currentkv, kd, r parameters of the small-signal modelLk leakage inductorLm magnetizing inductorLo output inductorn turns ratioR load resistanceS1, S2 main switchesSa auxiliary switcht timeTs switching periodvctrl control signalvi input voltagevo output voltageVp peak modulation signalωr angular resonant frequencyZn character impedence

Fig. 15 (a) Output voltage response as R = 40 → 15 Ω (vertical: 0.1 V/div., horizontal: 0.2 s/div.), (b) upper: input voltage Vi = 150 → 140V, lower: output voltage response (vertical: 20 V/div., 50 mV/div., horizontal: 0.2 s/div.)

Fig. 16 Measured efficiency at various load currents

94

92

90

88

86

84

82

80

78

[%]

0 10.43 2

Io [A]

3 4

η

(a) (b)

554 Journal of the Chinese Institute of Engineers, Vol. 32, No. 4 (2009)

ζ damping ratio

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Manuscript Received: Mar. 13, 2008Revision Received: Sep. 30, 2008

and Accepted: Oct. 30, 2008