July 29, 2011PHY Version: 1.00a

DesignWare Cores DDR multiPHYDatabook for SMIC40LL25

DDR multiPHY SMIC40LL25

Copyright Notice and Proprietary InformationCopyright 2011 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary informationthat is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used orcopied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced,transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior writtenpermission of Synopsys, Inc., or as expressly provided by the license agreement.Destination Control StatementAll technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationalsof other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations andto comply with them.DisclaimerSYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THISMATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR APARTICULAR PURPOSE.Registered Trademarks ()Synopsys, AEON, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra, CATS, Certify, CHIPit, CoMET, Confirma, CODE V,Design Compiler, DesignWare, EMBED-IT!, Formality, Galaxy Custom Designer, Global Synthesis, HAPS, HapsTrak, HDL Analyst,HSIM, HSPICE, Identify, Leda, LightTools, MAST, METeor, ModelTools, NanoSim, NOVeA, OpenVera, ORA, PathMill, Physical Compiler,PrimeTime, SCOPE, Simply Better Results, SiVL, SNUG, SolvNet, Sonic Focus, STAR Memory System, Syndicated, Synplicity, theSynplicity logo, Synplify, Synplify Pro, Synthesis Constraints Optimization Environment, TetraMAX, UMRBus, VCS, Vera, andYIELDirector are registered trademarks of Synopsys, Inc.Trademarks ()AFGen, Apollo, ARC, ASAP, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE,CosmosScope, CRITIC, CustomExplorer, CustomSim, DC Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision,DesignerHDL, DesignPower, DFTMAX, Direct Silicon Access, Discovery, Eclypse, Encore, EPIC, Galaxy, HANEX, HDL Compiler,Hercules, Hierarchical Optimization Technology, High-performance ASIC Prototyping System, HSIMplus, i-Virtual Stepper, IICE, in-Sync,iN-Tandem, Intelli, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library Compiler, Macro-PLUS, Magellan,Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, ORAengineering, Physical Analyst, Planet, Planet-PL, Polaris, Power Compiler, Raphael, RippledMixer, Saturn, Scirocco, Scirocco-i, SiWare, Star-RCXT, Star-SimXT, StarRC, SystemCompiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCSi, VHDL Compiler, VMC, and Worksheet Buffer are trademarks ofSynopsys, Inc.Service Marks (SM)MAP-in, SVP Caf, and TAP-in are service marks of Synopsys, Inc.

SystemC is a trademark of the Open SystemC Initiative and is used under license.ARM and AMBA are registered trademarks of ARM Limited.Saber is a registered trademark of SabreMark Limited Partnership and is used under license.PCI Express is a trademark of PCI-SIG.All other product or company names may be trademarks of their respective owners.

Synopsys, Inc.700 E. Middlefield RoadMountain View, CA 94043www.synopsys.com

2 Synopsys, Inc. July 29, 2011

DDR multiPHY for SMIC40LL25 Databook

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DDR multiPHY for SMIC40LL25 Databook ContentsContents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Databook Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Chapter 1 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

1.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141.1.1 System-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141.1.2 Component Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141.1.3 Component Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

1.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201.4 Applicable Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Chapter 2 Lane-Based Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.1 Byte Lane PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222.2 Command Lane PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252.3 PHY Utility Block Lite (PUBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.3.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282.4 PHY Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282.5 Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Chapter 3 Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

3.1 Memory Controller RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323.2 PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

3.2.1 DLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323.2.2 ITMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333.2.3 SSTL I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.3 Solution Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Chapter 4 Timing and Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

4.1 Clocking Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364.2 Command/Data To ITMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374.3 Command/Data To SDRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37July 29, 2011 Synopsys, Inc. 3SolvNet

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Contents DDR multiPHY for SMIC40LL25 Databook4.3.1 Single Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374.3.2 Double Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

4.4 Read Data From SDRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384.5 Communication with ASIC Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Chapter 5 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Chapter 6 Interface and Control Solution Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Chapter 7 External Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Chapter 8 DLL Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

8.1 DLL Library Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528.1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528.1.2 Process Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538.1.3 Metal Layer Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538.1.4 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538.1.5 Cell List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

8.2 Master DLL for DDRn (MSD_MDLL_DDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .548.2.1 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558.2.2 Master Cell Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .568.2.3 Master DLL Control for Trim and Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .568.2.4 Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .598.2.5 MDLL Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608.2.6 MDLL Reset Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

8.3 Master-Slave DLL for DDRn MSD_MSDLL_DDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .618.3.1 Master-Slave DLL Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .628.3.2 MSDLL Cell Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .638.3.3 MSDLL Control for Trim and Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .648.3.4 MSDLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .688.3.5 MSDLL Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .698.3.6 MSDLL Reset Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

8.4 Mobile DDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .708.5 DLL DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

8.5.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .718.5.2 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .718.5.3 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .728.5.4 Working with SDRAM Jitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Chapter 9 ITM Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

9.1 ITM Library Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .809.1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .829.1.2 Process Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .829.1.3 Metal Layer Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .829.1.4 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .839.1.5 ITM Cell List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .844 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook Contents9.1.6 Byte Lane PHY Construction with ITMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .859.1.7 Command Lane PHY Construction with ITMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

9.2 ITMs for Byte Lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .899.2.1 ITM for Data (MSD_ITMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .899.2.2 ITM for Strobe (MSD_ITMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .959.2.3 ITM Byte Lane Clock Buffer (MSD_ITMBB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1059.2.4 ITM Byte Lane Fill Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

9.3 ITMs for Command Lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1109.3.1 ITM for Command (MSD_ITMC_D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1109.3.2 Command Lane Clock Buffer, Stage 0 (MSD_ITMCB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1159.3.3 Command Lane Clock Buffer, Stage 1 (MSD_ITMCB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1179.3.4 ITM Command Lane Fill Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

9.4 DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1209.4.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1209.4.2 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1209.4.3 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

9.5 Placement Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Chapter 10 SSTL I/O Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

10.1 SSTL I/O Library Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13010.1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13010.1.2 Process Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13010.1.3 I/O Metal Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13110.1.4 Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13210.1.5 Cell List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13310.1.6 Cell Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

10.2 Bi-Directional Buffer (MSD_D3R_PDDRIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13610.2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13610.2.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13710.2.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

10.3 Differential Bi-Directional Buffer (MSD_D3R_PDIFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14010.3.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14010.3.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14110.3.3 Differential Cell Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

10.4 ZQ Calibration Cell (MSD_D3R_PZQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14410.4.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14410.4.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14610.4.3 ZPROG Settings for Zo and ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

10.5 Impedance Calibration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14910.5.1 Direct Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15010.5.2 Override Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15010.5.3 Custom Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

10.6 Impedance Control Logic (MSD_D3R_zctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15610.6.1 Applicability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15610.6.2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15710.6.3 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15710.6.4 Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

10.7 Reference Voltage Cell (MSD_D3R_PVREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16010.7.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160July 29, 2011 Synopsys, Inc. 5SolvNet

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Contents DDR multiPHY for SMIC40LL25 Databook10.7.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16010.7.3 Requirements for Powering Up/Powering Down PVREF . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

10.8 Retention Latch Enable Input (MSD_D3R_PRETLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16210.8.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16210.8.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16210.8.3 Retention Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

10.9 Retention Latch Enable Input - External (MSD_D3R_PRETLEX) . . . . . . . . . . . . . . . . . . . . . . . . . . .16910.9.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16910.9.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16910.9.3 Retention Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

10.10 Retention Latch Enable Input - Core (MSD_D3R_PRETLEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17610.10.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17610.10.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17610.10.3 Retention Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

10.11 Analog Signal Cell (MSD_D3R_PAIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17810.11.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17810.11.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

10.12 Power/Ground Supply Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17910.12.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17910.12.2 Cell List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

10.13 Corner and Filler Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18110.13.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18110.13.2 Cell List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

10.14 Wire Bond Pad Cells with Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18310.15 SnapCap Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18510.16 SSTL I/O DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

10.16.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19010.16.2 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19110.16.3 DC Drive Mode Power Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19710.16.4 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21110.16.5 Decoupling Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21610.16.6 ESD and LU Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

10.17 Power-Up/Power-Down Sequence Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2196 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 DatabookRevision History

The following table provides revision history for this document.

PHYVersion

DatabookVersion Date Description

1.00a 1.00 July 29, 2011 Initial releaseJuly 29, 2011 Synopsys, Inc. 7SolvNetDesignWare.com

Revision History DDR multiPHY for SMIC40LL25 Databook8 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 DatabookPreface

This document describes the DWC DDR multiPHY for communicating with DDRn SDRAMs. This PHY is part of the DDRn SDRAM Interface solution, designed specifically for ease of use, ease of implementation, and robust system timing while maximizing channel bandwidth.

The DDR2/3-Lite/mDDR features support for the following: DDR2 DDR3 Mobile DDR (also referred to as mDDR and LPDDR) LPDDR2

The PHY works with the following memory controllers: DWC Universal Protocol Controller (uPCTL) DWC Universal Memory Controller (uMCTL)

The PHY corresponds to DDR multiPHY for SMIC40LL25 in the SolvNet database.

Databook OrganizationThe chapters of this databook are organized as follows:

Product Overview provides an overview of the solution, key features, and system-level overview. Lane-Based Architecturedescribes the architecture of the PHY. Timing and Clocking discusses the critical timing relationships at the external interface. Timing Diagrams provides timing diagram examples that show the timing between the

customers ASIC logic and the Memory Controller logic, the Controller and PHY, and the external interface between the PHY I/O and the SDRAMs.

Test Methodologyprovides recommendations for testing the product. Interface and Control Solution Connectivity provides examples of connectivity within the

command and byte lane PHY components and between the PHY and Memory Controller components.

NoteNoteNoteNote The term DDRn refers to DDR2/ DDR3/ Mobile DDR/ LPDDR2

NoteNoteNoteNote In some instances, documentation-only updates occur. The DesignWare IP product information(http://www.designware.com) has the latest documentation.July 29, 2011 Synopsys, Inc. 9SolvNetDesignWare.com

Preface DDR multiPHY for SMIC40LL25 Databook External Memory Configuration provides an example of how the Synopsys DDR2/DDR3 interface is connected to DDR2 SDRAMs.

DLL Library describes the DDR2/DDR3 SDRAM interfacing DLL (Delay Locked Loop) library, a component of the PHY.

ITM Library describes the DDR2/DDR3 SDRAM Interface Timing Modules (ITMs), which are timing translation components used in a DDR2/DDR3 PHY between memory controller logic and DDR-specific SSTL I/Os.

SSTL I/O Library describes the Synopsys DDR2/DDR3 series SSTL (Stub Series Terminated Logic) I/O library.

Web Resources DesignWare IP product information: http://www.designware.com Your custom DesignWare IP page: http://www.mydesignware.com Documentation through SolvNet: http://solvnet.synopsys.com (Synopsys password required) Synopsys Common Licensing (SCL): http://www.synopsys.com/keys

Recommended ReadingThe following documentation provides essential information about Synopsys controllers that can be attached to the DDR2/3-Lite/mDDR to create a complete DDR2/3-Lite/mDDR solution, as well as information on implementing and packaging the PHY:

DesignWare Cores Universal DDR Memory Controller Databook, Synopsys, Inc. DesignWare Cores Universal DDR Protocol Controller Databook, Synopsys, Inc. DesignWare Cores DDR2/3-Lite Memory Controller Databook, Synopsys, Inc. DesignWare Cores DDR2/3-Lite Protocol Controller Databook, Synopsys, Inc. DesignWare Cores PHY Ultility Block Lite (PUBL) Databook, Synopsys, Inc. DesignWare Cores DDR2/3-Lite/mDDR/multiPHY SDRAM PHY Implementation Guide, Synopsys, Inc. Guidelines for Implementing Signaling Environments for DDRn Interfaces: Packages and PCBs, Synopsys,

Inc. DesignWare Cores DDRn SDRAM PHY Implementation Checklist, Synopsys, Inc.

Application notes maybe added after the publication of this databook, so please check the DesignWare Cores DDR2/3-Lite PHY Application Notes overview document.10 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook PrefaceCustomer SupportTo obtain support for your product, choose one of the following:

Enter a call through SolvNet. Go to http://solvnet.synopsys.com/EnterACall

and provide the requested information, including: Product: DesignWare Cores Sub Product: Memory DDRn SDRAM PHY Tool Version:

Send an e-mail message to support_center@synopsys.com. Include the Product name, Sub Product name, Process (such as, TSMC 65GP25), and Version

(product version number) in your e-mail so it can be routed correctly. Telephone your local support center.

North America:Call 1-800-245-8005 from 7 AM to 5:30 PM Pacific time, Monday through Friday.

All other countries:http://www.synopsys.com/Support/GlobalSupportCenters July 29, 2011 Synopsys, Inc. 11SolvNet

DesignWare.com

Preface DDR multiPHY for SMIC40LL25 Databook12 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook1Product Overview

Over 70% of SoCs designed today require an interface to off-chip memory. Due to their huge volumes supplying the computer market, DDRn SDRAMs are the least expensive off-chip memory solution for SoC designs. However, these memories come with a unique high-speed, parallel, source synchronous interface and complex command protocol.Synopsys DWC DDR multiPHYs are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR2 and DDR3 SDRAM memories up to 1066 Mbps data rates and Mobile DDR (also referred to as mDDR and LPDDR) SDRAM memories up to 400 Mbps data rates. This particular PHY supports switching between DDR2 and DDR3 memories once a chip is in production. This Lite PHY does not go up to the full 1600 Mpbs data rate targeted for DDR3. Instead, this is an area and feature optimized DDR2/DDR3 PHY for customers that want to go to market with DDR2 interfaces up to 1066 Mbps and also want an insurance policy against equivalent DDR3 devices becoming cheaper while their chip remains in the market. As part of the optimization of this PHY, a small number of the new features for DDR3, such as write leveling, are not supported as they are not supported by DDR2 SDRAMs.A complete memory interface and control solution is achieved when utilizing the complete component family of memory controller and PHY. The PHY consists of Interface Timing Modules, DLLs, and DDR-specific SSTL I/Os.This chapter includes the following sections:

System Overview on page 14 Key Features on page 20 Limitations on page 20 Applicable Standards on page 20July 29, 2011 Synopsys, Inc. 13SolvNetDesignWare.com

Product Overview DDR multiPHY for SMIC40LL25 Databook1.1 System OverviewThis section provides a system-level overview of the DWC DDR multiPHY in an SoC, and an overview of the components that comprise the solution.

1.1.1 System-Level Block DiagramFigure 1-1 shows the DDR multiPHY, controller solution, and related components.

Figure 1-1 DDR multiPHY and Controller Solution

1.1.2 Component PackagesProviding a robust timing system at high data rates requires hardening of critical timing components. To maximize system timing margins, timing-critical near-pad logic for DDR drive and capture has been specially designed for optimal DDR performance and hardened into a library of ITM (Interface Timing Module) components. The IP is provided as a combination of RTL for the general control logic and GDSII for the ITM, Timing DLLs, and DDR-specific I/Os to complete the PHY portion of the solution. This unique offering of soft and hard IP permits architectural design flexibility, effortless physical implementation, correct-by-construction timing closure, and seamless implementation in customer-specific design flows.

MSDLL

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To/FromASIC Logic14 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook Product Overview1.1.3 Component OverviewIn order to facilitate robust system timing and ease of use, Synopsys interface and control architecture utilizes a mixture of soft-IP and hard-IP design elements. The main control logic (Memory Controller) is supplied as soft-IP. The PHY is comprised of hard-IP components that include double-data rate Interface Timing Modules, input and output path DLLs, and application-specific SSTL I/Os.

1.1.3.1 Controller SolutionsThe Synopsyss DDR SDRAM interface and controller solution can be implemented in either the recommended implementation, a legacy implementation, or a non-Synopsys implementation.Synopsys offers the following controller solutions:

Recommended Solutions (see Recommended Solution on page 16) Universal DDR Memory Controller (uMCTL)

The uMCTL is an advanced multi-port memory controller which accepts memory access requests from up to 32 application-side host ports. Application-side interfaces can be connected to the uMCTL either through the standard AMBA 3 AXI/AHB bus interfaces or through Synopsys custom-defined interface (ENIF). The controller connects to a DFI 2.1 interface compatible PHY to create a complete memory interface and control solution. The controller includes software configuration registers, which are accessed through an AMBA 2.0 APB interface.

Universal DDR Protocol Controller (uPCTL)The uPCTL delivers efficient bandwidth with minimum latency and provides the designers with transparent access and complete control of the memory subsystem. The uPCTL serves the memory control needs of applications with simple transactions that do not require an internal scheduler, and can also be deployed with custom-designed memory management units. The uPCTL SoC application bus interface supports a lowest-latency native application interface (NIF).The controller connects to a DFI 2.1 interface compatible PHY to create a complete memory interface and control solution. The controller includes software configuration registers, which are accessed through an AMBA 2.0 APB interface.

PHY Utility Block Lite (PUBL) (see PHY Utility Block Lite (PUBL) on page 27)The PUBL is a soft-IP component to be used with the DWC DDR multiPHY. It provides control features to ease the customer implementation of digitally controlled features of the PHY such as initialization, DQS gate training, Zo and ODT impedance control, and programmable configuration controls. The PUBL has built-in self test features to provide support for production testing of the PHY. It also provides a DFI 2.1 compliant interface to the PHY.

Non-Synopsys Controller Solution (seeNon-Synopsys Controller Solution on page 17) PHY Utility Block Lite (PUBL) (see PHY Utility Block Lite (PUBL) on page 27)

This implementation does not use a Synopsys controller, but does use the PUBL to interconnect the PHY to the customer controller through the DFI 2.1 interface.July 29, 2011 Synopsys, Inc. 15SolvNet

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Product Overview DDR multiPHY for SMIC40LL25 Databook1.1.3.1.1 Recommended SolutionThe recommended solution uses the PUBLs DFI 2.1 interface to connect between the PHY and the Synopsys DWC Universal DDR Protocol Controller or DWC Universal DDR Memory Controller (see Figure 1-2 on page 16). For more information on the PUBL, refer to PHY Utility Block Lite (PUBL) on page 27.This implementation has the following requirements:

The zctrl RTL is not used in this implementation. This configuration uses the PUBL RTL, which contains the zctrl logic.

Figure 1-2 Recommended Implementation of the DDR Interface and Control Solution

Soft-IP Hard-IP

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DDR multiPHY for SMIC40LL25 Databook Product Overview1.1.3.1.2 Non-Synopsys Controller SolutionA non-Synopsys controller solution uses the PUBL's DFI 2.1 interface to connect between the PHY and the customer controller (see Figure 1-3 on page 17). This implementation has the following requirements:

The zctrl cell is not used in this implementation.

Figure 1-3 Non-Synopsys Controller Implementation of DDR Interface and Control Solution

MDLL

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CustomerControl

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Soft-IP Hard-IPJuly 29, 2011 Synopsys, Inc. 17SolvNet

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Product Overview DDR multiPHY for SMIC40LL25 Databook1.1.3.2 Controller Configurable ParametersTo permit optimum flexibility, each controller option includes a wealth of configurable parameters and register-programming options. Each controller has a user (chip-logic) interface, which is translated by the controller logic into Mobile DDR/DDR2/DDR3 transactions. To facilitate 533 MHz DDR (1066 Mbps) at the SDRAM interface, the data width throughout the controller is 2x the external data width. For example, for a 32-bit SDRAM interface, the data width throughout the controller is 64 bits. The ITMs handle both the 2x SDR to 1x DDR conversion for data output to the SDRAM and 1x DDR back to 2x SDR conversion for input from the SDRAM.

1.1.3.3 TimingIn order to maximize system timing margins on the command/write path, inputs to the SDRAM are provided with the clock or data strobe centered in the associated data eye. The ITM components perform timing translation for the various signal groups of the interface. The hardened ITM approach ensures minimal pin to pin skew while allowing optimal circuit design for drive and capture circuitry. A DLL is utilized to facilitate the clock centering. In the Command Lane, a master DLL (MDLL) is utilized. In the Byte Lane, the master portion of a master/slave DLL macrocell (MSDLL) is utilized.On the read path, read data from the SDRAM is arriving from the SDRAM edge aligned with the data strobes. In order to maintain maximum system timing margins on the input path, the data strobes are translated to the center of the data eye. The MSDLL macrocell associated with each Byte Lane contains a master DLL and 2 slave DLLs (mirror delay lines). The slave DLL portion of the MSDLL is utilized to facilitate the clock centering. DQS and DQS_b strobe inputs each utilize one of these slave DLL functions. The captured double data rate inputs are then converted to single data rate and passed onto the DDR Controller RTL logic. The ITM facilitates both data capture and DDR to SDR conversion.

1.1.3.4 SSTL I/O BuffersThe physical interface between the DDR controller and DDR SDRAMs uses DDR-specific SSTL I/O buffers with programmable on-die termination (ODT). These I/Os operate at either 1.8V for Mobile DDR/DDR2 interfacing (SSTL_18), or 1.5V for DDR3.The Synopsys memory interface and control architecture follows a common signal grouping philosophy. A Byte Lane is a complete eight-bit data unit consisting of the associated DQ, DM, and DQS/DQS_b signals. A 16-bit system would consist of two Byte Lanes. A Command Lane is a complete command and address unit including also clock signals. There would normally be only one Command Lane in a particular DDR SDRAM interface. All clock and data signals relative to a Lane, either Byte or Command, are isolated to within that Lane only. Timing critical clock and data signals do not traverse between Lanes. Implementation of a memory interface involves placing the Command Lane components, placing the Byte Lane components, and standard synthesis/place and route to complete the design.18 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook Product Overview1.1.3.5 ITM LibraryEach SSTL cell communicating with the SDRAM has an associated ITM component. The ITM library consists of individual components designed specifically for signal groups of address and command, data & data mask, and data strobes. In order to ensure low pin to pin skews and facilitate ease of implementation, the ITM components are tileable. DLL output clock distribution is embedded within the ITM components. The ITM library contains filler cells to allow continuous clock and power connections across power/gnd cell locations and to allow for variations in pad pitch. Break cells are also provided to isolate clock signals within a Lane while allowing power connections to continue.Figure 1-4 on page 19 provides a basic view of ITM cell library placement. Refer to the ITM GDSII /LEF for the actual physical design of the ITM cells.

Figure 1-4 ITM Placement

This figure provides a relative example of the ITM library functional and break cell implementation. Various width fill cells permit matching the ITM cell pitch with the desired I/O pad pitch. Larger fill cells are placed where ITM functional cells are not required, such as power cell slots. Break cells are used to discontinue the embedded clock distribution between abutting Lanes.

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Product Overview DDR multiPHY for SMIC40LL25 Databook1.2 Key FeaturesThe DesignWare Cores DDR multiPHY includes the following features:

Compatible with JEDEC standard DDR2/ DDR3LPDDR (or Mobile DDR)/ LPDDR2 SDRAMs Operating range of 100MHz (200Mb/s) to 533MHz (1066Mb/s) in DDR2/DDR3/LPDDR2 modes

Operating range of DC to 200MHz in Mobile DDR mode PHY Utility Block (PUBL) component

DFI 2.1 compliant interface to controller At-speed loopback testability

Configurable external data bus widths in 8-bit increments Permits operating with SDRAMs using data widths narrower than the implemented data width Programmable output and ODT impedance with dynamic PVT compensation Embedded Dynamic Drift Detection in the PHY to facilitate Dynamic Drift Compensation with the

controller Utilizes Master and Slave DLLs for precise timing management Lane-based architecture (Byte Lane, Command Lane) Test modes supporting IDDq and DLL characterization Library-based hard-IP PHY to permit maximum flexibility while ensuring high data rates Full documentation including physical implementation guide Includes all required views for a typical ASIC design flow

1.3 Limitations Does not support write leveling as required by DDR3 DIMM Must supply both DQS and DQS_b in DDR2 mode

1.4 Applicable StandardsThe following JEDEC standards are applicable in the DDR multiPHY design:

JESD8-15A JEDEC Stub Series Terminated Logic for 1.8V (SSTL_18)JESD79-2E JEDEC DDR2 SDRAM Specification

JESD79-3C JEDEC DDR3 SDRAM Specification

JESD209A JEDEC LPDDR (Mobile DDR) SpecificationJESD209-2B JEDEC LPDDR2 SDRAM Specification20 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook2Lane-Based Architecture

This chapter includes the following sections: Byte Lane PHY on page 22 Command Lane PHY on page 25 PHY Utility Block Lite (PUBL) on page 27 PHY Type on page 28 Floorplanning on page 29July 29, 2011 Synopsys, Inc. 21SolvNetDesignWare.com

Lane-Based Architecture DDR multiPHY for SMIC40LL25 Databook2.1 Byte Lane PHYFigure 2-1 provides an example Byte Lane configuration for discussion purposes. Actual Byte Lane configurations are dependent on the anticipated memory configuration, performance goals, and packaging technology. The designer should refer to the component datasheets for actual port lists.

Figure 2-1 Byte Lane Overview

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PUBL22 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook Lane-Based ArchitectureThe data bus interface to the external memory is organized into self-contained units referred to herein as Byte Lanes. The external memory components are designed to support Byte Lanes for optimal system timing. The partitioning of the data word into discrete Byte Lanes allows pin to pin skew to be managed across a much smaller group of signals than would typically be required. This also helps ease the task of signal track topology matching in the package and PCB environments.All components of the Byte Lane PHY are designed to permit connectivity by abutment. The ITM connects by abutment to the SSTL I/O, and the DLL connects by abutment to the ITM. It is highly recommended to implement these components by abutment whenever possible. An example scenario where this might not be possible is if filler cells are used to create a larger than minimum pad pitch, in which case the ITM would continue to abut to the SSTL I/O but the DLL may not be able to abut to the ITM due to pin alignment offsets. In such scenarios the components do also fully support standard routing for connectivity.The SDRAM contains data strobes associated with each 8 bits of data and there is a timing skew allowance between the main clock signal to the SDRAM and its data strobe inputs during a Write command (tDQSS). 8 bit memory components provide a single DQS. 16 bit memory components provide 2 DQS, one for each 8 bits. 4 bit memory components provide a single DQS where 2 components are used to realize an 8 bit word and the DQS from each of the components are connected together to interface with the host. With this 4 bit DQS connectivity, during a Write the host will drive the DQS to both components and during a Read both components together will drive the DQS back to the host, which without careful design may result in false triggering of the DQS back to the host. Due to the additional address and command signal loading and lack of a matched DQS/DQ Lane from a single device, memory systems configured with 4 bit memory components is not recommended.A Byte Lane consists of the following I/O slots:

8 data bits (DQ) data strobe bits (DQS / DQS_b) 1 data mask bit (DM) I/O power and ground cells Core power and ground cells

The number of required power cells is dependent on desired operating frequencies, packaging options, and core power requirements of the customers chip logic. It is recommended the customer work with Synopsys to determine the proper Byte Lane configuration for their design.Each functional I/O slot has an associated ITM module, including DQ, DM, and DQS/DQS_b. ITM library fill cells are inserted in the associated power cell slots to maintain a continuous ITM segment. Clock distribution is embedded within the ITM components, relieving the designer of this critical task. Corner cells are not provided in the ITM library, as Byte Lanes are not permitted to wrap around a corner of the IC. All components of a Byte Lane must reside on the same side of the IC. Complete Byte Lane units may be placed on different sides of the IC. The ITMs provide a mechanism for monitoring read timing drift, which can be used to adjust timing to maintain optimum system margins. Drift analysis and compensation is performed by the controller on a per Byte Lane basis. Read DQS recognition and drift compensation is described further in the related Memory Controller databooks. The ITM components contain the functions to monitor DQS drift and permit timing adjustment, the controller provides the analysis and control for these functions. These functions operate dynamically for each data bit of every user-issued Read command. There are no overhead penalties in channel bandwidth or utilization incurred by the use of these functions. The memory interface (PHY) architecture is based on the concept of independent, but related, signal groups to provide the highest level of system timing performance. In order to maintain robust system timing, all July 29, 2011 Synopsys, Inc. 23SolvNet

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Lane-Based Architecture DDR multiPHY for SMIC40LL25 Databookclock and data signals relevant to a Byte Lane remain within that Byte Lane. These signals are not shared between other Byte Lanes or between a Byte Lane and a Command Lane. Alternate approaches require clock distribution networks that span the full length of the interface including all address, command, and data signals. These large clock distribution networks are difficult for the user to design and implement, and add an additional component of pin to pin skew to the critical timing budget.A DLL macrocell (MSDLL) consisting of a master DLL and 2 slave DLLs (mirror delay lines) is utilized at each Byte Lane to facilitate optimal PHY timing for drive and capture of DDR data streams, and allows the Lanes to be independent. The master DLL section provides outputs for DDR data stream creation to the SDRAMs and acts as a reference for the slave delay line sections. The slave delay line sections translate the incoming DQS/DQS_b into the center of the read data eye to maximize read system timing margins.The user is permitted to fine tune the relationship of the DQS and DQ signals to maximize read system timing margin. The DLL includes adjustability of the slave delay lines for the DQS and DQS_b signals, which provide byte-wide timing adjustments. The ITMs include adjustability of the read DQS/DQS_b strobe timing, which provides byte-wide timing adjustments. The ITMs include adjustability of the read DQ signal timing, which provides per-bit timing adjustability. To permit Lane-independent timing adjustments, DLL adjustment bits are provided by the controller per Byte Lane and ITM adjustment bits are provided per bit.Synopsyss interface and control solution allows memory systems with a word width narrower than the design. For example, an IC may be designed with a 32 bit data width and this IC can then be utilized with either 16 bit or 32 bit memory systems. The controller contains register settings to allow the desired operational mode to be set in the final device. A FIFO is used in the ITM to provide reliable read data capture. This FIFO permits clock-domain crossing from the external SDRAM read DQS domain to the general control logic synthesized clock tree domain (controller clock). Each ITM requires the controller clock to read data from the FIFO. Distribution of the controller clock is not embedded in the ITMs. There are no special timing requirements for this controller clock input to the ITMs. The ITMs should be treated as any other register in the design during clock tree synthesis.The DDR-specific SSTL I/Os include programmable ODT and output impedance selection. The ODT and output impedances can be dynamically calibrated to compensate for variations in voltage and temperature. The ODT feature can be disabled by the controller. When ODT is enabled by the controller, the SSTL I/O automatically enables its internal ODT circuitry when in input mode and disable this circuitry when in output mode, as determined by the output enable signal. The initial programming and subsequent calibration of the of the ODT and output impedance is achieved through the use of an impedance control loop that can be triggered to calibrate the ODT and output impedance values at the I/Os based on the desired impedance value when compared to an precision external resistor. All the necessary pieces of the impedance control loop are included in the SSTL I/O library.The SSTL I/Os include embedded boundary scan support logic to permit the insertion of boundary scan by the customer without interfering with the matched timing of the mission-mode paths. This can also be used by the customer for test purposes other than boundary scan.The number of Byte Lanes required for a design is determined by the desired maximum databus interface width to the external memory. For example, a maximum 16 bit system would be comprised of 2 Byte Lanes and a maximum 64 bit system would be comprised of 8 Byte Lanes.24 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook Lane-Based Architecture2.2 Command Lane PHYFigure 2-2 provides an example Command Lane configuration for discussion purposes. A reduced number of address signals has been included in this figure. Actual Command Lane configurations are dependent on the anticipated memory configuration, performance goals, and packaging technology. The designer should refer to the component datasheets for actual port lists.

Figure 2-2 Command Lane Overview

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Lane-Based Architecture DDR multiPHY for SMIC40LL25 DatabookThe control and address interface to the external memory is organized into a self-contained unit referred to herein as a Command Lane. A memory interface would typically contain a single Command Lane and one or more Byte Lanes.All components of the Command Lane PHY are designed to permit connectivity by abutment. The ITM connects by abutment to the SSTL I/O, and the DLL connects by abutment to the ITM. It is highly recommended to implement these components by abutment whenever possible. An example scenario where this might not be possible is if filler cells are used to create a larger than minimum pad pitch, in which case the ITM would continue to abut to the SSTL I/O but the DLL may not be able to abut to the ITM due to pin alignment offsets. In such scenarios the components do also fully support standard routing for connectivity.A typical Command Lane consists of the following I/O slots:

1 system clock input (optional) Memory clocks (CK/CK_b) Command signals (RAS_b, CAS_b, WE_b) 1 or more clock enable (CKE) 1 or more on-die termination (ODT) 0 or more chip select (CS_b) 2 or 3 bank address (BA) Up to 16 row/column address (A) I/O power and ground cells Core power and ground cells

Note that for LPDDR2, the address/command address bus (CA) is 10-bit wide and there is no command signals (RAS_b, CAS_b, WE_b.The system clock input is used to provide the source clock for the memory interface. If the system clock is being provided from an on-die source, this input is not required.Each memory controller supports from 1 to 4 SDRAM ranks. There is one CKE, ODT, and CS_b signal provided for each rank. The designer can set the maximum number of ranks to be supported at compile time. Note that if a single-rank system is used, the CS_b output can be removed. In this case the CS_b input of the DRAM(s) is tied low on the PCB.The number of required power cells is dependent on desired operating frequencies, packaging options, and core power requirements of the customers chip logic. It is recommended the customer work with Synopsys to determine the proper Command Lane configuration for their design.Each functional I/O slot has an associated ITM module, with exception of the system clock input. ITM library fill cells are inserted in the associated power / system clock cell slots to maintain a continuous ITM segment. Clock distribution is embedded within the ITM components, relieving the designer of this critical task. Corner cells are not provided in the ITM library, as the Command Lane is not permitted to wrap around a corner of the IC. All components of the Command Lane must reside on the same side of the IC.A master DLL (MDLL) is utilized with the Command Lane to facilitate optimal PHY timing for drive of DDR data streams, and allows the Lane to be independent. The DLL macrocells provide two 0 degree phase outputs, one which can be used to drive the controller logic. The Command Lane MDLL is used for this purpose. Standard clock tree synthesis tools can be applied from this DLL output. Clocking of the memory interface and control solution is described later in this document.26 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook Lane-Based ArchitectureTo permit Lane-independent timing adjustments, DLL and ITM adjustment bits are provided by the controller separately for Command and Byte Lanes.

2.3 PHY Utility Block Lite (PUBL)The PUBL is a soft IP component to be used with the DWC DDR multiPHY. It provides control features to ease the customer implementation of digitally controlled features of the PHY such as initialization, DQS gate training, and programmable configuration controls. The PUBL has built-in self test features to provide support for production testing of the DWC PHY. It also provides a DFI 2.1 compliant interface to the PHY. The PUBL includes configuration registers that are accessible via a configuration port. The configuration port can be either a generic configuration interface (CFG) or an APB interface. There is also an optional JTAG interface that improves access for test functions. An example of a complete memory interface and control solution (Figure 2-3 on page 27) is achieved when the PUBL is combined with Synopsys DWC DDR multiPHY and with either Synopsys Universal Controllers (uPCTL or uMCTL) or a third party controller.

Figure 2-3 DDR Memory Interface and Control SolutionJuly 29, 2011 Synopsys, Inc. 27SolvNet

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Lane-Based Architecture DDR multiPHY for SMIC40LL25 Databook2.3.1 Key FeaturesThe PUBL supports the following features:

DDR/DDR2/DDR3/DDR3L/mDDR (LPDDR)/LPDDR2 operation Scalable performance from 0 MHz (LPDDR) through DDR3-1066 Maximum controller clock frequency of 533 MHz resulting in maximum SDRAM data rate of

1066Mbps Data path width scales in 8-bit increments Multiple (4) memory rank support Complete PHY initialization, training and control Automatic DQS gate training and drift compensation At-speed built-in-self-test (BIST) loopback testing on both the address and data channels for DWC

DDR multiPHYs PHY control and configuration registers APB or generic interfaces to configuration registers Optional, additional JTAG interface to configure registers DFI 2.1 interface

A full description of the PUBL is contained in the standalone DesignWare Cores DDR1/2/3 SDRAM PHY Utility Block (PUBL) Databook.

2.4 PHY TypeThe Synopsys DesignWare DDR multiPHY PHYs include minor differences for the various PHYs to support orientation sensitive processes. This has resulted in minor changes in SSTL and ITM cell selection. The PUBL is a configurable soft IP and may be configured to support each PHY. To easily distinguish between these PHYs they are denoted by TYPE A and TYPE B1 in the DesignWare Cores PHY Utility Block "Lite" (PUBL) databook. The SMIC40LL25 PHY is of PHY TYPE A, and the PHY Utility Block "Lite" (PUBL) must be configured for this type when using this PHY.

NoteNoteNoteNote You must make sure you are using the latest available version of the PUBL. Refer to the DesignWareCores PHY Utility Block "Lite" (PUBL) Release Notes and PHY Utility Block "Lite" (PUBL) Databookfor details.28 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook Lane-Based Architecture2.5 FloorplanningFigure 2-4 provides basic examples of proper memory interface floorplanning. There are a few simple guidelines to keep in mind when floorplanning the PHYs.

Figure 2-4 PHY Floorplanning Examples

Follow these guidelines to ensure a robust design with ease of integration.1. Insert ITM break cells at the end of a given byte lane when it will abut with another byte lane to

ensure clock signals do not cross Lanes. Command Lane ITMs do not physically abut to Byte Lane ITMs, therefore, a space is required to prevent these two ITM types from interacting.

2. Place all components of a lane on the same side of the IC. Only wrap around corners at lane boundaries.

3. Position the lane clocking signals (CK/CK_b, DQS/DQS_b) centered in the Lane.4. Position the DLL for a Lane centered in the length of the Lane.July 29, 2011 Synopsys, Inc. 29SolvNet

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Lane-Based Architecture DDR multiPHY for SMIC40LL25 Databook5. Position the Command Lane equivalently centered in the Byte Lanes when utilizing balanced tree Command Lane routing on the PCB. If using a pseudo-fly-by routing style for the Command Lane signals on the PCB, where the Byte Lane signals are effectively length matched to the Command Lane signals for each SDRAM component, than it may improve efficiency to place the Command Lane at one end of the group of Byte lanes.

6. Aside from placing the padframe cells for Command and Byte Lanes, a number of VREF supply cells must be placed to ensure the VREF supply on the die is free of coupling noise. Refer to the Physical Implementation Guide for VREF implementation guidelines.

Please refer the Physical Implementation Guide for further design and implementation details.30 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook3Test Methodology

This chapter outlines testing recommendations for the Memory Interface and Control Solution.This chapter includes the following sections:

Memory Controller RTL on page 32 PHY on page 32 Solution Testing on page 34July 29, 2011 Synopsys, Inc. 31SolvNetDesignWare.com

Test Methodology DDR multiPHY for SMIC40LL25 Databook3.1 Memory Controller RTLThe general logic of the Controller is delivered as synthesizable RTL. It is suggested the customer add internal scan and utilize ATPG for production testing. This will provide traditional Stuck-At and Stuck-Open fault coverage. Scan techniques using low-speed ATE hardware to provide Delay-Fault testing are now popular. In process geometries of 130nm and below, resistive faults begin to appear which are not hard faults that can be detected by traditional low-speed stuck-at testing. Delay-faults are of high enough resistance that the net drivers can overcome them at low speed, however they extend the amount of time required for the driver to pull the net to a logic 0 or 1 level, thus at higher speeds they have the effect of slowing down net transitions and possibly causing timing errors. When possible, it is recommended to implement delay-fault testing to improve your overall test strategy.

3.2 PHYThis section describes the blocks of the PHY.

3.2.1 DLLsFor low-speed functional test purposes of circuitry outside of the DLL, the DLL contains a bypass mode to buffer the input clock to the output clocks. Bypass is also used for IDDq test mode as all DC current paths within the DLL are disabled when bypass is asserted.The DLL jitter, lock range, and characterization across PVT can be measured using the CK/CK_b and DQS/DQS_b output clocks. Phase relationships can be determined by viewing a DQS output and a DQ output simultaneously. These tests are functional tests requiring a small test vector set and the ability to operate the design at the maximum clock rate on the ATE. Direct pin measurements such as these provide good system-level measurements, but due to the ITM in the path do not allow direct access to characterize the DLLs. It is also not always possible to operate the ATE at full interface speed test rates.For enhanced characterization purposes, the DLLs include special analog and digital test outputs for viewing various internal signals and references. The use of these test outputs requires the addition of 1 analog signal pad (included in the SSTL I/O library) and 2 SSTL I/O pads on the die. It is recommended that the customer add these extra signals to allow DLL characterization in the final design.The DLLs include the ability to place their analog test output into tristate, thus the DLL analog test outputs can be connected together and only one analog test output is required to observe all DLLs on the die. In this method the analog test output from only 1 DLL is enabled at a time. The digital test outputs from the DLLs can be routed to the 2 digital test outputs of the die and the customer implements muxing to select one DLL at a time. The two digital test outputs are required to be able to perform phase measurements. The digital test output path requires the ability to pass 533MHz clock signals through the output.By implementing the above recommendation of 3 dedicated test pins which are shared for all DLLs of the design, each DLL of the design can be directly characterized and it can be performed on a lower-speed ATE. The load board and/or DUT card for the ATE could be designed such that after setting the device into test mode, a PLL or other clock source can be substituted for the ATE clock input such that the DLLs can be ramped-up to the desired operating frequency. Time measurement equipment can then be used to capture data such as jitter and phase relationships. Scopes could also be used to monitor the waveforms.32 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook Test Methodology3.2.2 ITMsThe ITM macrocells are not included in logic scan due to the critical timing nature of the drive and receive logic and the issue of modeling the ITM functionality to ATPG tools. These modules are efficiently tested with a simple functional test pattern. For complete testing, it is suggested that a functional test be run which performs a series of Write commands followed by a series of Read commands in which a one-hot pattern can be created at the external interface. For example, a device with a 16-bit data bus width might use two Write commands and two Read commands, each burst of 8. A walking 1 pattern would be used for the commands to get full test coverage of the databus. A second series of Write commands with a walking data mask activation would permit full test coverage of the mask bits. A third series of commands can be output with a walking bit pattern to verify the command and address signals.Testing of the ITM drift detection and compensation requires the ability to operate the device on an ATE capable of operating at a test rate supported by the solution with the DLLs enabled, i.e. 125MHz/250Mbps or higher. For this test a normal Read operation functional test vector is established. In the same test case, after a normal read operation the timing of the Read data back to the device is altered such that it should cause a 90 degree adjustment in the DQS window. This is repeated 4 times such that the window is moved a full 360 degrees in one direction. The same operation is repeated, this time moving the window in the opposite direction. A successful Read operation under these changing conditions indicates the drift detection and compensation is working properly.Examples of these testcases is included in the verification environment delivered with the memory controller RTL.

3.2.3 SSTL I/OsThe SSTL I/O buffer is designed to allow the input buffer to be placed into an LVCMOS mode, called Mobile DDR mode. When performing IDDq testing, the user can place the I/Os into a low-power mode. In this mode, the SSTL input buffer mode, which consumes static current, is disabled and the Mobile DDR input buffer mode enabled. Note that this mode only disables the SSTL static current paths. The user must also bypass the DLLs, which also disables all of their internal static current paths.Much of the required testing of the SSTL I/O can be performed with the same testing used for the ITMs. This includes VOH, VOL, VIH, VIL, leakage current, and drive current. The ITM vectors should, if required, be supplemented with vectors which test different I/O voltages (1.8V versus 1.5V), SSTL ODT and SSTL drive strength options. Testing is not required for modes which are not used in the end application.As an alternative access method, the embedded boundary scan logic of the SSTL I/Os, if used, is an excellent method of testing I/O parameters such as VOH/VOL/VIH/VIL. This test support logic could also be used by the customer for other test purposes for their chip.Regarding the impedance control logic of the SSTL I/O, be aware of the following guidelines:

You can override the impedance control logic and write whatever drive codes you wish into the registers that control pull-up and pull-down ODT and Zout.

You can let the impedance control logic perform its PVT compensation and then freeze the code so it no longer changes.

In order to run the PVT compensation closed-loop system, you must have the prescribed external resistor connected to the ZQ pin. July 29, 2011 Synopsys, Inc. 33SolvNet

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Test Methodology DDR multiPHY for SMIC40LL25 Databook3.3 Solution TestingThe main method of testing connectivity of the entire solution is through the use of a relatively small functional test vector set. This will be performed by the ITM and SSTL functional test vectors.Low-speed testing with the DLLs bypassed will give a good measure of output time matching of the clock, strobe, address/ command, and data signals taking into account the system reference clock distribution to the DLLs, the ITM clock distribution, the ITM output circuitry, and the SSTL output circuitry. At-speed functional testing will also allow output time matching checks to be performed, and will allow the phase relationships of the clock and data signals to be verified. Where possible, testing the solution at-speed with a select set of functional test vectors provides a good degree of testing. When at-speed is not possible, defaulting to partial at-speed if the ATE platform is capable of operating within the normal operating range of the system with the DLL enabled will still provide a higher level of testing than low-speed functional test alone. Normally some level of low-speed functional test vectors are required to supplement the at-speed or partial at-speed tests to achieve a high overall test coverage.For ATE platforms that cannot support at-speed testing due to the double data rate bandwidth (i.e. 250MHz clock = 500Mbps data rate), 2-pass testing could be an option. The data stream can be created such that it only switches once per clock cycle instead of twice per clock cycle. This is done by driving the same data twice. For example, one set of test vectors would transition data in the first bit period and drive that same data in the second bit period. The second set of test vectors would transition data in the second bit period and drive that same data in the following first bit period. Most ATE platforms today support pin muxing and/or pattern muxing which allow an effective doubling of the test rate, permitting at a minimum partial-at speed testing with or without a 2-pass test methodology.While performing at-speed or partial at-speed testing it is recommended to apply different forms of noise patterns and observe the response. The greatest amount of noise in the interface solution is created by the output drivers. Testing with data patterns of very low switching activity (i.e. 1 bit switching) and data patterns of high switching activity (i.e. all outputs switching 0-1-0-1 simultaneously) is an excellent test for noise impact.At-speed testability is supported through the PUBL. Refer to the DesignWare Cores DDR1/2/3 SDRAM PHY Utility Block (PUBL) Databook.34 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook4Timing and Clocking

This chapter includes the following sections: Clocking Overview on page 36 Command/Data To ITMs on page 37 Command/Data To SDRAMs on page 37 Read Data From SDRAMs on page 38 Communication with ASIC Logic on page 38July 29, 2011 Synopsys, Inc. 35SolvNetDesignWare.com

Timing and Clocking DDR multiPHY for SMIC40LL25 Databook4.1 Clocking OverviewThe interface and control solution is based on the use of DLLs in conjunction with ITMs to manage the critical timing relationships at the external interface. The architecture naturally places timing priority on the external interface. The PHY is designed such that interface timing is correct by construction. Once placement of the Lane components (I/O, ITM, DLL) is complete, there are no timing closure issues or static timing analysis required for the PHY portion of the interface. The general control logic RTL is designed such that synthesis/place & route and timing closure will not pose a challenge even at a clock rate of 533MHz. There are only two timing relationships of focus to complete the implementation passing data from the general control logic to the ITMs, and communication between the customers ASIC logic and the Memory Controller host port logic.Figure 4-1 provides a block diagram of the clock architecture for the solution to be used for discussion purposes, assuming the DWC memory controller is implemented. Please refer to the component databook for actual port names.

Figure 4-1 Solution Clocking Overview

QD

QD

Q D

QD

ITM

Q D

Q D

QD

QD

QD

Q D

System Clock

SynthesizedClock Tree

Controller

DQ

/DM

ADD

R/C

MD

/CK

/CK_

b

ITM

ITM

DQSb_90

CLKCCLK_0

CLK_0CLK_90

CLK_180CLK_270DQS_90

MSDLL

Memory

DQS

/DQS

_b

DQS_bDQS

MDLL

CCLK_0CLK_0

CLK_90CLK_180CLK_270

CLK

ADD

R/C

MD

/DAT

Afo

rclo

ckcr

oss

ing

logi

cto

chip

logi

cD

ATA

from

chip

logi

cCo

nfig

ADD

R/C

MD

/DAT

Afro

m/to

chip

logi

c

ITM

rclk36 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook Timing and ClockingThe system clock is the reference clock for the interface, which can operate at up to 533MHz. The system clock may be provided externally or from an on-die source. Each Lane contains a dedicated DLL (MDLL, MSDLL) which is used to create clock phases used for PHY timing management. The clock phases produced are 0, 90, 180, and 270 degrees. The customer distributes the system clock to the DLL in each Lane. The customer should ensure that this distribution has a relatively low skew (

Timing and Clocking DDR multiPHY for SMIC40LL25 DatabookFigure 4-2 Output Signal Timing from PHY for SDRAM Interfacing

4.3.2 Double Data RateThe address and command lines are commonly more heavily loaded than data lines due to data width expansion (multiple memory devices to create a wide word width). LPDDR2 uses double data rate on the address and command lines. LPDDR2 is enabled through the Timing Mode Select Line (tmsel) signal.For more information, refer to ITMs for Command Lane on page 117.

4.4 Read Data From SDRAMsDuring a Read command, the SDRAMs output the DQS/DQS_b and DQ edge aligned. The slave DLLs (mirror delay lines) within the MSDLL at each byte lane are used to shift the incoming DQS/DQS_b strobes by 90 degrees to place them into the center of the data eye for capture of the DQ. In order to permit customers to fine-tune the relationship of the shifted DQS and the data eye at the capturing ITM, per-byte timing adjustment is included in both the MSDLL and the ITMs. In addition, per-bit timing adjustability is included in the ITMs.After capturing the read data, it is entered into a FIFO within the ITM. A data valid flag is supplied by the ITM to indicate to the controller when it can fetch the data. This permits an asynchronous crossing of the DQS clock domain back to the controller clock domain, removing timing constraints on this path. The synthesized controller clock tree will connect to the ITMs for reading of the FIFOs. Communication from the ITM back to the controller is direct register to register. There are no special clocking requirements on this Read path, standard synthesis, place & route, and STA methods are used.Due to inherent system-level skews between data bits within a byte lane, it is possible that the controller may see the valid flags asserted for some data bits at the end of one controller clock cycle and the remaining data bit valid flags asserted at the beginning of the next clock cycle. This is permitted. The controller performs a logical AND of all data bit valid flags within a byte lane, and when all are asserted it immediately fetches the data. The ITM is designed to permit such timing behavior.Due to inherent system-level skews between byte lanes, it is possible that the controller may see the valid flag asserted from some byte lanes at the end of one controller clock cycle and the remaining byte lane valid flags asserted at the beginning of the next clock cycle. This is permitted. The controller will independently fetch data from each byte lane when all bits of the lane are available, and then aligns the captured data from each byte lane before further processing the captured read data.

4.5 Communication with ASIC LogicAt the host ports, communication between the controller and the ASIC logic is synchronous to the controller clock domain. In most instances the memory interface is designed to operate at a different clock rate than 38 Synopsys, Inc. July 29, 2011SolvNetDesignWare.com

DDR multiPHY for SMIC40LL25 Databook Timing and Clockingthe asic logic, at an adjustable clock rate versus the ASIC logic, or the various host ports are required to operate at different clock rates. In these circumstances the designer is to add clock domain crossing logic external to the controller host ports. A port is added to the controller interface to provide a convenient connection point to the controller clock for the ASIC chip logic to be used for clock crossing logic. Additional discussion of clock crossing at the controller/ASIC logic interface can be found in the memory controller databook.In instances where the chip logic interfacing with host ports is to operate at the same clock rate as the memory controller and clock crossing logic is not desired, direct communication is accommodated. If there is a relatively small amount of chip logic, it is possible to drive it directly from the clock output provided for clock domain crossing logic, and this branch would be taken into account during normal clock tree synthesis such that all points are within the user-defined clock skew parameters.If there is a large amount of chip logic that may make the total insertion delay of the controller clock too great to ensure proper timing to the ITMs, the clock output for clock crossing could be treated as the root for a second pass of clock tree synthesis for the chip logic, paying attention to ensure the insertion delay to the chip logic permits proper communication to and from the controller logic.Figure 4-3 on page 39 provides a brief look at this scheme.

Figure 4-3 Direct Communication with ASIC Logic

In this scheme the controller logic clock is synthesized such that the CLKOUT path is constrained with a lower insertion delay than the rest of the tree endpoints. This leaves timing margin for the subsequent chip logic clock tree synthesis.The following example in Table 4-1 on page 40 shows the collective insertion delay of the chip logic versus the insertion delay to the controller logic registers results in a large setup time margin but a low hold time margin. In this case the hold margin can easily be raised by allowing the optimization tool to add buffers in the DOUT path.July 29, 2011 Synopsys, Inc. 39SolvNet

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Timing and Clocking DDR multiPHY for SMIC40LL25 DatabookA further option for direct communication between the chip logic and the controller host port logic involves multi-pass clock tree insertion. In this scenario the asic logic and the memory interface and control solution are treated as separate logical entities. A clock tree is synthesized for the chip logic. Separately the clock system for the memory controller is developed, as a cclk_0-based timing system as previously described. Once the insertion delay for the memory controller logic clock (including DLL) and the chip logic clock are known, a top-level balancing using the clock tree synthesis tool is performed. The designer must take into account the varying delay of the DLL based on clock frequencies and operating mode. Also the designer must be aware that the two clock paths will have different logical structures, and timing must be well margined to allow for PVT variances. The designer must apply great attention to detail in timing analysis to ensure the system works properly and is adequately margined. This method of clock balancing is not recommended for most scenarios.Additional clocking examples for direct communication when there is a large ASIC clock insertion requirement include use of DLLs and/or PLLs between the controller clock domain and the ASIC clock domain to effectively zero-out the insertion delay of the ASIC clock domain. This method of clocking can be applicable in many situations.Customers are encouraged to discuss their clocking requirements with Synopsys in order to plan the most appropriate clocking strategy for the application.

Table 4-1 Insertion Delay Example

Reviewing the DIN path

Delay

Insertion delay of Controller logic clock to CLKOUT 0.300 ns

Insertion delay of chip logic clock 0.200 ns

Chip logic register clock to data out 0.200 ns

Routing delay 0.150 ns

Controller register setup time requirement 0.150 ns

Total time required 1.000 ns

Clock cycle @ 533 MHz 1.875 ns

Setup Time Margin 0.8