DVCS Calorimeter Trigger Version 2014 ---- Technical...

Fichier : DVCS TRIGER version 2014 création le : 24 septembre 2013 sur 33

DVCS Calorimeter Trigger

Version 2014

Laboratoire de Physique Corpusculaire de Clermont-Ferrand

CNRS – IN2P3 / Université Blaise Pascal

Auteur Magne Magali Date 24/09/2013 Réf. AAAAA

DVCS Calorimeter Trigger Version 2014

----

Technical Information Manual

---- DRAFT

Version: 24/09/2013

Laboratoire de Physique Corpusculaire de Clermont-Ferrand CNRS – IN2P3 / Université Blaise Pascal

Magne Magali 24 Avenue des Landais

BP 80026 F-63171 AUBIERE CEDEX

Contact: [email protected]

mailto:[email protected]



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Table des matières

1. VME_CONTROL BOARD ..................................................................................................................... 4

1.1. Front panel: .................................................................................................................................................. 4

1.2. More information ......................................................................................................................................... 4

2. CALORIMETER VERSUS TRIGGER INPUTS ................................................................................. 5

2.1. Calorimeter ................................................................................................................................................... 5

2.2. Trigger inputs and board mezzanine reference ............................................................................................. 6

2.3. Trigger inputs and board mezzanine reference versus FPGA and VHDL assignments .................................... 7

2.4. Calorimeter versus FPGA .............................................................................................................................. 8

2.5. Calorimeter versus FPGA and VHDL assignments .......................................................................................... 8

3. TRIGGER BOX ....................................................................................................................................... 9

3.1. Right part view ............................................................................................................................................. 9

3.2. Front LEMO Output signals ..........................................................................................................................10

4. VME INTERFACE BY THE VME TRIGGER INTERFACE .......................................................... 11

4.1. Addressing is the base address using ...........................................................................................................11

4.2. VME address modifier used .........................................................................................................................11

4.3. Addressing standard A24 .............................................................................................................................11

5. REGISTERS ......................................................................................................................................... 12

5.1. Register addresses .......................................................................................................................................12

5.2. Equations ( defini dans le code ) of output LEMO .........................................................................................14

5.3. Reading register FIFOEventData data order reg0x080 more details or by BLT at the reg 0x110 ...................15

6.1. Typical trigger signals ...................................................................................................................................16

6.2. JTAG daisy chain ..........................................................................................................................................17

6.2.1. for DATA_FPGAs ctrl_FPGA ..........................................................................................................................17



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6.2.2. For logic unit ................................................................................................................................................18

6.2.3. Verify which version is programming ...........................................................................................................18

7. C TEST PROGRAM ............................................................................................................................ 19

7.1. InitTrigger1E ................................................................................................................................................19

7.2. Read_1E .......................................................................................................................................................23

7.3. READ1E_BLT.C drivers Clermont ..................................................................................................................27

8. TROUBLE SHOOTING: PROBLEMS CAN OCCUR: .................................................................... 31

8.1. JTAG Chain 1 and 2 don’t works ...................................................................................................................31



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1. VME_control Board Inside the VME crate and interconnect to the trigger box by 2 flat cables.

1.1. Front panel:

Vme coding address: by default the board is configure at the address x1E

1.2. More information

To Trigger BOX Connector VME RIGH and Left Cable 34 contacts



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2. Calorimeter versus trigger inputs

2.1. Calorimeter

15 31 47 63 79 95 111 127 143 159 175 191 207 14 30 46 62 78 94 110 126 142 158 174 190 206 13 29 45 61 77 93 109 125 141 157 173 189 205 12 28 44 60 76 92 108 124 140 156 172 188 204 11 27 43 59 75 91 107 123 139 155 171 187 203 10 26 42 58 74 90 106 122 138 154 170 186 202 9 25 41 57 73 89 105 121 137 153 169 185 201 8 24 40 56 72 88 104 120 136 152 168 184 200 7 23 39 55 71 87 103 119 135 151 167 183 199 6 22 38 54 70 86 102 118 134 150 166 182 198 5 21 37 53 69 85 101 117 133 149 165 181 197 4 20 36 52 68 84 100 116 132 148 164 180 196 3 19 35 51 67 83 99 115 131 147 163 179 195 2 18 34 50 66 82 98 114 130 146 162 178 194 1 17 33 49 65 81 97 113 129 145 161 177 193 0 16 32 48 64 80 96 112 128 144 160 176 192



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2.2. Trigger inputs and board mezzanine reference



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2.3. Trigger inputs and board mezzanine reference versus FPGA and VHDL assignments



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2.4. Calorimeter versus FPGA

2.5. Calorimeter versus FPGA and VHDL assignments



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3. Trigger Box

3.1. Right part view



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3.2. Front LEMO Output signals

It’s the same of the previous trigger version Part right:

The adding input and outputs lemo and ecl are not defined at the moment.



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4. VME interface by the VME trigger interface

4.1. Addressing is the base address using The card works in A24 mode

4.2. VME address modifier used AM (5…0) compatible: $ 39 A24 Non-privileged data access $ 3B A24 Non-privileged block transfer (BLT) Figure 1 Address modifiers compatible

4.3. Addressing standard A24 Bit (23… 20) : internally frozen at level "0" Bit (19) : configurable by the switch (B2) Bits (18... 16) : configurable by the coding wheel (REG1). Bits (15..8): select addressing FPGA

0x00 to 0x0F VMEFpga 0x10 to 0x13 CTRLFpga 0x14 to 0x17 D1Fpga 0x18 to 0x1B D2Fpga 0x1C to 0x1F D3Fpga



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5. Registers

5.1. Register addresses Addressing: VMEFpga register (15 ..0) Register: 0x0000 Full Reset WO: full reset of Trigger Crate Register: 0x0004 Partial Reset WO: partial reset of Trigger Crate (empty FIFO's, clear scalars) Register: 0x000C FWRevision RO: FPGA ID and Firmware revision Addressing: Ctrl_Fpga register (15 ..0) Register: 0x1000 FullReset WO: full reset of Trigger Crate Register: 0x1004 PartialReset WO: partial reset of Trigger Crate (empty FIFO's, clear scalars) Register: 0x1008 SoftwareTrigger WO: software trigger Register: 0x100C FWRevision RO: FPGA ID and Firmware revision Register: 0x1020 FWDatestamp RO: Firmware revision date Register: 0x1024 GlobalThreshold 20 bits global threshold Register: 0x1028 GateWidth (GateWidth+1)*5ns = actual gate width Register: 0x102C GateDelay Delay in 5ns steps Register: 0x1030 RequireCluster 0 = require global threshold only 1 = require cluster + global threshold Register: 0x1034 HRSSinglesMode



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0 = (S0 and S1) or (S0 and s2m) or (S0 and Cer) or (S1 and S2m ) or (S1 and cer) or (s2m and cer) 1 = (S0 and S1) or (S0 and s2m) or (S1 and S2m) 2-3 = 0 Register: 0x1038 HRSTriggerMode 0 = prescaled(s2m and not Cer) or s2m and Cer 1-3 = 0 Register: 0x103C S2mANDnCerPrescale 16bit Prescale factor: N+1 Register: 0x1040 TrigClkPrescale 16bit Prescale factor: N+1 Register: 0x1080 FIFOEventData : RO: 156 words of 32 bits See the table of the data event structure paragraph 5-3 Register 0x1084 : FIFOStatus bits [10:0] - Number of 32bit words in FIFO bit 11 - FIFO full flag bit 12 - FIFO empty flag Addressing : Data_Fpga register (15 ..0) Register 0x1510 : D1_ClusterThreshold 16 bits Cluster Threshold Register 0x1910 : D2_ClusterThreshold; 16 bits Cluster Threshold Register 0x1D10 : D3_ClusterThreshold; 16 bits Cluster Threshold Register: 0x1100 FIFOEventData in BLT MODE read only RO: 156 words of 32 bits See the table of the data event structure paragraph 5-3



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5.2. Equations ( defini dans le code ) of output LEMO MasterOr <= trigclkN or Cosmic or HRSSingle or vme_trig or HRSTrig; MasterOrTrig <= trigclkN or Cosmic or HRSSingle or vme_trig or HRSTrig; HRSSingle => 2 equations possibles (« 0 » par defaut ) 0 => (S0 and S1)or (S0 and s2m)or (S0 and Cer)or (S1 and S2m ) or (S1 and cer) or(s2m and cer); 1 => (S0 and S1)or (S0 and s2m)or (S1 and S2m ); HRSTrig <= (scales2m and (not Cer)) or (s2m and Cer) ARS_STOP <= MasterOr and TS_live



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5.3. Reading register FIFOEventData data order reg0x1080 more details or by BLT at the reg 0x1100

1 0xAAAAAAAA 2 CptCosmic 3 CptClock 4 CptS0 5 CptS1 6 CptS2m 7 CptCer 8 CptCosmic_Live 9 CptClock_Live

10 CptS0_Live 11 CptS1_Live 12 CptS2m_Live 13 CptCer_Live 14 CptARSStop 15 CptARSValid 16 CptMasterOrTrig 17 CptClkN 18 CptHRSSingle 19 CptHRSTrig 20 CptScaleS2m 21 CptS2mANDCer 22 CptS2mANDCer_Live 23 CptMasterOr 24 CptClk25MHz(31 downto 0) 25 x"000000" & CptClk25MHz(39 downto 32) 26 CptClk25MHz_Live(31 downto 0) 27 x"000000" & CptClk25MHz_Live(39 downto 32) 28 CptL1A 29 ClusterFound & "00000" & TRIGPATTERN_Q & GlobalSum 30 0x00000000 31 0x00000000 32 0x00000000 33 0x00000000

105 to 34 0x"0" & Odd data (12 bits) & 0x"0" & pair data (12 bits) 72 words 113 to 106 8 words with 0X03FF03FF 144 to 114 0x"0" & Odd data (12 bits) & 0x"0" & pair data (12 bits) 32 words 153 to 145 8 words with 0X03FF03FF



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6. ANNEXES

6.1. Typical trigger signals

1 - trigger cosmic 2 - Analog input signal (example channel 16) 3 - gate for integrated signal 4 - analog integrated signal

Timing ARS_stop/ ARS_start /Gate /signal integer

1 –cosmic trigger 2 – Ars_stop 3 – Gate (left plot) - ARS_start (right) 4 - analog integrated signal



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6.2. JTAG daisy chain

6.2.1. for DATA_FPGAs ctrl_FPGA

Use the middle right jtag connector Same than the 2010 trigger version And put the sof or/and pof program in this order

Programming this chain in two times:

1- data1/ data2/ data3: this part of chain is already correctly program the memories work well.

2- Program sof of Dataf3/ triggerCtrl : the external memeories if trigger ctrl don’t work well and at each power on of the trigger you must do that don’t forgot to program in the same time the sof of the Data3 it’s help the triggerCtrl to program well



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6.2.2. For logic unit Use the high left jtag connector.

At each power on of the trigger you must program the sof of the LogicUnit

6.2.3. Verify which version is programming Look the 4 right led but the trigger must be program if it’s not the case the 4 led is lightly lighting The two left are for trigger ctrl The two righ are for the logic unit If all is off : you have verion V0 for the two FPGA If 0101 : V1 for the two fpga if it’s different reprogram the fpga witch have a bad led code.



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7. C test program

The vme_ctrl board is configure with high vme address 0x1E Be carefull the library used to make the file is the jlab library whith a LPC library

7.1. InitTrigger1E #include <stdio.h> #include <unistd.h> #include <errno.h> #include <sys/types.h> #include <sys/stat.h> #include <sys/ioctl.h> #include <fcntl.h> #include <stdlib.h> #include <unistd.h> #include <string.h> #include <linux/fs.h> #include <linux/types.h> #include "vme.h" #include "vme_user.h" #include "vmemap.h" //typedef unsigned long u64; typedef unsigned int u32; typedef unsigned short u16; typedef unsigned char u8; #define ARS_addr 0x1f0000 #define ARS_addr2 0x1e0000 #define VmeFullReset 0x0000 // WO: full reset of VME control board #define VmePartialReset 0x0004 // WO: partial of VME control board #define VmeFWRevision 0x0008 // RO: Firmware revision #define TriggFullReset 0x1000 // WO: full reset of Trigger Crate #define TriggPartialReset 0x1004 // WO: partial reset of Trigger Crate (empty FIFO's, clear scalars) #define TriggSoftwareTrigger 0x1008 // WO: software trigger #define TriggFWRevision 0x100C // RO: FPGA ID and Firmware revision #define FWDatestamp 0x1020 // RO: Firmware revision date #define GlobalThreshold 0x1024 // 20bit global threshold #define D1ClusterThreshold 0x1540 #define D2ClusterThreshold 0x1940 #define D3ClusterThreshold 0x1d40



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#define GateWidth 0x1028 // (GateWidth+1)*5ns = actual gate width #define GateDelay 0x102C // Delay in 5ns steps #define RequireCluster 0x1030 // 0 = require global threshold only // 1 = require cluster + global threshold #define HRSSinglesMode 0x1034 // 0 = (S0 and S1) or (S0 and s2m) or (S0 and Cer) or (S1 and S2m ) or (S1 and cer) or (s2m and cer) // 1 = (S0 and S1) or (S0 and s2m) or (S1 and S2m) // 2-3 = 0 #define HRSTriggerMode 0x1038 // 0 = prescaled(s2m and not Cer) or s2m and Cer // 1-3 = 0 #define S2mANDnCerPrescale 0x103C // 16bit Prescale factor: N+1 #define TrigClkPrescale 0x1040 // 16bit Prescale factor: N+1 #define FIFOEventData 0x1080 // sizeof(ARSEventDataStruct) / 4 words per event #define FIFOStatus 0x1084 // bits [10:0] Number of 32bit words in FIFO // bit 11 FIFO full flag // bit 12 FIFO empty flag #define CptCosmic 0x1100 #define CptClock 0x1104 #define CptS0 0x1108 #define CptS1 0x110C #define CptS2m 0x1110 #define CptCer 0x1114 #define CptARSStop 0x1118 #define CptARSregid 0x111C #define CptMasterOrTrig 0x1120 #define CptClkN 0x1124 #define CptHRSSingle 0x1128 #define CptHRSTrig 0x112C #define CptScaleS2m 0x1130 #define CptS2mANDCer 0x1134 #define CptMasterOr 0x1138 #define CptL1A 0x113C int main(void) { u32 reg; u32 pReg[4096]; int i;



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//struct vme_master master; printf("Test Driver vme\n"); /*----------------------------------------------------------------*/ /* Ouverture des fenetres VME */ /*----------------------------------------------------------------*/ OpenJlabWindows(); VmeMap *pVmeDRS1 = new VmeMap(ARS_addr2,0x1000000,VME_A24,0x39,VME_D32); //A24 D16 if (!pVmeDRS1->GetMap()) {printf("erreur ouverture\n");return(-1);} // test si l'ouverture est correcte /*----------------------------------------------------------------*/ /* init */ /*----------------------------------------------------------------*/ printf("******************debut************************\n"); //*********************************************************** /* printf("ADRESSE de base :"); scanf ("%x", &AddrTrigger); Addrtrigg = AddrTrigger * 0x10000; printf("ADRESSE=%p",Addrtrigg); printf("\n");*/ printf("******************init************************\n"); //*********************************************************** pVmeDRS1->Write((u32)0x1, VmeFullReset); //pVmeDRS1->Read(&reg, FullReset); pVmeDRS1->Write((u32)0x0, TriggFullReset); //pVmeDRS1->Read(&reg, ConfArs); pVmeDRS1->Write((u32)200, GlobalThreshold); pVmeDRS1->Read(&reg, GlobalThreshold); printf("GlobalThreshold =%x\n",reg); pVmeDRS1->Write((u32) 15, GateWidth); pVmeDRS1->Read(&reg, GateWidth); printf("GateWidth =%x\n",reg); pVmeDRS1->Write((u32) 10, GateDelay); pVmeDRS1->Read(&reg, GateDelay ); printf("GateDelay =%x\n ",reg); pVmeDRS1->Write((u32) 0, RequireCluster); pVmeDRS1->Read(&reg, RequireCluster); printf("RequireCluster =%x\n",reg); pVmeDRS1->Write((u32) 0, HRSSinglesMode); pVmeDRS1->Read(&reg, HRSSinglesMode); printf("HRSSinglesMode =%x\n",reg); pVmeDRS1->Write((u32) 0x0, HRSTriggerMode); pVmeDRS1->Read(&reg, HRSTriggerMode); printf("HRSTriggerMode =%x\n",reg); pVmeDRS1->Write((u32) 0, S2mANDnCerPrescale); pVmeDRS1->Read(&reg, S2mANDnCerPrescale); printf("S2mANDnCerPrescale =%x\n",reg); pVmeDRS1->Write((u32) 2, TrigClkPrescale); pVmeDRS1->Read(&reg, TrigClkPrescale); printf("TrigClkPrescale =%x\n",reg); pVmeDRS1->Write((u32) 0x40, D1ClusterThreshold); pVmeDRS1->Read(&reg, D1ClusterThreshold); printf("D1ClusterThreshold =%x\n",reg);



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pVmeDRS1->Write((u32) 0x40, D2ClusterThreshold); pVmeDRS1->Read(&reg, D2ClusterThreshold); printf("D2ClusterThreshold =%x\n",reg); pVmeDRS1->Write((u32) 0x40, D3ClusterThreshold); pVmeDRS1->Read(&reg, D3ClusterThreshold); printf("D3ClusterThreshold =%x\n",reg); u32 pd_2ch =0x8108100; for (i=0; i<32; i++) { int addrpied = 2*i + 0x1500; pVmeDRS1->Read(&reg, addrpied);printf("= %x",reg); } for (i=0; i<32; i++) { int addrpied = 2*i + 0x1900; pVmeDRS1->Read(&reg, addrpied);printf("= %x",reg); } for (i=0; i<32; i++) { int addrpied = 2*i + 0x1d00; pVmeDRS1->Read(&reg, addrpied);printf("= %x",reg); } printf("\n\n\n"); // config piedestaux-- eteint principalement les voies //fpga1 /* for (i=0; i<80; i++) { u32 pd_2ch1 =pd_2ch +i ; int addrpied = 1*i + 0x1400; pVmeDRS1->Write((u32)pd_2ch1, addrpied); pVmeDRS1->Read(&reg, addrpied);printf(" %x",reg); } //fpga2 for (i=0; i<80; i++) { int addrpied = 8*i + 0x1800; printf("valeur de addr = 0x%x",addrpied); pVmeDRS1->Write((u32)pd_2ch, addrpied); pVmeDRS1->Read(&reg, addrpied); printf(" valeur de addrpied =%x\n",reg); } //fpga3 for (i=0; i<80; i++) { int addrpied = 4*i + 0x1C00; printf("valeur de addr = 0x%x",addrpied); pVmeDRS1->Write((u32)pd_2ch, addrpied); pVmeDRS1->Read(&reg, addrpied);printf(" valeur de addrpied =%x\n",reg);



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}*/ //-------------------------------------------------------------------- printf("\n\n\n"); printf("fin\n"); printf("\n\n\n"); /*----------------------------------------------------------------*/ /* Fermeture des fenetres VME S */ /*----------------------------------------------------------------*/ if (pVmeDRS1) delete(pVmeDRS1); CloseJlabWindows(); return 0; }

7.2. Read_1E #include <stdio.h> #include <unistd.h> #include <errno.h> #include <sys/types.h> #include <sys/stat.h> #include <sys/ioctl.h> #include <fcntl.h> #include <stdlib.h> #include <unistd.h> #include <string.h> #include <linux/fs.h> #include <linux/types.h> #include "vme.h" #include "vme_user.h" #include "vmemap.h" //typedef unsigned long u64; typedef unsigned int u32; typedef unsigned short u16; typedef unsigned char u8; #define ARS_addr 0x1f0000 #define ARS_addr2 0x1e0000 #define Trigg_1E 0x1e0000 #define FifoStatus 0x84 #define FIFOEventData 0x1080 #define CptCosmic 0x1100 #define TriggFullReset 0x1000 // WO: full reset of Trigger Crate #define TriggPartialReset 0x1004 // WO: partial reset of Trigger Crate (empty FIFO's, clear scalars)



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#define FIFOEventData 0x1080 // sizeof(ARSEventDataStruct) / 4 words per event #define FIFOStatus 0x1084 // bits [10:0] Number of 32bit words in FIFO // bit 11 FIFO full flag // bit 12 FIFO empty flag #define VmePartialReset 0x1004 // WO: partial of VME control board int main(void) { u32 reg; u32 pReg[4096]; unsigned int *laddr; int i,j,z; unsigned int val1 =0x0000000; unsigned int val ; int AddrTrigger, Addrtrigg; //struct vme_master master; printf("Test Driver vme\n"); /*----------------------------------------------------------------*/ /* Ouverture des fenetres VME */ /*----------------------------------------------------------------*/ OpenJlabWindows(); VmeMap *pVmeDRS1 = new VmeMap(ARS_addr2,0x1000000,VME_A24,0x39,VME_D32); //A24 D16 if (!pVmeDRS1->GetMap()) {printf("erreur ouverture\n");return(-1);} // test si l'ouverture est correcte /*----------------------------------------------------------------*/ /* init */ /*----------------------------------------------------------------*/ printf("******************debut************************\n"); printf("******************init************************\n"); //*********************************************************** //write init ars pVmeDRS1->Write((u32)0x1, TriggPartialReset); //pVmeDRS1->Read(&reg, FullReset); for (j=0; j<5000; j++) { while(val1 < 0x00000001) {



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pVmeDRS1->Read(&val, FIFOStatus); val1= val & 0x00000001; // printf(" / DATA=%x",val); printf("/ DATA=%x\n",val1); for (z =0; z<500 ; z++) { pVmeDRS1->Read(&val, FIFOStatus); } } printf("\n"); printf("****************sortie de boucle*********************\n"); printf("ADRESSE=%p",(FIFOStatus*4)); printf(" / DATA=%x",val); printf("/ DATA=%x\n",val1); // readout et display printf("****************INFO TRIGGER*********************\n"); pVmeDRS1->Read(&val,FIFOEventData); printf("Header: 0x%08X\n", val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptCosmic=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptClock=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptS0=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptS1=%x\n",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptS2m=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptCer=%x\n",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptCosmic_Live=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptClock_Live=%x\n",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptS0_Live=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptS1_Live=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptS2m_Live=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptCer_Live=%x\n",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptARSStop=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptARSValid=%x\n",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptMasterOrTrig=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptClkN=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptHRSSingle=%x\n",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptHRSTrig=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptScaleS2m=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptS2mANDCer=%x\n",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptS2mANDCer_Live=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptMasterOr=%x\n",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptClk25MHz0=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptClk25MHz1=%x\n",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptClk25MHz_Live0=%x",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptClk25MHz_Live1=%x\n",val); pVmeDRS1->Read(&val,FIFOEventData); printf(" / CptL1A=%x",val);



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pVmeDRS1->Read(&val, FIFOEventData); ; printf(" / mot non decomposé=%x\n",val); printf("****************DONNEES TRIGGER*********************\n"); int globalsum = val & 0x000fffff ; printf(" / GlobalSum=%x",globalsum); int TrigPattern = (val & 0x03f00000)>> 20; printf(" / TrigPattern=%x",TrigPattern); int ClusterFound = (val & 0x80000000)>> 31; printf(" / ClusterFound =%x\n",ClusterFound); int x, y; unsigned sum,sum1,summreal; unsigned int valLow, valHigh; for(x = 0; x < 4; x++) //suppression de ;ots de zero { pVmeDRS1->Read(&val, FIFOEventData); //printf("--%8x",val); // printf("\n"); } sum =0x00000000; for(y = 14 ;y >= 0; y--) { for(x = 0; x < 8; x++) { pVmeDRS1->Read(&val, FIFOEventData); valLow = (val & 0x00000fff);valHigh = (val & 0xfff0000)>>16 ; sum = valLow + valHigh + sum; printf("-%3x",valHigh);printf("-%3x",valLow); } // printf("-%8x",sum); sum = sum; printf("\n"); } summreal =sum -(32*0x7ff); printf("\n"); //printf("sum = %8x\n",sum); //printf("sum1 = %8x\n",sum1); printf("summreal = %8x\n",summreal ); printf("\n"); for (i=0; i<25; i++) { pVmeDRS1->Read(&val, FIFOEventData); // printf(" %8x",val); } while(val1 = 0x00000000)



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{ pVmeDRS1->Read(&val, FIFOStatus); val1= val & 0x00000001; // printf(" %8x",val1); } } //-------------------------------------------------------------------- printf("\n\n\n"); printf("fin\n"); printf("\n\n\n"); /*----------------------------------------------------------------*/ /* Fermeture des fenetres VME */ /*----------------------------------------------------------------*/ if (pVmeDRS1) delete(pVmeDRS1); CloseJlabWindows(); return 0; }

7.3. READ1E_BLT.C drivers Clermont #include <stdio.h> #include <stdio.h> #include <unistd.h> #include <errno.h> #include <sys/types.h> #include <sys/stat.h> #include <sys/ioctl.h> #include <fcntl.h> #include <stdlib.h> #include <unistd.h> #include <string.h> #include <linux/fs.h> #include <linux/types.h> #include <arpa/inet.h> #include "vme.h" #include "vme_user.h" #include "vmemap.h" #ifndef UTYPES_H #define UTYPES_H #include <stdint.h> typedef uint64_t u64; typedef uint32_t u32; typedef uint16_t u16; typedef uint8_t u8; #endif



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extern u32 *dma_dabufp; #define DRS1 0x1E0000 #define Trigg_1E 0x1e0000 #define FIFOEventData 0x1080 #define TriggFullReset 0x1000 // WO: full reset of Trigger Crate #define TriggPartialReset 0x1004 // WO: partial reset of Trigger Crate (empty FIFO's, clear scalars) #define FIFOEventData 0x1080 // sizeof(ARSEventDataStruct) / 4 words per event #define FIFOStatus 0x1084 // bits [10:0] Number of 32bit words in FIFO // bit 11 FIFO full flag // bit 12 FIFO empty flag VmeMap *pVmeDRS1; unsigned int *Buffer ; int main(void) { u32 reg; u32 pReg[4096]; u32 nbrEch,toto; u32 val1, val; //struct vme_master master; printf("Test Driver vme\n"); /*----------------------------------------------------------------*/ /* Ouverture des fenetres VME */ /*----------------------------------------------------------------*/ OpenJlabWindows(); pVmeDRS1 = new VmeMap(DRS1,0x1000000,VME_A24,0x39,VME_D32); //A24 D161 if (!pVmeDRS1->GetMap()) {printf("erreur ouverture\n");return(-1);} // test si l'ouverture est correcte //*** blt pVmeDRS1->InitBlt(10240,1,2,0); //**************************************************************** //************************************************************************* u32 evt_id; int nb; // parametre de lecture nb = 2; nbrEch = 190; FILE *p_fichier; /* pointeur sur FILE */ char FICHIER[30], NOM_FICHIER[30], NOM_PERS[30]; int C,NB_ENREG;



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// Créer et remplir le fichier * //printf("Entrez le nom du fichier à créer : "); scanf("%s", FICHIER); printf("\n"); pVmeDRS1->Write((u32)0x1,0x1004); // reset partiel pVmeDRS1->Read(&val, 0x1024); //fifostausglobal sum printf(" / DATA=%x\n",val); printf("\n"); for (int j=0; j<5000; j++) { while(val1 < 0x00000001) { pVmeDRS1->Read(&val, 0x1084); //fifostaus val1= val & 0x00000001; } printf("\n"); printf("****************fifo status ok*********************\n"); printf("ADRESSE=%p",(0x1084)); printf(" / DATA=%x",val); printf("/ DATA=%x\n",val1); printf("***-----debut lecture blt-----*\n"); int i; int AddrBlt = 0x1100; int nbrEch = 156; u32 word[1024]; pVmeDRS1->ReadBlt(Buffer,(nbrEch),(DRS1 + AddrBlt)); //***display**********************// // remise en fornme des donnees //******************************** for ( unsigned int x = 0 ; x< (nbrEch) ;x++) { dma_dabufp[x] = ((dma_dabufp[x]& 0xff000000) >>24) + ((dma_dabufp[x]&0x00ff0000) >> 8)+((dma_dabufp[x]&0x0000ff00) << 8) + ((dma_dabufp[x]&0xff) <<24); // printf(" %d",x ); printf("%8x\n",dma_dabufp[x] ); } printf("\n"); printf("***-----fin lecture blt-----*\n"); //--------------------------------------------------- printf("\n"); // for (int i=0; i<25; i++)



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// { // pVmeDRS1->Read(&val, 0x1080); //fifoevent data // printf(" %8x",val); // } while(val1 = 0x00000000) { pVmeDRS1->Read(&val,0x1084);//fifostatus val1= val & 0x00000001; // printf(" %8x",val1); } } //***********fermeture process**************************************************** printf("\n\n\n"); printf("fin\n"); printf("\n\n\n"); /*----------------------------------------------------------------*/ /* Fermeture des fenetres VME */ /*----------------------------------------------------------------*/ delete(pVmeDRS1); CloseJlabWindows(); return 0;



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8. Trouble shooting: Problems can occur:

8.1. JTAG Chain 1 and 2 don’t works Verify the two fuse of 3.3 V and 5 V (see picture) If it’s bad : change it (little fuse 5 or 7 A old resistor format) The fuse are soldering on the front top side of the board but you can test it on the bottom side .

- Open the power supply door - And check if you you have power at th two pin of each fuse.

The fuse are just under the last orange connector.

- If the fused are good check all the others fuses of the boards. If all are ok : i don’t know where the problems come from. If the fuses are BAD look the next procedure to extract the mother board. 9 Put the trigger off

9 REMOVE THE SCREW OF THE FRONT PANEL

Fuses need to be tested



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9 Un plugged one by one the daughter board but take care of the 3 righ boards( all the boards with jytag connector / and inputs/outputs logic signal)

9 When you have finich to unplugged analog boards : un plugged the

last board whith extractor .

9 Unplugged the low board.

9 To unplugged the high board do the last thing in this order :

9 Now you can unplugged the board 9 Extract the screws of the boards( uo to 36) 9 Take care of don’t lost the plastic bar under the board 9 Change the fuse and redo the thing in the other way … good luck

…

Programming information:

Lok and be very carrefull with this connector



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9. Measure in Electronic test Lab

9.1. Timing of reading an event with the VME_STD protocol at the register: x1080

Around: 520 us

9.2. Timing of reading an event with the VME_BLT protocol at the register: x1100

Around: 100 us Result: you wind a coefficient 5 on the data acquisition.

DVCS Calorimeter Trigger Version 2014 ---- Technical...

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