Dual Scalable 500 MS/s, 5b Time- Interleaved SAR ADCs for ...€¦ · SAR energy dominated by...
Transcript of Dual Scalable 500 MS/s, 5b Time- Interleaved SAR ADCs for ...€¦ · SAR energy dominated by...
-
Dua
l Sca
labl
e 50
0 M
S/s
, 5b
Tim
e-In
terle
aved
SA
R A
DC
s fo
r UW
B
App
licat
ions
Dua
l Sca
labl
e 50
0 M
S/s
, 5b
Tim
e-In
terle
aved
SA
R A
DC
s fo
r UW
B
App
licat
ions
Bria
n P
. Gin
sbur
g, A
nant
haP
. Cha
ndra
kasa
n
Cus
tom
Inte
grat
ed C
ircui
ts C
onfe
renc
eS
an J
ose,
Cal
iforn
iaS
epte
mbe
r 20,
200
5
The
MIT
Ultr
a-W
ideb
and
Pro
ject
–ht
tp://
ww
w-m
tl.m
it.ed
u/re
sear
chgr
oups
/icsy
stem
s/uw
b/
-
Out
line
Out
line
•U
ltra-
Wid
eban
d R
adio
•A
DC
Arc
hite
ctur
e•
Circ
uit I
mpl
emen
tatio
n•
Mea
sure
d R
esul
ts•
Con
clus
ion
-
Ultr
a-W
ideb
and
Rad
io O
verv
iew
Ultr
a-W
ideb
and
Rad
io O
verv
iew
•IE
EE
802
.15.
3a is
dev
elop
ing
a hi
gh d
ata
rate
(≥48
0Mb/
s)
UW
B fo
r PA
N.
•Bot
h O
FDM
and
pul
se-b
ased
so
lutio
ns a
re p
ropo
sed.
FCC
Spe
cific
atio
ns
•>50
0MH
z 10
dB b
andw
idth
•Ver
y lo
w a
vera
ge p
ower
de
nsity
(see
mas
k at
righ
t)
FCC
Spe
ctru
m M
ask
and
14-C
hann
el
Freq
uenc
y P
lan
-
UW
B R
ecei
ver D
esig
nU
WB
Rec
eive
r Des
ign
•50
0MS
/s fo
r Nyq
uist
sam
plin
g of
min
imum
ban
dwid
th R
F si
gnal
s•
5 bi
t res
olut
ion
suffi
cien
t for
pro
per r
ecep
tion;
few
er b
its p
ossi
ble
unde
r fav
orab
le c
hann
el c
ondi
tions
•G
oal:
min
imiz
e po
wer
dis
sipa
tion
•P
aral
lel i
nter
face
to re
lax
I/O re
quire
men
ts a
nd p
rovi
de p
aral
lel d
ata
to b
ack-
end
I Q
LNA
Dig
ital
Bac
k-E
nd
AD
C
AD
C
Syn
ch
[F.S
. Lee
, CIC
C 2
005]
-
AD
C A
rchi
tect
ure
Sel
ectio
nA
DC
Arc
hite
ctur
e S
elec
tion
•Fl
ash
mos
t com
mon
but
re
quire
2b -
1 co
mpa
rison
s pe
r sa
mpl
e•
[Dra
xelm
ayr,
ISS
CC
200
4]
6b, 6
00M
S/s
tim
e-in
terle
aved
su
cces
sive
app
roxi
mat
ion
regi
ster
(SA
R)
•S
AR
cha
ract
eris
tics:
–b
com
paris
ons
–C
ompa
rato
rs h
ave
sam
e sp
eed/
accu
racy
re
quire
men
ts a
s fla
sh–
6 pe
riods
to re
solv
e ou
tput
–D
igita
l and
cap
acito
r arr
ay
switc
hing
ove
rhea
dSA
R e
nerg
y do
min
ated
by
digi
tal
logi
c at
low
reso
lutio
ns a
nd
com
para
tors
at m
ediu
m re
solu
tion
-
Tim
e-In
terle
aved
SA
R A
DC
Tim
e-In
terle
aved
SA
R A
DC
•Si
ngle
500
MH
z cl
ock
from
on-
chip
VC
O o
r ext
erna
l sou
rce
•6
perio
ds p
er c
onve
rsio
n at
nom
inal
reso
lutio
n•
Sta
rt si
gnal
s sh
ared
bet
wee
n I a
nd Q
AD
Cs
for s
ynch
roni
zatio
n
Slic
e 0
star
tne
xt ENDout
Vin
y[0]
Slic
e 1
star
tne
xt ENDout
Vin
y[1]
Slic
e 2
star
tne
xt ENDout
Vin
y[2]
Slic
e 3
star
tne
xt ENDout
Vin
y[3]
Slic
e 4
star
tne
xt ENDout
Viny[
4]
Slic
e 5
star
tne
xt ENDout
Vin
y[5]
Sta
rtG
enVIN
CLK
bit-s
calin
g co
ntro
ller
b
Pre
sent
s ~1
pF c
apac
itive
lo
ad (w
ith p
aras
itics
)O
utpu
ts s
orte
d to
mai
ntai
n co
nsta
nt
time
orde
ring
at c
hip
inte
rface
-
Bit
Sca
ling
Bit
Sca
ling
•S
= s
ampl
e•
BC =
bit-
cycl
e•
Off
= G
ate
STA
RT
and
CLK
sign
als,
po
wer
dow
n pr
eam
plifi
ers
•Sc
alab
le d
own
to
1 bi
t
654321
Tim
e P
er.
SB
C 1
BC
2B
C 3
BC
4B
C 5
BC
5S
BC
1B
C 2
BC
3B
C 4
BC
4B
C 5
SB
C 1
BC
2B
C 3
BC
3B
C 4
BC
5S
BC
1B
C 2
BC
2B
C 3
BC
4B
C 5
SB
C 1
BC
1B
C 2
BC
3B
C 4
BC
5S
SL5
SL4
SL3
SL2
SL1
SL0
4321
Tim
e P
er.
Off
Off
SB
C 1
BC
2B
C 3
Off
Off
BC
3S
BC
1B
C 2
Off
Off
BC
2B
C 3
SB
C 1
Off
Off
BC
1B
C 2
BC
3S
SL5
SL4
SL3
SL2
SL1
SL0
Gen
erat
ing
the
STA
RT
sign
al fo
r the
firs
t slic
e of
eac
h A
DC
fa
ster
aut
omat
ical
ly re
sets
bit-
cycl
ing
and
latc
hes
outp
uts
at
the
appr
opria
te ti
me.
3 bi
ts
5 bi
ts
-
Slic
e Im
plem
enta
tion
Slic
e Im
plem
enta
tion
auto
zero
clk
LL
SA
R lo
gic
and
cont
rol
CO
MP
DO
NE
NEX
TST
AR
T
CLK
V IN
V REF
S 0–S
5
Y 0–Y
4
Pol
y-po
lyca
paci
tors
Sel
f-Tim
edB
it-cy
clin
g
Fully
Diff
eren
tial
Full
cust
om
logi
c
Bia
s cu
rren
t du
ty-c
yclin
g in
pr
eam
plifi
ers
-
Pro
paga
tion
dela
y is
2·t c
k-q
from
risi
ng e
dge
of CLK
BC
SA
R L
ogic
and
Con
trol
SA
R L
ogic
and
Con
trol
S 4
DQ RST
SW0
DQ
SR1
L 4
S 3
DQ RST
SW1
DQ
SR2
L 3
S 2
DQ RST
SW2
DQ
SR3
L 2
S 1
DQ RST
SW3
DQ
SR4
L 1
S 0
DQ RST
SW4
DQ
SR5
L 0D
QSR
0
DQ
SR' 0
STA
RT
CO
MP
CLK
BC
Sam
ple
Gen
SAM
P
NEX
T
CLK
Sta
ndar
d C
2 MO
S
regi
ster
s w
ith
enab
le
C2 M
OS
regi
ster
s w
ith
enab
le a
nd s
ynch
rono
us
rese
t
Sw
itch
driv
e re
gist
er is
sin
gle
gate
impl
emen
ting
com
plex
logi
c fu
nctio
n to
driv
e ca
paci
tor a
rray
(S0-
S4)
Gen
erat
es s
ampl
e an
d au
toze
roin
gsi
gnal
s to
m
inim
ize
corr
uptio
n of
st
ored
cha
rge
on
capa
cito
r arra
y
-
Cus
tom
Sw
itch
Driv
e R
egis
ter
Cus
tom
Sw
itch
Driv
e R
egis
ter
Pre
char
gea
to
avoi
d ch
arge
sh
arin
g ef
fect
s
Fast
cha
rge
path
upo
n ris
ing
edge
of L
i
C2 M
OS
latc
h Det
erm
inis
tic n
atur
e of
SA
R a
lgor
ithm
allo
ws
sim
plifi
ed g
ate
desi
gns
beca
use
not a
ll in
put s
igna
l com
bina
tions
are
pos
sibl
e.
58%
fast
er a
nd 8
0% lo
wer
tota
l di
gita
l pow
er th
an s
tand
ard
cell
impl
emen
tatio
n
DQ RST
SW1
L i
CO
MP
SAMPS i
-
Tim
e-B
orro
win
gTi
me-
Bor
row
ing
•D
igita
l fee
dbac
k be
twee
n ea
ch
bit-c
ycle
•U
se s
elf-t
imed
bit-
cycl
ing
[Pro
mitz
er, J
SS
C 2
001]
•E
xten
ds p
erio
d fo
r ana
log
settl
ing →
redu
ced
bias
cu
rrent
s•
Det
erm
inis
tic n
atur
e of
SA
R
sign
als
forc
es a
larg
e in
put
(fast
set
tling
tim
e) to
follo
w a
sm
all o
ne (c
hanc
e of
m
etas
tabi
lity)
•Jo
int d
esig
n of
the
timin
g be
twee
n an
alog
and
dig
ital
sect
ions
.
12
3
Sel
f-Tim
ed
Met
asta
ble
-
Com
para
tor D
esig
n an
d S
chem
atic
sC
ompa
rato
r Des
ign
and
Sch
emat
ics
Sim
ple
stru
ctur
e al
low
s hi
gh s
peed
op
erat
ion
with
low
vo
ltage
(1–1
.2V
)
Pre
ampl
ifier
s on
ly o
n w
hen
activ
ely
need
ed
[Mon
tana
ro96
]
Dig
ital s
uppl
y
-
Die
Pho
toD
ie P
hoto
•N
atio
nal S
emic
ondu
ctor
0.
18µm
CM
OS
pro
cess
•To
tal a
rea:
2.3
mm
x
2.4m
m•
Activ
e ar
ea p
er A
DC
: 0.
5mm
x 1
mm
•C
hip
also
incl
udes
re
fere
nce
volta
ge b
uffe
r, V
CO
, and
ext
erna
l clo
ck
chai
n.
AD
C I
AD
C Q
-
Sta
tic P
erfo
rman
ceS
tatic
Per
form
ance
500
MS
ampl
e/s
oper
atio
n
Ana
log
VD
D: 1
.2V
nom
inal
Dig
ital V
DD: 1
.8V
nom
inal
7.8m
W m
ax p
ower
per
AD
C,
excl
udin
g I/O
Full
scal
e in
put:
200-
400m
V
sing
le-e
nded
Dut
y cy
clin
g re
duce
s an
alog
po
wer
by
15%
Typi
cal r
esul
ts
-
Dyn
amic
Per
form
ance
Dyn
amic
Per
form
ance
•Per
iodi
c be
havi
or ↔
Insu
ffici
ent t
ime
for s
ampl
ing
•Dyn
amic
test
s us
e ex
tern
al, l
ow ji
tter c
lock
•Offs
et a
nd ti
min
g m
ism
atch
bet
wee
n sl
ices
not
lim
itatio
n of
per
form
ance
Sig
nal-t
o-no
ise-
plus
-dis
torti
on ra
tioFF
T of
170
.56M
Hz
inpu
t sa
mpl
ed a
t 500
MH
z
-
Tim
e In
terle
avin
g P
erfo
rman
ceTi
me
Inte
rleav
ing
Per
form
ance
Sta
tic p
erfo
rman
ce te
stin
g av
erag
es u
ncor
rela
ted
erro
rs; d
ynam
icpe
rform
ance
is
dom
inat
ed b
y w
orst
cas
e sl
ice.
Bes
t and
wor
st s
lice
INLs
-
Con
clus
ions
Con
clus
ions
•P
aral
lelis
m e
nabl
es g
reat
er a
rchi
tect
ural
flex
ibili
ty.
•S
AR
arc
hite
ctur
e no
t lim
ited
to o
nly
low
spe
ed
conv
erte
rs.
•S
elf-t
imin
g, a
tech
niqu
e w
ell k
now
n in
dig
ital,
can
also
eas
e cr
itica
l pat
h co
nstra
ints
and
pow
er in
an
alog
.•
Dig
ital p
ower
and
com
plex
ity c
anno
t be
igno
red
in
high
-spe
ed m
ixed
sig
nal c
ircui
ts.
-
Ack
now
ledg
men
tsA
ckno
wle
dgm
ents
•N
atio
nal S
cien
ce F
ound
atio
n•
HP
-MIT
Alli
ance
•N
DS
EG
Fel
low
ship
•N
atio
nal S
emic
ondu
ctor
for c
hip
fabr
icat
ion