DT Track Finder, Global Muon Trigger, Global Trigger H. Bergauer, L. Boldizsar, M. Dallavalle, Ch....

DT Track Finder, DT Track Finder, Global Muon Trigger,Global Muon Trigger,

Global TriggerGlobal TriggerH. Bergauer, L. Boldizsar, M. Dallavalle, Ch. Deldicque, J. Erö, H. Bergauer, L. Boldizsar, M. Dallavalle, Ch. Deldicque, J. Erö, L. Guiducci, A. Jeitler, I. Jimenez Alfaro , P. Hidas, K. Kastner, L. Guiducci, A. Jeitler, I. Jimenez Alfaro , P. Hidas, K. Kastner,

S. Kostner, A. Montanari,A. Nentchev, B. Neuherz, N. S. Kostner, A. Montanari,A. Nentchev, B. Neuherz, N. Neumeister, M. Padrta, Neumeister, M. Padrta,

G. Pellegrini, P. Porth, H. Rohringer, H. Sakulin, J. Strauss, G. Pellegrini, P. Porth, H. Rohringer, H. Sakulin, J. Strauss, A. Taurok, J. F. de Trocóniz, C.-E. WulzA. Taurok, J. F. de Trocóniz, C.-E. Wulz

Bologna, Budapest, Univ. Aut. Madrid and Vienna GroupsBologna, Budapest, Univ. Aut. Madrid and Vienna Groupspresented by

Claudia-Elisabeth WulzClaudia-Elisabeth WulzAnnual Review, CERN, 16 Sep 2003

C.-E. Wulz 2 Annual Review, Sep. 2003

Drift Tube Trigger Track FinderVienna, Madrid, Bologna

The Drift Tube Trigger Track Finder system (DTTF) consists of:

PHTF - Phi Track Finder Sector Processor (72 boards) - Vienna- new name (formerly called DTTF)ETTF - Eta Track Finder (12 boards) - Madrid, Vienna WS - Wedge Sorter (12 boards) - BolognaTIM - Timing Module (6 boards) - Vienna- same design as for Global TriggerDAQU - DAQ output unit (1+6 boards) - Vienna- muon data to be stored on tape by DAQ DT/CSC Transition Board (24 boards) - Vienna- information exchange between DT and CSCOutput Test Board (1 board) -Vienna- only for testing


Status of PHTF

- Function Evaluation Prototype ready• Long term tests performed• Tests with ORCA simulation data

– One bit error in one track segment (probably broken line in an internal layer)

– One assignment error– Clock phase control: 3 states instead of 5– Further investigations in progress

- Four additional PHTF boards are in production• Final adjustments were made to layout• Individual JTAG access added for each BGA chip (important for the initial phase)• PCB with better thermal parameters chosen


Matching patterns recalculated (2002) Number of patterns reduced by 25%: Fit neatly into two FPGAs

Pseudo-rapidity assignment:

Region covered goes from (-1.3, 1.3) to (-1.2,1.2) Assigned eta now in Station 2 to be consistent with RPC

Quality ordering revised (based on simulation)

Prefers one extra segment rather than a high-quality one But might be reconsidered according to June test beam results

New algorithm tested with ORCA_6 New reduced set of patterns slightly more efficient (91% to 93%)

Changes to the ETTF algorithm


VDHL model done and tested

High-statistics ORCA sample prepared to check VHDL model in event-by-event basis (will follow)

Board design ready, 2 boards in production

8 layers 2 big and 5 small FPGAs – fully reconfigurable (except the connections) same input connection as for PHTF

Integration test with PHTF will follow

Status of ETTF


ETTF board block diagram

ETTF-N

ETTF-P

InputSynch.

-2

InputSynch.

-1

InputSynch.

0

InputSynch.

+1

InputSynch.

+2

Outputdriver

21 bit hit21 bit quality




21 bit hit21 bit quality 7+7

7+7

7+7

2+2

1+1

7+7

7+7

2x3x6 bit Eta

2x3x6 bit Eta

Address of Tracks found by positive side PHTFs3x2x5 bit on Backplane

Address of Tracks found by negative side PHTFs3x2x5 bit on Backplane

4x3x6 bit Eta

To WedgeSorter

Optical Inputs


Status of Wedge Sorter (Bologna)

Board received in August. Description of functionality:http://montan.home.cern.ch/montan/DT_WedgeSorter_May2003.pdf

Almost finished preliminary electrical test (power, connections, etc).

Ready to start the first JTAG tests and preparing the test jig for a full functionality test by using Pattern Units.


Status of other DTTF boards

- DT/CSC Transition Board• Board ready, partly tested• FPGA with Range Correction LUT filled in by 1:1 mapping• Connection test next week

- Output Test Board- Board ready, participates in tests• Allows to read out DTTF results in real time with logic analyzer or Input Buffer Board• Plugged to the Wedge Sorter back side

– selectable PHTF output– GTL+ termination pluggable (remove when WS is in use)

- DAQ Output Board• first design steps made


DTTF Milestones and Schedule

DATE ITEM STATUS

May 2003: PHTF function evaluation prototype tested basically done June 2003: DT/CSC overlap test now: Sept. 2003* July 2004: PHTF pre-production prototype (PPP) done on schedule

* Dec. 2004: PHTF production done on schedule

June 2003: ETTF design done done Dec. 2003: ETTF boards produced on schedule

* Sep. 2003: DTTF prototype integration (PHTF,ETTF,WS) foreseen: Dec. 2003

* June 2003: Wedge Sorter prototype done ready for final tests* July 2004: Wedge Sorter production done on schedule

* Nov. 2003: Barrel Sorter prototype done now: Jan. 2004* July 2004: Barrel Sorter production done on schedule

(most recent milestone indicated by *)


Timing ModulePHTF Data source cardResult read back card

DTTF Test Crate (front)


Optical link emulator

Output Test Board DT/CSC Transition Board

DTTF Test Crate (rear)


Global Muon Trigger Overview

Output:Output:8 bit8 bit, 6 bit , 6 bit , 5 bit p, 5 bit pTT, ,

2 bits charge/synch, 3 bit 2 bits charge/synch, 3 bit quality,quality, MIP bit, Isolation bitMIP bit, Isolation bit

Output:Output:8 bit8 bit, 6 bit , 6 bit , 5 bit p, 5 bit pTT, ,

2 bits charge/synch, 3 bit 2 bits charge/synch, 3 bit quality,quality, MIP bit, Isolation bitMIP bit, Isolation bit

Inputs:Inputs:8 bit 8 bit , 6 bit , 6 bit , 5 bit p, 5 bit pTT, ,

2 bits charge, 3 bit quality,2 bits charge, 3 bit quality,1 bit halo/eta fine-coarse1 bit halo/eta fine-coarse

Inputs:Inputs:8 bit 8 bit , 6 bit , 6 bit , 5 bit p, 5 bit pTT, ,

2 bits charge, 3 bit quality,2 bits charge, 3 bit quality,1 bit halo/eta fine-coarse1 bit halo/eta fine-coarse

Best 4 Best 4

4 4 RPC brl RPC brl

4 4 DT DT

4 4 CSC CSC

4 4 RPC fwd RPC fwd

252 MIP bits252 Quiet bits


GMT in the Global Trigger Crate

Conceptual design readyFPGAs being designed

1 GMT Logic Board1 GMT Logic Board 3 Pipeline Sync. Boards3 Pipeline Sync. Boards

6-channel

prototype

available

4 DT/CSC + 8 RPC muonsGlobal Trigger CrateGlobal Trigger Crate

Special wide input board Special wide input board parallel to front panelparallel to front panel


GMT progress since September 2002

ÿ Development of FPGA firmwareÌ MIP & ISO Assignment FPGAs (completed)Ì Logic FPGAs (95% complete)

ÿ Development of tools for FPGA developmentÌ Framework for handling of look-up-tables in

ORCA C++ simulation and hardware modelÌ Automated testing

ÿ Updated ORCA simulation results (for DAQ TDR)ÿ Interface Document

Ì CMS/IN 2002/069: Bristol, RAL and Vienna groups: “CMS Level-1 GlobalCalorimeter Trigger to Global Trigger and Global Muon TriggerInterfaces“

ÿ PhD ThesisÌ H. Sakulin: “Design and Simulation of the First Level Global Muon

Trigger for the CMS Experiment at CERN”, TU Vienna, November 2002http://cmsdoc.cern.ch/documents/03/doc2003_005.pdf


FPGA Development for GMT

Cadence NCSIMCadence NCSIM

Cadence NCSIMCadence NCSIM

Xilinx ISE Xilinx ISE 5.2.03i5.2.03i

Synplify Synplify 7.37.3

VHDL VHDLVHDL

Behavioral simulationBehavioral simulation

Gate level simulationGate level simulation

Chip configurationChip configuration

VHDL for look-up tables generated byVHDL for look-up tables generated byLUT FrameworkLUT Framework from C++ from C++representationrepresentation

SynthesisSynthesis

ImplementationImplementation

Concurrent Versions SystemConcurrent Versions Systemto manage VHDL codeto manage VHDL code

CVS ServerCVS Server

““Build System”Build System”most of design flow most of design flow scripted with Makefilesscripted with Makefiles

Automated testsAutomated testsverify functionality after every changeverify functionality after every changecross-check with C++ simulationcross-check with C++ simulation

DeveloperDeveloper


MIP and ISO Assignment FPGA’s

• Xilinx XC2V3000– 432 chip inputs/outputs– 96/96 18 kbit memory blocks used

Developed VHDL model Simulated behavioral model &

cross-checked with ORCA (NC-SIM)

Synthesized using Synplify 7.21 Implemented with Xilinx ISE 5.2.03 Simulated chip-level VHDL &

cross-checked with ORCA (NC-SIM)

GMT Logic Board


Logic FPGA’s

• Xilinx XC2V3000– 464 chip inputs/outputs– 92/96 18 kbit memory blocks used

• Developing VHDL model – 95 % complete

Synthesized using Synplify 7.21 Implemented with Xilinx ISE 5.2.03

– 75% of chip resources used

• To be done– Complete VHDL model– Synthesize/Implement final version– Simulate gate level model

GMT Logic Board


Generic Handling of GMT Lookup-Tablesprojection, -conversion, sort-rank, merge-rank, …

Function calculated at runtimeMemory efficientAll code in ORCA CVS repository

ORCA simulation (C++)ORCA simulation (C++)

Lookup()Lookup()

GMT LUT YGMT LUT YLookup MethodLookup Method

GMT LUT XGMT LUT XLookup MethodLookup Method

configconfigfilefile

Scales,Scales,ParameterizationsParameterizations

Global Muon Trigger SimulationGlobal Muon Trigger Simulation

LUT Generator Application (C++)LUT Generator Application (C++)

COE COE memorymemorycontentscontents

LUT2HW tool (C++)LUT2HW tool (C++)

LUT LUT filefile

Save()Save()

GMT LUT YGMT LUT YSave MethodSave Method

GMT LUT XGMT LUT XSave MethodSave Method

configconfigfilefile

Scales,Scales,ParameterizationsParameterizations

LUT LUT filefile

C++ classesrepresent LUT function

Used in ORCA Simulation of GMT

Used to generate all files need

for firmware implementation

XCO XCO DPM RAMDPM RAM

definitiondefinition

.EDN.EDN .VHD.VHD .MIF.MIF

VHDLVHDL

wrapperwrapper

Xilinx CoreGeneratorXilinx CoreGenerator


GMT Hardware Status

• GMT consists of– 3 pipeline synchronizing boards … prototype available– 1 GMT logic board … logic design completed

• FPGA design for GMT logic board in progress– Input FPGA (4x) … logic design completed– MIP and ISO assignment unit (2x) … firmware completed (brl+fwd)– GMT logic FPGA (2x) … firmware 95% complete (brl+fwd) – Sorter FPGA (1x) … logic design completed

• Milestones (unchanged since Apr 2002)– (Dec 01) Dec 02: logic design completed … completed– (Dec 02) Dec 03: FPGA design done … progress as planned– (Dec 03) Jun 04: GMT available … progress as planned– (Jun 04) Oct 04: GMT tested … progress as planned– Oct 04: GMT integration tests start … planned on time– Jan 05: GMT integration tests completed … planned on time


A.Taurok 28 May 2003

Global Trigger56U Rack

4 Tracker Emulators,..other 6U_boards

(standard VME backplane)

GMT, GT, TCS(non-standard backplane)

Conversion boards(Fast signals,...)

(standard VME backplane)

2 S-links

JTAG

PCI-VME link

16 DT,CSC,RPC muon cables12 cables MIP/QUIET bits7 cables Calo trigger data

+1 free cable trigger data

32 TTC_data (L1A,cmd)

32 Subdetector STATUS cables8 DAQ STATUS cables

1U=1.75“=44.45mm56U racks, w=60cm, depth=90cm, h=256cm

Ethernet

2 opt. DAQ links

Note: PCs will actually be moved to top of rack

47U used

less than 9U used

PCs outside Air Flow

Rack Layout according to CMS Standard Rack: CMS-DISIR-IG-0002 v.2 (EDMS Id: 114226)

9kW cooling power3kW per crate

8 PTC STATUS cables

8 Emulator cables

2U Heat Exchanger

2U Fan Unit

9U/6U crate

2U Heat Exchanger

2U Fan Unit

9U crate

2U Heat Exchanger

2U Fan Unit

2U Heat Exchanger

2U Air Flow Guide

4U Cross Flow Fanwith Monitoring Unit

DAQ-PC

Online-PC

PrivateTest-PC

9U/6U crate

Global Trigger Rack


All boards on front side.

Boards arranged for minimum cable length.

Global Trigger Crate


VMEinterface PSBPSB

GTL6U

GTL_CONV

Global Trigger Prototype Crate


VMEinterface

MEMORYSYNCchips

ROP for DAQ

Input module

Synchronisation and monitoring of trigger data

PSB6U only for the Prototype Crate

PSB-6U Prototype Board


40, 80 MHz CLK drivers

DS92LV16 receivers

Registers for 40 80 MHz conversion

Infiniband connectors

DS92LV16 transmitter for

tests

new

PSB_IN80 for PSB-6U


VMEinterface

CONVchips

80MHzGTL+signals

ChannelLinkRec

+1.5V supply

VME to GTL6U

GTL_CONV is used only in the Prototype Crate

ChannelLink

signals

GTL Conversion Board


Calculates 64 trigger algorithms

GTL6U will be used in the prototype crate as well as in the final GT-crate

GTL-6U Logic Board (right side)

VME

REC chips

COND chips

GTL+signals

4x4 calo objects

4 muons


TIM chip

TTCrx

CLOCK circuits

LVDS driversCLK, BCRES, L1A,

RESETto each VME slot

VME

TIM-6U will be used in the prototype as well as in the final GT and DTTF crates.

Front Panel

new

TIM-6U Timing Module


A.T. 21.2.03

FDL-9U Final Decision Logic

VME

ALGO bits to DAQ

ALGO bits to EVM

Final OR bits to TCS

Techn.Trigger bitsfrom PSB

ALGO bits from GTL

FDL chipon

MEZZ896


TCS-9U Central Trigger Control Board

VME

FastSigs24 part‘s

+ 8DAQ part‘s

TCS statusto 8 DAQ part‘s

L1A,...to 32 TTCvi

FastSigs from8 Emulators

TCS_MON chip TCS chip Clock

EVM+DAQ records


bottom sidetop side50 Ohm

connectorsXC2V2000-4FF896C

BGA: 1mm pitch, track width=83 m

Mezzanine Board (MEZZ896)

MEZZ896 will be used in TCS-9U and FDL-9U


GCT/GT integration test setup

TTCvi

clk_in

A BTIM

clk_x

orbit_x NIM

NIM

ECL

SIGNAL GENERATOR

A

B

clk_outorbit_out

clk_out

clk_in

ECL

100kHz-1GHz

CLKboard

TTCrx

IM

bcres

clk

diff PECL

PSB +PSBin80

trans

return

rec

Serial Link 1280 Mbps

BGo command: 0001

AC

Global Trigger

GlobalCalorimeter

Trigger

TTC units

TTCvx

Infiniband cable 1m / 5m

GCT-trigger data

opticalfibre

Bristol + Vienna groups, Vienna, July 2003


GCT/GT integration test results and plans

Link latency50 ns with 1m cable, 65 ns with 5m cable.

Data exchange64 bits per 25 ns sent over one two-pair Infiniband cable.Different sets of patterns have been programmed at the transmitterend of the link and successfully read from a memory on the PSB.

ClockPLL-based clock drivers to stabilize the TTC clock signals can beused.

Long term stabilityFull test still to be made.20000 LHC orbits equivalent to 5 . 109 bit cycles tested.

Further testsPlanned in Vienna with boards from Bristol in autumn 2003.


GT on-line software

C++ test programs exist to run the following boards both stand-alone and as a system : PSB-6U, GTL-CONV, GTL-6U, TIM-6U, TTCvi.

The programs are being implemented as XDAQ-plugins.

The GT setup definition is planned in .xml format, also to be used by ORCA.

We are working on the SETUP program, including on a concept with a GUI.

BackplaneGlobal TriggerSetup Program

Database.sof, .pof.bit.xml.rbf, .bit, .rbt.vhd.vhd.sof, .pofHAL.rbf


Milestones updated • Custom Backplane for VME 9U crate

6U Prototype: Channel Links ... exists MS 03/02– 9U Backplane: 80MHz GTLp and Channel Links, ... design in progress MS 03/03 09/03 12/03

• PSB Input board (synchronisation, monitoring)

6 channel 6U Prototype: Channel Link receivers ... board tested MS 03/02 PSB-IN80: DS92LV16 serial receivers ... board tested

– 12 channel board: memories inside FPGAs ...conceptual design MS 06/04• GTL Logic board:

Conversion board for prototype ... board tested MS 03/02– GTL-6U prototype: 20 channels …hardware is tested MS 06/03

• Signal transfer tested with test patterns -> ok … working on firmware• XDAQ compatible test program in C++ exists• Loading of conditions not tested yet (software under development)

– GTL-9U board: 32 channels ...conceptual design MS 11/04

• 4, 4 isol. e/, 4e/, 4 central jets, 4 fwd jets, 4 -jets, ET, ET mis, HT, 12 jet counts

• TIM Timing board ... board tested MS 06/03 09/04 6U size, TTCrx, clock and L1A distribution, also used by DTTF; working on version for new TTCrx

• MEZZ896 Mezzanine boards (used on TCS-9U, FDL-9U) ... boards produced MS 06/03

• FDL-9U Final Decision board ... design in progress MS 06/03 11/03 02/04

• TCS-9U Central Trigger Control board ... Layout finished MS 04/03 09/03 12/03

• GTFE-9U Readout board ... conceptual design MS 12/03 03/04 02/05

Global Trigger Status and Milestones Sept. 2003Global Trigger Status and Milestones Sept. 2003


Production, Full Chain and Slice Tests, Integration

GTL-6U hardware ok

TIM-6U 09/04 (version for new TTCrx)

TCS-9U 09/03 12/03

BACK-9U 09/03 12/03

FDL-9U 11/03 02/04

System test (full chain) of 20-channel GT (without GTFE) 06/04

GT system tests 6/05

Global Trigger

PSB-9U 06/04

Integration of GT/GMT with DAQ 01/06

Slice tests performed in Vienna as boards become available.Installation and commissioning in USC55 planned in phase with other subsystems (GCT, regional muon trigger systems) during second half of 2005.

GTFE 03/04 02/05

GTL-9U 11/04

Global Muon Trigger

FPGA design 12/03

Board production 06/04

GMT system tests 01/05

Global Trigger PROTOTYPEBACK-6U ok PSB-6U okPSB-IN80 okGTL-CONV okGTL-6U hardware tested (Milestone 6/03)TIM-6U done (Milestone 6/03) - prototype will be

used as spare module for final systemIntegration test with GCT done (July 2003)


Acknowledgements

Thanks to the following people for providing transparencies:

J. Erö, J. F. de Trocóniz, Ch. Deldicque (DT Track Finder)

A. Montanari (Wedge Sorter)

H. Sakulin (Global Muon Trigger)

A. Taurok (Global Trigger hardware)

J. Strauss (Global Trigger software)


Summary of main progress

DTTF (Bologna, Madrid, Vienna) track finder function evaluation prototype produced and tested (Vienna)

track finder VHDL model and board design ready (Madrid, Vienna) Wedge Sorter prototype available (Bologna)

Other DTTF boards produced (Vienna)

GMT (Vienna)FPGA logic design close to completion

GT (Vienna)Logic board produced and testedTiming module produced and testedLayout of TCS module finished

All systems (Bologna, Budapest, Madrid, Vienna)On-line software under developmentORCA software updated in parallelCMS-Note on SUSY level-1 trigger efficiencies practically ready

DT Track Finder, Global Muon Trigger, Global Trigger H. Bergauer, L. Boldizsar, M. Dallavalle, Ch....

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