dsp56f827evm - NXP

56F800

16-bit Digital Signal Controllers

freescale.com

56F827Evaluation Module User Manual

DSP56F827EVMUMRev. 207/2005

TABLE OF CONTENTS

Table of Contents, Rev. 2

Freescale Semiconductor i

Preface vii

Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

Notation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

Chapter 1Introduction

1.1 56F827EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 56F827EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.3 56F827EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Chapter 2Technical Summary

2.1 56F827. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Program and Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.3 SPI EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.4 RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.5 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.6 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.7 Debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.8 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.8.1 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.8.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.9 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.10 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.12 Stereo Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.12.1 Analog Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.12.2 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.13 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.13.1 Memory Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.13.2 Peripheral Daughter Card Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

56F827EVM User Manual, Rev. 2

ii Freescale Semiconductor

2.14 SCI Port #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.15 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Appendix A56F827EVM Schematics

Appendix B56F827EVM Bill of Material

LIST OF FIGURES

List of Figures, Rev. 2

Freescale Semiconductor iii

1-1 Block Diagram of the 56F827EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1-2 56F827EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1-3 Connecting the 56F827EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

2-1 Schematic Diagram of the External Memory Interface. . . . . . . . . . . . . . . . . . . . . . . 2-3

2-2 SPI EEPROM Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2-3 Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2-4 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2-5 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2-6 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2-7 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2-8 Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2-9 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2-10 Codec Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2-11 CS4218 Stereo Audio Codec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16


iv Freescale Semiconductor

LIST OF TABLES

List of Tables, Rev. 2

Freescale Semiconductor v

1-1 56F827EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2-1 SPI Port Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2-2 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2-3 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2-4 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2-5 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . . 2-9

2-6 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2-7 Codec Sample Rate Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2-8 Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2-9 Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-19

2-10 SCI Port #2 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20


vi Freescale Semiconductor

Preface, Rev. 2

Freescale Semiconductor vii

Preface

This reference manual describes in detail the hardware on the 56F827 Evaluation Module.

AudienceThis document is intended for application developers who are creating software for

devices using the 56F827 part.

OrganizationThis manual is organized into two chapters and two appendixes.

• Chapter 1, Introduction - provides an overview of the EVM and its features.

• Chapter 2, Technical Summary - describes in detail the 56F827 hardware.

• Appendix A, "56F827EVM Schematics" contains the schematics of the

DSP56F827EVM.

• Appendix B, 56F827EVM Bill of Material - provides a list of the materials used on the

DSP56F827EVM board.

Suggested ReadingMore documentation on the 56F827 and the DSP56F827EVM kit may be found at URL:

www.freescale.com

DSP56F827EVM User Manual, Rev. 2

viii Freescale Semiconductor

Notation ConventionsThis manual uses the following notational conventions:

Term or Value Symbol Examples Exceptions

Active High Signals (Logic One)

No special symbol attached to the signal name

A0CLKO

Active Low Signals(Logic Zero)

Noted with an overbar in text and in most figures

WEOE

In schematic drawings, Active Low Signals may be noted by a backslash: /WE

HexadecimalValues

Begin with a “$” symbol

$0FF0$80

Decimal Values No special symbol attached to the number

1034

Binary Values Begin with the letter “b” attached to the number

b1010b0011

Numbers Considered positive unless specifically noted as a negative value

5-10

Voltage is often shown as positive: +3.3V

Blue Text Linkable on-line ...refer to Figure 1-1

Bold Reference sources, paths, emphasis

...see: http://www.freescale.com/...

Preface, Rev. 2

Freescale Semiconductor ix

Definitions, Acronyms, and AbbreviationsDefinitions, acronyms and abbreviations for terms used in this document are defined below for

reference.

Codec COder/DECoder; a part used to convert analog signals to digital (Coder) and digital signals to analog (Decoder)

EEPROM Electrically Erasable Programmable Read Only Memory

EVM Evaluation Module; a hardware platform which allows a customer to evaluate the silicon and develop their application

GPIO General Purpose Input and Output Port; does not share pin functionality with any other peripheral on the chip and can only be set as an input, output or level-sensitive interrupt input

IC Integrated Circuit

JTAG Joint Test Action Group; a bus protocol/interface used for test and debug

LQFP Low-profile Quad Flat Pack

MPIO Multi-Purpose Input/Output Port; shares package pins with other peripherals on the chip and can function as a GPIO

OnCETM

On-Chip Emulation, a debug bus and port created by Freescale to enable designers to create a low-cost hardware interface for a professional quality debug environment

PCB Printed Circuit Board

PLL Phase Locked Loop

RAM Random Access Memory

ROM Read-Only Memory

SCI Serial Communications Interface Port

SPI Serial Peripheral Interface Port

SRAM Static Random Access Memory

SSI Synchronous Serial Interface Port

WS Wait State


x Freescale Semiconductor

ReferencesThe following sources were referenced to produce this manual:

[1] DSP56800 Family Manual, DSP56800FM, Freescale Semiconductor

[2] DSP56F826/827 Digital Signal Processor User’s Manual, DSP56F826_827UM,

Freescale Semiconductor

[3] DSP56F827 Technical Data, DSP56F827, Freescale Semiconductor

Introduction, Rev. 2

Freescale Semiconductor 1-1

Chapter 1Introduction

The 56F827EVM is used to demonstrate the abilities of the 56F827 and to provide a

hardware tool allowing the development of applications that use the 56F827.

The 56F827EVM is an evaluation module board that includes a 56F827 part, 16-bit stereo

codec, external memory and a daughter card expansion interface. The daughter card

expansion connectors are for signal monitoring and user feature expandability.

The 56F827EVM is designed for the following purposes:

• Allowing new users to become familiar with the features of the 56800 architecture.

The tools and examples provided with the 56F827EVM facilitate evaluation of the

feature set and the benefits of the family.

• Serving as a platform for real-time software development. The tool suite enables

the user to develop and simulate routines, download the software to on-chip or

on-board RAM, run it, and debug it using a debugger via the JTAG/OnCETM port.

The breakpoint features of the OnCE port enable the user to easily specify complex

break conditions and to execute user-developed software at full-speed, until the

break conditions are satisfied. The ability to examine and modify all user

accessible registers, memory and peripherals through the OnCE port greatly

facilitates the task of the developer.

• Serving as a platform for hardware development. The hardware platform enables

the user to connect external hardware peripherals. The on-board peripherals can be

disabled, providing the user with the ability to reassign any and all of the

controller's peripherals. The OnCE port's unobtrusive design means that all of the

memory on the board and on the controller chip are available to the user.

1.1 56F827EVM Architecture

The 56F827EVM facilitates the evaluation of various features present in the 56F827 part.

The 56F827EVM can be used to develop real-time software and hardware products based


1-2 Freescale Semiconductor

on the 56F827. The 56F827EVM provides the features necessary for a user to write and debug

software, demonstrate the functionality of that software and interface with the customer's

application-specific device(s). The 56F827EVM is flexible enough to allow a user to fully

exploit the 56F827's features to optimize the performance of his product, as shown in Figure 1-1.

56F827

RESET

MODE

Address,Data &Control

JTAG/OnCE

XTAL/EXTAL

SPI

SCI

SSI

GPIO

& GND

Peripheral Daughter

Card Connector

RESETLOGIC

MODELOGIC

Program Memory64Kx16-bit

SRAM

MemoryDaughter Card

Connector

JTAGConnector

ParallelJTAG

Interface

4.00MHzCrystal

DSub25-Pin

Data Memory64Kx16-bit

SRAM

Debug LEDs

Stereo 16-bitCodec

RS-232Interface

SPI EEPROM1M-bit

Power Supply+2.5V, +3.3V & +5.0V

IRQ InterfaceIRQ

Amp

Stereo Line Out

Headphone Jack

Stereo Line In

+2.5V, +3.3V

A/D

DSub9-Pin

Figure 1-1. Block Diagram of the 56F827EVM

1.2 56F827EVM Configuration Jumpers

Seven jumper groups, (JG1-JG7), shown in Figure 1-2, are used to configure various features on

the 56F827EVM board. Table 1-1 describes the default jumper group settings.

JG6DSP56F827EVM

J3

JTAG

U7

S/N

P1

Y1

U1U2 S2

S3

S1

S4

P2

LEDS

JG5

JG2

U5

RESET

IRQB

IRQA

1

2

7

8

JG3

J2

P6

1

JG5

3

JG2

JG3

JG1

JG6

TB1

P3

P4 P5

JG4

J1

JG7

HEADPHONE

LINELINEIN OUT

JG1

JG4

31

JG7

J3

JTAG

56F827EVM Connections

Introduction, Rev. 2


Figure 1-2. 56F827EVM Jumper Reference

Table 1-1. 56F827EVM Default Jumper Options

Jumper

GroupComment

Jumpers

Connections

JG1 Enable on-board Parallel JTAG Host/Target Interface NC

JG2 Enable RS-232 output NC

JG3 Enable on-board SRAM 1–2

JG4 Use on-board EXTAL crystal input for controller oscillator 2–3

JG5 Use on-board XTAL crystal input for controller oscillator 1–2

JG6 Selects controller’s Mode 0 operation upon exit from reset 1-2

JG7 Enable SPI EEPROM 1–2, 3–4, 5–6 & 7–8

1.3 56F827EVM Connections

An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external

+12.0V DC power supply or external +5.0V DC lab power supply to the 56F827EVM board.

PC-compatible

Cable

Computer

Parallel Extension

56F827EVM

External+12.0VPower

P2

P1Connect cableto Parallel/Printer port

with 2.1mm,receptacleconnector

+5.0VLab

Supply

TB1

or



Figure 1-3. Connecting the 56F827EVM Cables

Perform the following steps to connect the 56F827EVM cables:

1. Connect the parallel extension cable to the parallel port of the host computer.

2. Connect the other end of the parallel extension cable to P2, shown in Figure 1-3, on the

56F827EVM board. This provides the connection which allows the host computer to

control the board.

3. Make sure that the external +12.0V DC 1.2A switching power supply or the external

+5.0V DC 1.0A lab power supply is not plugged into a 120V AC power source.

4. Connect the 2.1mm output power plug from the external switching power supply into P1,

shown in Figure 1-3, on the 56F827EVM board. Optionally, attach an external +5.0V DC

lab power supply via the 2-pin terminal block, TB1.

5. Apply power to the external power supply. The green Power-On LED, LED7, will

illuminate when power is correctly applied.

Technical Summary, Rev. 2


Chapter 2Technical Summary

The 56F827EVM is designed as a versatile controller development card for developing

real-time software and hardware products to support a new generation of applications in

digital and wireless messaging, digital answering machines, feature phones, modems, and

digital cameras. The power of the 16-bit 56F827 controller, combined with the on-board

64K 16-bit external program static RAM (SRAM), 64K 16-bit external data SRAM,

RS-232 interface, stereo 16-bit codec interface, Daughter Card Expansion interface and

parallel JTAG interface, makes the 56F827EVM ideal for developing and implementing

many audio and voice algorithms, as well as for learning the architecture and instruction

set of the 56F827 processor.

The main features of the 56F827EVM, with board and schematic reference designators

include:

• 56F827 16-bit +2.5V/+3.3V controller operating at 80MHz [U1]

• External fast static RAM (FSRAM) memory [U2], configured as:

— 64K 16 bits of program memory with 0 wait states at 70MHz

— 64K 16 bits of data memory with 0 wait states at 70MHz

• 1M-bit Serial EEPROM [U4]

• 4.00MHz crystal oscillator for controller frequency generation [Y1]

• Optional external oscillator frequency input connector [JG4 and JG5]

• Joint Test Action Group (JTAG) port interface connector for an external debug

Host Target Interface [J3]

• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer

port cable [P2]

• RS-232 interface for easy connection to a host processor [U3 and P3]

• 16-bit stereo codec interface [U5, P4 and P5]

• Stereo headphone interface [U6 and P6]



• Codec sample rate selector [S4]

• Peripheral Daughter Card Expansion Connector, to allow the user to connect his own SCI,

SSI, SPI or GPIO-compatible peripheral to the controller[J2]

• Memory Daughter Card Expansion Connector, to allow the user to connect his own

memory or memory device to the controller[J1]

• On-board power regulation from an external +12V DC-supplied power input [P1]

• On-board power regulation from an optional +5V DC-supplied power input [TB1]

• Light Emitting Diode (LED) power indicator [LED7]

• Six on-board real-time user debugging LEDs [LED1-6]

• Manual RESET push-button [S1]

• Manual interrupt push-button for IRQA [S2]

• Manual interrupt push-button for IRQB [S3]

2.1 56F827

The 56F827EVM uses a Freescale DSP56F827FG80 part, designated as U1 on the board and in

the schematics. This part will operate at a maximum speed of 80MHz. A full description of the

56F827, including functionality and user information, is provided in these documents:

• DSP56F827 Technical Data, (DSP56F827): Provides features list and specifications

including signal descriptions, DC power requirements, AC timing requirements and

available packaging.

• DSP56F826/827 16-Bit Digital Signal Processor User’s Manual, (DSP56F826_827UM):

Provides an overview description of the controller and detailed information about the

on-chip components including the memory and I/O maps, peripheral functionality, and

control/status register descriptions for each subsystem.

• DSP56800 Family Manual, (DSP56800FM): Provides a detailed description of the core

processor, including internal status and control registers and a detailed description of the

family instruction set.

Refer to these documents for detailed information about chip functionality and operation. They

can be found on this URL:

www.freescale.com

Program and Data Memory



2.2 Program and Data Memory

The 56F827EVM uses one bank of 128K 16-bit Fast Static RAM (GSI GS72116, labelled U2)

for external memory expansion; see the FSRAM schematic diagram in Figure 2-1. This physical

memory bank is split into two logical memory banks of 64Kx16-bits: one for program memory

and the other for data memory. By using the controller’s program strobe, PS, signal line along

with the memory chip’s A0 signal line, half of the memory chip is selected when program

memory accesses are requested and the other half of the memory chip is selected when data

memory access are requested. This memory bank will operate with zero wait-state accesses while

the 56F827 is running at 70MHz. However, when running at 80MHz, the memory bank operates

with four wait-state accesses. This memory bank can be disabled by removing the jumper at JG3.

56F827 GS72116

A0-A15

PS

D0-D15

RD

WR

A1-A16

A0

DQ0-DQ15

OE

WE

CE

1 2

JG3

+3.3V

Jumper Pin 1-2:

Enable SRAM

Jumper Removed:

Disable SRAM

Figure 2-1. Schematic Diagram of the External Memory Interface



2.3 SPI EEPROM Memory

A 1M-bit +3.3V SPI serial EEPROM Memory, Atmel AT45DB011-SC, is provided on the

56F827EVM, reference Figure 2-2. This memory connects directly to the SPI Port through a

header on the 56F827. It can be used to load program code and data into the 56F827’s internal or

external memory spaces. A jumper block is provided, JG7, to allow the user to disconnect the

on-board SPI EEPROM from the SPI port and allow him to connect his own SPI port peripheral.

The header details are shown in Table 2-1.

56F827

MOSI

MISO

SCLK

GPIOF7

Serial EEPROM

SDI

SDO

SCK

CS

EEPROM Enable(SPI Port Connector)

Figure 2-2. SPI EEPROM Memory Block Diagram

Table 2-1. SPI Port Connector Description

JG7

Pin # Signal Pin # Signal

1 SS/GPIO7 2 CS

3 MISO 4 SDO

5 MOSI 6 SDI

7 SCLK 8 SCK

RS-232 Serial Communications



2.4 RS-232 Serial Communications

The 56F827EVM provides an RS-232 interface by the use of an RS-232 level converter, (Maxim

MAX3245EEAI, designated as U3). Refer to the RS-232 schematic diagram in Figure 2-3. The

RS-232 level converter transitions the SCI UART’s +3.3V signal levels to RS-232 compatible

signal levels and connects to the host’s serial port via connector P3. Flow control is not provided,

but could be implemented using uncommitted GPIO signals. The pinout of connector P3 is listed

in Table 2-2. The RS-232 level converter/transceiver can be disabled by placing a jumper at JG2.

56F827RS-232

Level Converter Interface

TXDO

RXDO R1in

T1outT1in

R1out

FORCEOFF

JG2

12

6

3

2

7

84

5x

1

9+3.3V

Jumper Removed:

Enable RS-232

Jumper Pin 1-2:

Disable RS-232

P3

Figure 2-3. Schematic Diagram of the RS-232 Interface

Table 2-2. RS-232 Serial Connector Description

P3


1 Jumper to 6 & 4 6 Jumper to 1 & 4

2 TXD 7 Jumper to 8

3 RXD 8 Jumper to 7

4 Jumper to 1 & 6 9 N/C

5 GND



2.5 Clock Source

The 56F827EVM uses a 4.00MHz crystal, Y1, connected to its External Crystal Inputs, EXTAL

and XTAL. The 56F827 uses its internal PLL to multiply the input frequency by 20, achieving its

80MHz maximum operating frequency. An external oscillator source can be connected to the

controller by using the oscillator bypass connectors, JG4 and JG5; see Figure 2-4. If the input

frequency is above 4MHz, then the EXTAL input should be jumpered to ground by adding a

jumper between JG4 pins 2 and 3. The input frequency would then be injected on JG5’s pin 2. If

the controller needs to be synchronized to the codec’s sample frequency, then the controller’s

input frequency should be jumpered using the 12.2280MHz codec frequency. If the input

frequency is below 4MHz, then the input frequency can be injected on JG4’s pin 2.

56F827

EXTERNAL OSCILLATOR

HEADERS

JG4

3 21

1 23

EXTAL

XTAL

JG5

10M4.00MHz

12.2880MHz

Figure 2-4. Schematic Diagram of the Clock Interface

Operating Mode



2.6 Operating Mode

The 56F827EVM provides a boot-up MODE selection jumper, JG6. This jumper is used to select

the operating mode of the controller as it exits RESET. Refer to the DSP56F827 User’s Manual

for a complete description of the chip’s operating modes. Table 2-3 shows the two operation

modes available on the 56F827.

Table 2-3. Operating Mode Selection

Operating Mode JG6 Comment

0 1–2 Bootstrap from internal memory

3 No Jumper Bootstrap from external memory



2.7 Debug LEDs

Six on-board Light-Emitting Diodes, (LEDs), are provided to allow real-time debugging for user

programs. These LEDs will allow the programmer to monitor program execution without having

to stop the program during debugging; refer to Figure 2-5. User LED1 is controlled by Port B’s

PB0 signal. User LED2 is controlled by PB1. User LED3 is controlled by PB2. User LED4 is

controlled by PB3. User LED5 is controlled by PB4. User LED6 is controlled by PB5. Setting

PB0, PB1, PB2, PB3, PB4 or PB5 to a Logic One value will turn on the associated LED.

56F827 INVERTING BUFFER

PB0

PB1

PB2

GREEN LED

YELLOW LED

RED LED

+3.3V

GREEN LED

YELLOW LED

RED LED

PB3

PB4

PB5

Figure 2-5. Schematic Diagram of the Debug LED Interface

2.8 Debug Support

The 56F827EVM provides an on-board Parallel JTAG Host Target Interface and a JTAG

interface connector for external Target Interface support. Two interface connectors are provided

to support each of these debugging approaches. These two connectors are designated the JTAG

connector and the Host Parallel Interface Connector.

Debug Support



2.8.1 JTAG Connector

The JTAG connector on the 56F827EVM allows the connection of an external Host Target

Interface for downloading programs and working with the 56F827’s registers. This connector is

used to communicate with an external Host Target Interface which passes information and data

back and forth with a host processor running a debugger program. Table 2-4 shows the pin-out

for this connector.

Table 2-4. JTAG Connector Description

J3


1 TDI 2 GND

3 TDO 4 GND

5 TCK 6 GND

7 NC 8 KEY

9 RESET 10 TMS

11 +3.3V 12 NC

13 NC 14 TRST

When this connector is used with an external Host Target Interface, the parallel JTAG interface

should be disabled by placing a jumper in jumper block JG1. See Table 2-5 for this jumper’s

selection options.

Table 2-5. Parallel JTAG Interface Disable Jumper Selection

JG1 Comment

No jumpers On-board Parallel JTAG Interface Enabled

1–2 Disable on-board Parallel JTAG Interface



2.8.2 Parallel JTAG Interface Connector

The Parallel JTAG Interface Connector, P2, allows the 56F827 to communicate with a Parallel

Printer Port on a Windows PC; reference Figure 2-6. By using this connector, the user can

download programs and work with the 56F827’s registers. Table 2-6 shows the pin-out for this

connector. When using the parallel JTAG interface, the jumper at JG1 should be removed, as

shown in Table 2-5.

DB-25 Connector Parallel JTAG Interface 56F827

TDITDO

P_TRST

TMS

TCK

P_RESET

OUT

OUT

OUT

OUT

OUT

OUTIN

IN

IN

IN

IN

IN

EN

TDI

TDO

TRST

TMS

TCK

RESET

JG1

1

2

+3.3V

Jumper Removed:

Enable JTAG I/F

Jumper Pin 1-2:

Disable JTAG I/F

Figure 2-6. Block Diagram of the Parallel JTAG Interface

Table 2-6. Parallel JTAG Interface Connector Description

P2


1 NC 14 NC

2 PORT_RESET 15 PORT_IDENT

3 PORT_TMS 16 NC

4 PORT_TCK 17 NC

5 PORT_TDI 18 GND

6 PORT_TRST 19 GND

7 NC 20 GND

8 PORT_IDENT 21 GND

9 PORT_VCC 22 GND

10 NC 23 GND

11 PORT_TDO 24 GND

12 NC 25 GND

13 PORT_CONNECT

Debug Support





2.9 External Interrupts

Two on-board push-button switches are provided for external interrupt generation, as shown in

Figure 2-7. S2 allows the user to generate a hardware interrupt for signal line IRQA. S3 allows

the user to generate a hardware interrupt for signal line IRQB. These two switches allow the user

to generate interrupts for his user-specific programs.

56F827

IRQA

IRQB

+3.3V

+3.3V

10K

10K

SW2

SW3

0.1µF

0.1µF

Figure 2-7. Schematic Diagram of the User Interrupt Interface

Reset



2.10 Reset

Logic is provided on the 56F827 to generate an internal Power-On RESET. Additional reset logic

is provided to support the RESET signals from the JTAG connector, the Parallel JTAG Interface

and the user RESET push-button; refer to Figure 2-8.

RESETPUSHBUTTON

MANUAL RESET

JTAG_TAP_RESET

JTAG_RESETRESET

TRST

Figure 2-8. Schematic Diagram of the RESET Interface



2.11 Power Supply

The main power input, +12.0V DC, to the 56F827EVM is through a 2.1mm coax power jack, P1.

An optional +5.0V DC power supply input is available through a 2-pin terminal block, TB1. A

1.2A power supply is provided with the 56F827EVM; however, less than 500mA is required by

the EVM. The remaining current is available for user daughter card applications when connected

to the daughter card interface. The power regulation on the 56F827EVM provides +5.0V DC

voltage regulation for the codec’s analog circuits and to the additional voltage regulation logic on

the EVM. The additional voltage regulation logic provides +2.5V DC voltage regulation for the

controller’s core and +3.3V DC voltage regulation for the controller’s I/O, memory, parallel

JTAG interface and supporting logic; refer to Figure 2-9. Power applied to the 56F827EVM is

indicated with a Power-On LED, referenced as LED7.

+5.0V DCAnalog

+12.0V DCPower

ConditionCodec

56F827+3.3V

Regulator

TB1

P1

+5.0V DC

GND

+2.5VRegulator

56F827EVMParts

56F827Core

+3.3V DC

+2.5V DC

+5.0VRegulator

Figure 2-9. Schematic Diagram of the Power Supply

2.12 Stereo Codec

A 16-bit audio quality stereo codec, Crystal Semiconductor CS4218, is connected to the

56F827’s SSI port to support audio, voice and signal analysis applications. The codec is clocked

with a 12.288MHz oscillator. This allows the codec to operate between a sample frequency of

8kHz and 48kHz. The sample rate can be manually set by setting the appropriate switch positions

on dip switch S4. The sample rate selections possible using this three-position dip switch are

detailed in Table 2-7. The codec supports +3.3V digital levels, eliminating the need for

voltage-level translation circuitry. Additionally, a set of zero ohm resistors are provided on the

EVM to allow a user to disconnect the on-board codec from the SSI port and to connect his own

codec to the SSI port; refer to Figure 2-11. The on-board codec has analog signal conditioning

Stereo Codec



logic, allowing direct connection to its line-level input and line-level output signals through two

1/8” stereo jacks; see Figure 2-10.

Table 2-7. Codec Sample Rate Selector

SW 4

Position 3

(MF6)

SW 4

Position 2

(MF7)

SW 4

Position 1

(MF8)Sample Rate

ON ON ON 48.00kHz

ON ON OFF 32.00kHz

ON OFF ON 24.00kHz

ON OFF OFF 19.20kHz

OFF ON ON 16.00kHz

OFF ON OFF 12.00KHz

OFF OFF ON 9.60kHz

OFF OFF OFF 8.00kHz

Line-level

Output

RIN1

LIN1

LOUTL

LOUTR

A

A

A

Line-level

Output

Headphone

Input

CS4218

LM4880

P4 P5

P6

Figure 2-10. Codec Analog Connections

Codec Enable Logic56F827 CS4218

SDIN

SDOUT

SCLK

FSYNC

RESET

STD

SRD

STCK

STFS

PD0

CCS

CDIN

CCLK

PD1

PD2

PD3



Figure 2-11. CS4218 Stereo Audio Codec

2.12.1 Analog Input/Output

The 56F827EVM uses jacks for line-level stereo input, line-level stereo output and stereo

headphone output. A National Semiconductor LM4880 is used to provide the drive required for

the use of headphones. This device offers a THD, which is superior to the CS4218’s on-chip

headphone drive circuitry by a factor of two. The basic Analog codec connections are shown in

Figure 2-10.

2.12.2 Digital Interface

The serial interface of the codec transfers digital audio data and control data into and out of the

device. The SSI port, which consists of independent transmitter and receiver sections, is used for

serial communication with the codec.

On the controller side, the Serial Transmit Data pin, STD, is an output when data is being

transmitted to the codec. The Serial Receive Data pin, SRD, is an input when data is being

received from the codec. These two pins are connected to the codec’s Serial Data Input pin,

SDIN, and Serial Data Output pin, SDOUT.

The controller’s Transmit Serial Clock pin, STCK, provides the serial bit rate clock for the SSI

interface. It is connected to the codec’s Serial Port Clock pin, SCLK. Data is transmitted on the

rising edge of SCLK and is received on the falling edge of SCLK.

Daughter Card Connectors



The device’s GPIO PORT D Bit 0 pin, PD0, is programmed to control the codec’s Active Low

Reset signal, RESET.

The Serial Transmit Frame Sync pin, STFS, is programmed to control the codec’s Frame Sync

signal, FSYNC. FSYNC is sampled by SCLK, with a rising edge indicating a new frame is about

to start. The FSYNC frequency is always the system’s sample rate. It may be an input to the

codec, or it may be an output from the codec in data mode.

The basic codec digital connections are shown in Figure 2-11.

The codec’s MODE is set by the three MODE selection resistors, R96-R98. In the factory default

setting of MODE 4, the codec is set to be the Master of the SPI bus with its data word set at 32

bits per frame; i.e., a 16-bit Left channel and a 16-bit Right channel. The sample rate is selected

on Sample Rate Selector switch S4; reference Table 2-7 for selection options. Codec control

information is sent over a separate serial port using: PD1 as the Control Chip Select signal, CCS;

PD2 as the Control Data Input signal, CDIN; and PD3 as the Control Clock signal, CCLK.

2.13 Daughter Card Connectors

The EVM board contains two daughter card expansion connectors. One connector, J1, contains

the controller’s external memory bus signals. The other connector, J2, contains the device’s

peripheral port signals.

2.13.1 Memory Daughter Card Expansion Connector

The controller’s external memory bus signals are connected to the Memory Daughter Card

Expansion connector, J1. Table 2-8 shows the port signal to pin assignments.

Table 2-8. Memory Daughter Card Connector Description

J1


1 A10 2 A11

3 A9 4 DS

5 A8 6 A15

7 A7 8 A14

9 GND 10 PCS7



2.13.2 Peripheral Daughter Card Expansion Connector

The controller’s peripheral port signals are connected to the Peripheral Daughter Card Expansion

connector, J2. Table 2-9 shows the port signal to pin assignments.

11 WR 12 A13

13 D0 14 A12

15 D1 16 D8

17 D2 18 D9

19 GND 20 GND

21 D3 22 D10

23 D4 24 D11

25 D5 26 D12

27 D6 28 D13

29 PCS6 30 PCS5

31 D7 32 D14

33 PS 34 D15

35 A0 36 RD

37 A1 38 A6

39 PCS4 40 GND

41 A2 42 A5

43 A3 44 A4

45 PCS3 46 PCS2

47 +3.3V 48 +3.3V

49 GND 50 GND

51 GND

Table 2-8. Memory Daughter Card Connector Description

J1


Daughter Card Connectors



Table 2-9. Peripheral Daughter Card Connector Description

J2


1 PB0 2 PB1

3 CLKO 4 PB2

5 TA0 6 TA1

7 PB3 8 PB4

9 TA2 10 TA3

11 PB5 12 PB6

13 ANA0 14 ANA1

15 SRD 16 PB7

17 SRFS 18 PD0

19 SCLK 20 PD1

21 ANA2 22 ANA3

23 MOSI 24 PD2

25 MISO 26 PD3

27 ANA4 28 ANA5

29 SS 30 PD4

31 SRCK 32 PD5

33 STFS 34 PD6

35 RESET 36 PD7

37 ANA6 38 ANA7

39 STD 40 RXD1

41 STCK 42 TXD1

43 IRQB 44 RXD0

45 IRQA 46 TXD0

47 +3.3V 48 +3.3V



2.14 SCI Port #2

A separate connector, J4, is provided to allow the easy connection of SCI Port #2 signals along

with a reference GND signal.

Table 2-10. SCI Port #2 Connector

J4 Signal Description

1 TXD2

2 RXD2

3 GND

2.15 Test Points

The 56F827EVM board has a total of seven test points. Three digital GND test points are located

in corners of the board. The +5.0VA and AGND test points are located in the bottom right,

analog corner, of the board. The +2.5V and +3.3V test points are located in the upper right, power

supply section, of the board.

49 ANA8 50 ANA9

51 GND

Table 2-9. Peripheral Daughter Card Connector Description (Continued)

J2


Appendix A, Rev. 2

Freescale Semiconductor A-1

Appendix A56F827EVM Schematics

A A

B B

C C

D D

E E

44

33

22

11

RED LED

YELLOW LED

GREEN LED

RED LED

YELLOW LED

GREEN LED

DSP

D D

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P56

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Pro

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4

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A6

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D6

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D1

D10

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D7

A10

A[0

..15

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[0..

15] M

ISO

SC

LK

RX

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1

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0

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D1

PB

0P

B1

PB

2P

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PB

6P

B7

PD

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PD

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PD

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3

PB

4

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5

PB

0

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1

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2

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C04

AD

34

R9

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MC

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AD

56

R4

47K

R5

47K

R7

47K

R8

47K

R10

47K

R12

47K

LED

1

LED

2

LED

3

LED

4

LED

5

LED

6

J4 1 2 3

T19

1T1

81

U1

DS

P56

F827

FG80

125

126

127

128 1 2 3 6 7 8 9 10 11 12 13 14

21 22 23 24 25 26 27 28 31 32 33 34 35 36 37 38 124

123

122

121

120

119

118

117

98 97 96 95 94 93 92 91

100

101

102 99 108

107

106

105 55 52 51 50 53 42

40 49

48 47 44 46 45 43 83 58 30 511

5 80 20

16 15 18 17 5759 60

62 61

82 56 29 4 116

81

54 41

19

39 112

110

111

109 63

65 6667 6870 71 72 73 74 64

69

75 76 7877

84 85 86 87 88 89

90

104

103

113

114

79

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

A0/

PE

0A

1/P

E1

A2/

PE

2A

3/P

E3

A4/

PE

4A

5/P

E5

A6/

PE

6A

7/P

E7

A8/

PA

0A

9/P

A1

A10

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2A

11/P

A3

A12

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4A

13/P

A5

A14

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6A

15/P

A7

PB

0P

B1

PB

2P

B3

PB

4P

B5

PB

6P

B7

PD

0P

D1

PD

2P

D3

PD

4P

D5

PD

6P

D7

MIS

O/P

F6

MO

SI/

PF

5S

CLK

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4S

S/P

F7

TX

D0/

SC

LK0

RX

D0/

MO

SI0

TX

D1/

MIS

O0

RX

D1/

SS

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SR

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C0

ST

D/P

C3

ST

FS

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4

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CK

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RC

K/P

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RE

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T

IRQ

AIR

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TD

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DO

TC

KT

MS

TR

ST

TC

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GN

D7

GN

D10

GN

DC

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ND

C2

GN

DC

3

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RD

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S0

DS

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S1

CLK

O

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TA

LX

TA

L

VD

DA

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VS

SA

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VD

D3

VD

D5

VD

D7

VD

D10

VD

DC

1V

DD

C2

SR

FS

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1

DE

VD

DC

3

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T

TA

0/P

F0

TA

2/P

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TA

1/P

F1

TA

3/P

F3

VS

SA

_AD

C

VR

EF

P

VR

EF

N

VR

EF

HI

VR

EF

MID

AN

A0

AN

A1

AN

A2

AN

A3

AN

A4

VR

EF

LO

VD

DA

_AD

C

AN

A5

AN

A6

AN

A8

AN

A7

PC

S2

PC

S3

PC

S4

PC

S5

PC

S6

PC

S7

VP

P

TX

D2

RX

D2

VD

D1

GN

D1

AN

A9

T16

1T1

71


A-2 Freescale Semiconductor

Fig

ure

A-1

.

56F

827 P

rocesso

r an

d D

eb

ug

LE

DS

A A

B B

C C

D D

E E

44

33

22

11

IRQA PUSHBUTTON

OSC BYPASS

IRQB PUSHBUTTON

RESET PUSHBUTTON

BO

OT

MO

DE

JU

MP

ER

INT BOOT

EXT BOOT

NC

1 - 2

12

3

DS1818

EXT OSC

>8MHZ

DS

PD

Des

ign

RE

SE

T,

CL

OC

K,

BO

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& I

RQ

S

DS

P5

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Mon

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3

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Hz

S1

S2

S3

R7

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R7

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R7

01

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U1

2

DS

18

18

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3

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RS

TG

ND

C3

00

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F

C3

10

.1u

F

C3

20

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F

JG5

12

3

Appendix A, Rev. 2


Fig

ure

A-2

.

Reset,

Clo

ck,

Bo

ot

Mo

de &

IR

Qs

A A

B B

C C

D D

E E

44

33

22

11

64Kx16-bit Program and 64Kx16-bit Data Memory

SR

AM

EN

AB

LE

JU

MP

ER

OPTION

JG3

SRAM ENABLE

SRAM DISABLE

1-2

NC

DS

PD

Des

ign

PR

OG

RA

M a

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DA

TA

SR

AM

ME

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Mon

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D5

D2

D1

3

D3

D7

D1

D1

5

D1

1

D4

D1

0

D6

D0

D1

2

D9

D8

D1

4

A1

1

A1

0

A1

A9

A1

5

A3

A7

A5

A1

4

A6

A1

3

A0

A1

2

A8

A2

A4

/RD

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D[0

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5]

A[0

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5]

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+3

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GS

72

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P-1

2

7 8

1

9 10

21

31

4

3

15

16

4

29

30

5

31

32

18

35

36

19

37

38

20

21

24

25

26

27

42

43

44

40

39

41

17 6

22

34

12

33

11

DQ

1D

Q2

A4

DQ

3D

Q4

A3

DQ

5D

Q6

A2

DQ

7D

Q8

A1

DQ

9D

Q1

0

A0

DQ

11

DQ

12

A1

5

DQ

13

DQ

14

A1

4D

Q1

5D

Q1

6

A1

3A

12

A1

1A

10

A9

A8

A7

A6

A5

UB

LB

OE

WE

CE

A1

6

VS

SV

SS

VD

DV

DD

JG3 1 2

R6

71

0K

R6

91

KR

68

1K



Fig

ure

A-3

.

Pro

gra

m &

Data

SR

AM

Mem

ory

A A

B B

C C

D D

E E

44

33

22

11

EEPROM Enable

DS

PD

Des

ign

SP

I S

eri

al

1M

-Bit

EE

PR

OM

ME

MO

RY

DS

P5

6F

82

7E

VM

.DS

N

1.0

410

Mon

day,

Apr

il 09

, 20

01A

DS

P S

tan

dar

d P

rod

uct

s D

ivis

ion

2100

Eas

t E

lliot

Roa

dT

empe

, A

rizo

na 8

5284

Titl

e

Do

cum

en

t

Da

te:

Siz

e

De

sig

ner

:S

he

et

of

Re

v.N

um

be

r

(480

) 41

3-50

90

F

AX

: (4

80)

413-

2510

/RE

S

/WP

/RE

S

/WP

EE

_S

O

EE

_S

I

EE

_S

CK

/EE

_C

S/S

S

MIS

O

MO

SI

SC

LK

+3

.3V

+3

.3V

R9

01

0K

R9

11

0K

JG7

1 3 5 7

2 4 6 8

U4

AT

45

DB

01

1-S

C

1846 3 5 7

2

SI

SO

CS

VC

C

RE

SE

T

WP

GN

DS

CK

Appendix A, Rev. 2


Fig

ure

A-4

.

SP

I S

eri

al

1M

-bit

Seri

al

EE

PR

OM

Mem

ory

A A

B B

C C

D D

E E

44

33

22

11

RS

-232

EN

AB

LE

1 - 2

N/C

RS-232 ENABLE

RS-232 DISABLE

CONNECTOR

CTS

DSR

DTR

RXD

TXD

RTS

DCD

SCI

RS-232RI

GND

DS

PD

Des

ign

SC

I P

OR

T,

RS

-23

2 A

ND

CO

NN

EC

TO

R

DS

P5

6F

82

7E

VM

.DS

N

1.0

510

Mon

day,

Apr

il 09

, 20

01A

DS

P S

tan

dar

d P

rod

uct

s D

ivis

ion

2100

Eas

t E

lliot

Roa

dT

empe

, A

rizo

na 8

5284

Titl

e

Do

cum

en

t

Da

te:

Siz

e

De

sig

ner

:S

he

et

of

Re

v.N

um

be

r

(480

) 41

3-50

90

F

AX

: (4

80)

413-

2510

R4

IN

R5

IN

R2

IN

R3

IN

T3

IN

/EN

T2

IN

T2

INT

3IN

/EN

R3

INR

4IN

R5

IN

R2

IN

TX

D0

RX

D0

+3

.3V

+3

.3V

+3

.3V

R6

11

K

R6

21

K

R6

01

K

R5

91

K

R5

61

K

R5

81

K

R5

51

K

JG2 1 2

R5

71

K

T1

11

T1

21

T1

31

T1

41

P3

594837261

T9

1T

81

T1

51

T1

01

U3 M

AX

32

45

EE

AI

27

1

26

2

23

28

14

13

12

19

18

17

16

15

8765411

10

9

22

24

3 25

20

21

V+

C2

+

VC

C

C2

-

FO

RC

EO

N

C1

+

T1

INT

2IN

T3

IN

R1

OU

TR

2O

UT

R3

OU

TR

4O

UT

R5

OU

TR

5IN

R4

INR

3IN

R2

INR

1IN

T3

OU

TT

2O

UT

T1

OU

T

FO

RC

EO

FF

C1

-V

-

GN

D

R2

OU

TB

INV

AL

ID

R8

80

Oh

m

R8

90

Oh

m

C2

7

C2

81

.0u

F

C2

61

.0u

F

C2

91

.0u

F



Fig

ure

A-5

.

SC

I P

ort

, R

S-2

32 a

nd

Co

nn

ecto

r

A A

B B

C C

D D

E E

44

33

22

11

MF6

MF7

MF8

FS (KHZ)

00

0

00

00

0

00

0

01

1 11 1

1 1

11 1

11

48.00

32.00

24.00

19.20

16.00

12.00

9.60

8.00

SERIAL MODE 4 SELECTED

MASTER, 32BITS PER FRAME

Line

Out

Ster

eo J

ack

Line

-Inpu

tSt

ereo

Jac

k

Sam

ple

Sele

ct

Head

phon

e Ou

t S

tere

o Ja

ck

DSP

D D

esig

n

SS

I 16-

BIT

STE

RE

O C

OD

EC

DS

P56

F827

EV

M.D

SN

1.0

610

Mon

day,

Apr

il 09

, 200

1B

DS

P S

tand

ard

Pro

duct

s D

ivis

ion

2100

Eas

t Elli

ot R

oad

Tem

pe, A

rizon

a 85

284

Title

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:S

heet

of

Rev

.N

umbe

r

(480

) 41

3-50

90

FAX

: (48

0) 4

13-2

510

MF

1

CO

DE

C_F

SY

NC

CO

DE

C_S

DO

UT

RIN

G_I

N

CD

IN

/PD

N

TIP

_IN

CO

DE

C_S

CLK

12.2

88M

HZ

LOU

T

RIN

G_O

UT

RO

UT

CC

LK

CO

DE

C_S

DIN

MF

5/C

CS

/CO

DE

C_R

ES

ET

/CO

DE

C_R

ES

ET

/CC

S

CD

IN

CC

LK

CO

DE

C_S

CLK

CO

DE

C_S

DIN

CO

DE

C_S

DO

UT

CO

DE

C_F

SY

NC

/CC

S

MF

5

MF

1

MF

8

MF

7

MF

6

MO

DE

3

MO

DE

2

MO

DE

1

/PD

N

MF

6M

F7

MF

8

MO

DE

3M

OD

E2

MO

DE

1

SH

UT

DN

LOU

T

RO

UT

SH

UT

DN

BY

PA

SS

MF7

MF8

MF6

TIP

_OU

T

RIN

G_P

HN

TIP

_PH

N

MO

DE

1

MO

DE

2

MO

DE

3

SR

D

ST

D

ST

CK

ST

FS

PD

0

PD

1

PD

2

PD

3

12.2

88M

HZ

+5.0

VA

+3.3

V

+3.

3V

+3.

3V

+3.3

V

+5.0

VA

R31

5.62

K1%

C17

0.47

uF

R34

39.2

K1%

R32

5.62

K1%

C21

0.47

uF

C10

470p

F

R33

5.62

K1%

C15

0.00

22uF

R35

39.2

K1%

C14

0.33

uF

C12

470p

F

C16

0.00

22uF

R30

5.62

K1%

C18

0.47

uF

C8

0.33

uF

R53

0 O

hm

R54

0 O

hm

R52

0 O

hm

R48

0 O

hm

U7

12.2

88M

HZ

OS

C

18 4

5E

N

VC

C

GN

D

OU

T

R41

1K

R47

0 O

hm

R50

0 O

hm

R49

0 O

hm

R51

0 O

hm

R36

10K

R37

10K

R42

10K

R86

1K

R44

10K

R45

10K

R43

10K

R85

10K

R84

10K

R83

10K

R82

10K

C9

0.1u

F+

C7

47uF

10V

DC

R87

10K

C11

1uF

25V

C13

1uF

25V

C25

1uF

25V

P4 1/

8"

11 2 13 10P

5

1/8"

11 2 13 10

P6

1/8"

11 2 13 10

C20

1uF

25V

C19

1uF

25V

R39

20.0

K1% R

38

20.0

K1%

R46

20.0

K1%

R40

20.0

K1%

+

C24

47uF

10V

DC

+

C23

47uF

10V

DC

U6 LM

4880

M

26

17 8 453

IN_A

IN_B

OU

T_A

OU

T_B

VD

D

GN

DS

HU

TD

N

BY

PA

SS

R96

0 O

hm

R97

0 O

hm

R98

0 O

hm

DN

P

S4

6 4 2

5 3 1

U5 C

S42

18-K

Q

24 3525

41

28 2632 23

40

30

7 39

29

38

33

37 36

34 15 169 10

20 222119 14 18 17

42 43

WF

8

SW

OD

E3

WF

7

CLK

IN

WF

6

SW

OD

E2

MF

5

SW

OD

E1

RE

SE

T

MF

4

PD

NS

SY

NC

MF

3

SC

LK

MF

2

SD

OU

TS

DIN

MF

1

RE

FB

Y

RE

FG

ND

RO

UT

LOU

T

RIN

2

LIN

2

LIN

1

RIN

1

RE

FB

UF

VD

DA

GN

DA

VD

D

GN

D

Appendix A, Rev. 2


Fig

ure

A-6

. S

SI 16-B

it S

tere

o C

od

ec

A A

B B

C C

D D

E E

44

33

22

11

Parallel JTAG Interface

KEY

JTAG Connector

On-Board

Host Target Interface

Disable

PO

RT

_VC

C

PO

RT

_DE

DSP

D D

esig

n

PA

RA

LLE

L JT

AG

HO

ST

TAR

GE

T IN

TER

FAC

E A

ND

JTA

G C

ON

NE

CTO

R

DS

P56

F827

EV

M.D

SN

1.0

710

Mon

day,

Apr

il 09

, 200

1B

DS

P S

tand

ard

Pro

duct

s D

ivis

ion

2100

Eas

t Elli

ot R

oad

Tem

pe, A

rizon

a 85

284

Title

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:S

heet

of

Rev

.N

umbe

r

(480

) 41

3-50

90

FAX

: (48

0) 4

13-2

510

/J_R

ES

ET

P_R

ES

ET

/J_T

RS

T

/J_R

ES

ET

TD

O

P_R

ES

ET

TMS

TC

K

TD

I

/J_T

RS

T

TD

O

PO

RT

_TD

O

PO

RT

_TM

S

/PO

RT_

TRS

T

PO

RT

_TC

K

PO

RT

_TD

I

PO

RT

_CO

NN

EC

T

PO

RT

_RE

SE

T

PO

RT

_ID

EN

T

/J_T

RS

T

/J_R

ES

ET

/J_T

RS

T

/PO

R

TD

IT

DO

TC

K

TMS

/RE

SE

T

/TR

ST

/PO

R

+3.3

V

+3.3

V

+3.3

V

+3.

3V

+3.3

V

R21

51 O

hm

R25

5.1K

R24

5.1K

J3 135791113

2468101214

R26

47K

R28 47

K

R15

270

R17

270

R16

270

R19

270

R18

270

R23

5.1K

JG1

12

U8

MC

74LC

X24

4AD

W

18 16 14 12 9

7 5 3 1912 4 6 8 11

13 15 17

20

10

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

2G1G1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

VC

C

GN

D

T71

R20 5.1K

P2 DB

25M

1 321514 16

417

518

619

720

821

922

1023

1124

1225

13R

22

51 O

hm

R29 47

K

U9A

74A

C00

1 23

U9B

74A

C00

4 56

U9C

74A

C00

9 108

U9D

74A

C00

12 1311

R27 47

K

Q1

2N22

22A



Fig

ure

A-7

. P

ara

llel JT

AG

Ho

st

Targ

et

Inte

rface a

nd

JT

AG

Co

nn

ecto

r

A A

B B

C C

D D

E E

44

33

22

11

Daughter Address/Data Connector

Daughter Peripheral Port Connector

A16/GND

A17/GND

A18/GND

A19/GND

A20

CS2/GND

CS3/GND

/CS0

/CS1

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DS

PD

Des

ign

DA

UG

HT

ER

CA

RD

EX

PA

NS

ION

CO

NN

EC

TO

RS

DS

P5

6F

82

7E

VM

.DS

N

1.0

810

Mon

day,

Apr

il 09

, 20

01A

DS

P S

tan

dar

d P

rod

uct

s D

ivis

ion

2100

Eas

t E

lliot

Roa

dT

empe

, A

rizo

na 8

5284

Titl

e

Do

cum

en

t

Da

te:

Siz

e

De

sig

ner

:S

he

et

of

Re

v.N

um

be

r

(480

) 41

3-50

90

F

AX

: (4

80)

413-

2510

GN

DG

ND

GN

D

GN

D

GN

DG

ND

GN

DG

ND

GN

D

D0

D2

D4

D6

D8

D1

4

A0

A2

A6

A8

A1

4

/RD

/WR D1

D3

D5

D7

D9

D1

3

D1

5

A5

A7

A9

A1

3

A1

5

/PS A1

/DS

A1

0A

11

A1

2

A3

A4

D1

0D

11

D1

2M

ISO

SC

LK

TX

D1

SR

DS

RF

S

SR

CK

/RE

SE

T

/IR

QA

PB

2P

B0

PB

4

PB

6

PD

6

PD

4

PD

0

PD

2M

OS

I

/SS

RX

D0

RX

D1

ST

D

ST

FS

ST

CK

/IR

QB

CL

KO

PB

1

PB

3

PB

5

PB

7

PD

1

PD

3

PD

5

PD

7

TX

D0

TA

0

TA

2

TA

1

TA

3

PC

S3

PC

S2

PC

S4

PC

S5

PC

S6

PC

S7

AN

A0

AN

A2

AN

A4

AN

A6

AN

A1

AN

A3

AN

A5

AN

A7

AN

A8

AN

A9

+3

.3V

+3

.3V

+3

.3V

+3

.3V

J1

1 3 5 7 9 11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

2 4 6 81

01

21

41

61

82

02

22

42

62

83

03

23

43

63

84

04

24

44

64

85

05

1

J2

1 3 5 7 9 11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

2 4 6 81

01

21

41

61

82

02

22

42

62

83

03

23

43

63

84

04

24

44

64

85

05

1

Appendix A, Rev. 2


Fig

ure

A-8

.

Dau

gh

ter

Card

Exp

an

sio

n C

on

necto

rs

A A

B B

C C

D D

E E

44

33

22

11

EXTERNAL POWER INPUT

7-12VDC/AC

12

3

4

MC33269

5.0V, 3.3V

& Adj

REGULATOR

POWER GOOD LED

Vout = 1.25( 1 + (Rhigh/Rlow))

Rhigh = 243 1% for 2.5V

Rlow

Rhigh

INPUT

+5VDC

+ -

DS

PD

Des

ign

PO

WE

R S

UP

PL

IES

DS

P5

6F

82

7E

VM

.DS

N1.

09

10M

onda

y, A

pril

09,

2001

A

DS

P S

tan

dar

d P

rod

uct

s D

ivis

ion

2100

Eas

t E

lliot

Roa

dT

empe

, A

rizo

na 8

5284

Titl

e

Do

cum

en

t

Da

te:

Siz

e

De

sig

ner

:S

he

et

of

Re

v.N

um

be

r

(480

) 41

3-50

90

F

AX

: (4

80)

413-

2510

+5

.0V

+5

.0V

A

+3

.3V

+3

.3V

+2

.5V

+5

.0V

+5

.0V

+3

.3V

A

V C

C

C4

0.1

uF

C6

0.1

uF

U1

0

MC

33

26

9D

T-3

.3

32 4

1

VIN

VO

UT

VO

UT

GN

D

L1

FE

RR

ITE

BE

AD

L3

FE

RR

ITE

BE

AD

L2

FE

RR

ITE

BE

AD

+C

54

7u

F1

0V

DC

R2

47

0

C5

50

.1u

F

U1

3

MC

33

26

9D

T-A

DJ

32 4

1

VIN

VO

UT

VO

UT

GN

D

R9

42

43

1%

R9

52

43

1%

+C

57

47

uF

10

VD

C

L4

FE

RR

ITE

BE

AD

+C

56

47

uF

10

VD

C

TB

1 1 2

LE

D7

P1

13

2

U1

4

MC

33

26

9D

T-5

32 4

1

VIN

VO

UT

VO

UT

GN

D+

C3

47

0u

F1

6V

DC

-+

D4

51

84

D3

FM

40

01

D1

FM

40

01

D2

FM

40

01

L5

FE

RR

ITE

BE

AD

+C

58

47

uF

10

VD

C



Fig

ure

A-9

.

Po

we

r S

up

pli

es

A A

B B

C C

D D

E E

44

33

22

11

DSP56F827

74AC04

74AC00

GS72116

DS1818

MAX3245

AT45DB011

74LCX244

CS4218

OSC

LM4880

TEST POINTS

GROUND

ANALOG GROUND

TEST POINT

TEST POINT

TEST POINT

+5.0VA

+3.3V

TEST POINT

+2.5V

DS

PD

Des

ign

BY

PA

SS

CA

PS

DS

P5

6F

82

7E

VM

.DS

N1.

010

10M

onda

y, A

pril

09,

2001

A

DS

P S

tan

dar

d P

rod

uct

s D

ivis

ion

2100

Eas

t E

lliot

Roa

dT

empe

, A

rizo

na 8

5284

Titl

e

Do

cum

en

t

Da

te:

Siz

e

De

sig

ner

:S

he

et

of

Re

v.N

um

be

r

(480

) 41

3-50

90

F

AX

: (4

80)

413-

2510

+3

.3V

+3

.3V

+2

.5V

+2

.5V

+2

.5V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

A+

3.3

VA

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+3

.3V

+5

.0V

A

+5

.0V

A+

3.3

V+

2.5

V

+3

.3V

A

C4

1

0.0

1u

F

C4

2

0.1

uF

C3

9

0.0

1u

F

C3

5

0.0

1u

F

C3

7

1.0

uF

C3

3

0.0

1u

F

C3

6

0.1

uF

C3

4

0.1

uF

C3

8

0.1

uF

C4

0

1.0

uF

C4

9

0.0

1u

FD

NP

C4

5

0.0

1u

F

C4

3

0.0

1u

F

C4

6

0.1

uF

C4

4

0.1

uF

C4

8

0.1

uF

C5

0

0.1

uF

C5

1

0.1

uF

C5

2

0.0

1u

F

C5

3

0.1

uF

C5

4

0.0

1u

F

C2

2

0.1

uF

TP

31

TP

41

TP

51

TP

2

1

TP

1

1

TP

6

1

TP

7

1

C5

9

1.0

uF

Appendix A, Rev. 2


Fig

ure

A-1

0.

B

yp

ass C

ap

s

Appendix B, Rev. 2

Freescale Semiconductor B-1

Appendix B56F827EVM Bill of Material

Qty. Description Ref. Designators Vendor Part #s

Integrated Circuits

1 DSP56F827FG80 U1 Freescale, DSP56F827FG80

1 GS72116 U2 GSI, GS72116TP-12

1 MAX3245 U3 Maxim, MAX3245EEAI

1 AT45DB011 U4 Atmel, AT45DB011-SC

1 CS4218 U5 Crystal Semiconductor, CS4218-KQ

1 LM4880 U6 National Semiconductor, LM4880M

1 12.288MHZ OSC U7 Epson, SG-531P-12.288MC

1 74LCX244 U8 ON Semiconductor, MC74LCX244ADW

1 74AC00 U9 Fairchild, 74AC00SC

1 +3.3V Voltage Regulator U10 ON Semiconductor, MC33269DT-3.3

1 74AC04 U11 ON Semiconductor, MC74AC04AD

1 +2.5V Voltage Regulator U13 ON Semiconductor, MC33269DT-ADJ

1 +5.0V Voltage Regulator U14 ON Semiconductor, MC33269DT-5

Resistors

1 10M R1 SMEC, RC73L2A10MOHMJT

1 470 R2 SMEC, RC73L2A470OHMJT

11 270 R3, R6, R9, R11, R13 - R19 SMEC, RC73L2A270OHMJT

10 47K R4, R5, R7, R8, R10, R12, R26 - R29 SMEC, RC73L2A47KOHMJT

4 5.1K R20, R23 - R25 SMEC, RC73L2A5.1KOHMJT


B-2 Freescale Semiconductor

Resistors (Continued)

2 51 R21, R22 SMEC, RC73L2A51OHMJT

4 5.62K R30 - R33 SMEC, RC73L2A5.62KOHMFT

2 39.2K R34, R35 SMEC, RC73L2A39.2KOHMFT

19 10K R36, R37, R42 - R45, R67, R70 - R72, R82 - R85, R87, R90 - R93

SMEC, RC73L2A10KOHMJT

4 20.0K R38 - R40, R46 SMEC, RC73L20.0KOHMFT

12 1K R41, R55 - R62, R68, R69, R86 SMEC, RC73L2A1KOHMJT

12 R47 - R54, R88, R89, R96, R97 SMEC, RC73JP2A

2 243 1% R94, R95 SMEC, RC73L243OHMFT

Inductors

4 1.0mH FERRITE BEAD L1, L2, L3, L4 Panasonic, EXC-ELSA35V

LEDs

2 Red LED LED1, LED4 Hewlett-Packard, HSMS-C650

2 Yellow LED LED2, LED5 Hewlett-Packard, HSMY-C650

3 Green LED LED3, LED6, LED7 Hewlett-Packard, HSMG-C650

Diode

2 S2B-FM401 D1, D2, D3 Vishay, DL4001DICT

1 1Amp Bridge Rectifier D4 General Semiconductor, DF02S

Capacitors

1 470 F, +16V DC C3 ELMA, RV-16V471MH10R

18 0.1 F C4, C6, C9, C22, C30 - C32, C34, C36, C38, C42, C44, C46, C48, C50,

C51, C53, C55

SMEC, MCCE104K2NR-T1

7 47 F, +16V DC C5, C7, C23, C24, C56, C57, C58 ELMA, RV2-16V470M-R

2 0.33 F C8, C14 SMEC, MCCE334K3NR-T1

2 470pF C10, C12 SMEC, MCCE471J2NO-T1

12 1.0 F, +25V DC C11, C13, C19, C20, C25 - C29, C37, C40, C59



Appendix B, Rev. 2

Freescale Semiconductor B-3

Capacitors (Continued)

2 0.0022 F C15, C16 SMEC, MCCE222K2NR-T1

3 0.47 F C17, C18, C21 SMEC, MCCE474K3NR-T1

9 0.01 F C33, C35, C39, C41, C43, C45, C49, C52, C54


Jumpers

4 1 2, 2mm Header JG1 - JG3, JG6 SAMTEC, TMM-102-03-S-S

2 3 1, 2mm Header JG4, JG5 SAMTEC, TMM-103-03-S-S

1 4 2, 2mm Header JG7 SAMTEC, TMM-104-03-S-D

Test Points

7 1 1, Pin TP1 - TP7 Samtec, TSW-101-06-S-S

Crystals

1 4.00MHz Crystal Y1 CTS, ATS04ASM-T

Connectors

1 2.1mm coaxPower Connector

P1 Switchcraft, RAPC-722

1 DB25M Connector P2 AMPHENOL, 617-C025P-AJ121

1 DE9S Connector P3 AMPHENOL, 617-C009S-AJ120

3 1/8” Stereo Jack P4 - P6 Switchcraft, 35RAPC4BHN2

2 51-Pin HD Connector J1, J2 FCI Framatome Conn, 91930-21151

1 7 x 2 Bergstick J3 SAMTEC, TSW-107-07-S-D

1 2-Pin Terminal Block TB1 On-Shore Technology, ED500/2DS

Switches

3 SPST Pushbutton S1 - S3 Panasonic, EVQ-PAD05R

1 3-Position DIP SW S4 CTS, 209-3LPST

Transistors

1 2N2222A Q1 ZETEX, FMMT2222ACT



B-4 Freescale Semiconductor

Miscellaneous

8 2mm Shunt SH1–SH8 Samtec, 2SN-BK-T

4 Rubber Feet RF1–RF4 3M, SJ5018BLKC


INDEX

Index, Rev. 2

Freescale Semiconductor Index - i

Numerics

1.2A power supply 2-14

16-bit 2.5V/3.3V hybrid controller 2-1

16-bit stereo codec interface 2-1

1M-bit Serial EEPROM 2-1

4.00MHz crystal oscillator 2-1

64Kx16 bits of data memory 2-1

64Kx16 bits of program memory 2-1

C

Codec Preface-ix

D

Data memory 2-3

Daughter Card Expansion interface 2-1

Debugging 2-8

Development Card 2-1

E

EEPROM

EEPROM Preface-ix

Electrically Erasable Programmable Read Only

Memory Preface-ix

Evaluation Module Preface-ix

EVM

EVM Preface-ix

External oscillator frequency input 2-1

F

FSRAM 2-1, 2-3

G

General Purpose Input/Output port Preface-ix

GPIO 2-2

GPIO Preface-ix

H

Host Parallel Interface Connector 2-8

Host Target Interface 2-8

I

IC

IC Preface-ix

Integrated Circuit Preface-ix

J

Joint Test Action Group Preface-ix

JTAG 1-1, 2-1

connector 2-9

JTAG Preface-ix

JTAG port interface 2-1

Jumper Group 1-3

JG1 1-3

JG2 1-3

JG3 1-3

JG4 1-3

JG5 1-3

JG6 1-3

JG7 1-3

L

Low-profile Quad Flat Pack Preface-ix

LQFP

LQFP Preface-ix

M

MPIO

MPIO Preface-ix

Multi-Purpose Input/Output port Preface-ix

O

On-board power regulation 2-2

OnCE 1-1

OnCE(TM)

OnCE Preface-ix

On-Chip Emulation Preface-ix

Operating Mode 2-7


Index - ii Freescale Semiconductor

P

Parallel JTAG Host Target Interface 2-1

PCB

PCB Preface-ix

Phase Locked Loop Preface-ix

PLL

PLL Preface-ix

Printed Circuit Board Preface-ix

Program memory 2-3

R

RAM

RAM Preface-ix

Random Access Memory Preface-ix

Read-Only Memory Preface-ix

Real-time debugging 2-8

ROM

ROM Preface-ix

RS-232

interface 2-1, 2-5

level converter 2-5

schematic diagram 2-5

RS-232 interface 2-1

S

SCI

SCI Preface-ix

SCI-compatible peripheral 2-2

Serial Communications Interface port Preface-ix

Serial Peripheral Interface port Preface-ix

SPI 2-2

SPI Preface-ix

SRAM

external data 2-1

external program 2-1

SRAM Preface-ix

SSI 2-2

SSI Preface-ix

Static Random Access Memory Preface-ix

Stereo 16-bit codec interface 2-1

Stereo headphone interface 2-1

Synchronous Serial Interface port Preface-ix

W

Wait State Preface-ix

WS

WS Preface-ix

How to Reach Us:

Home Page:www.freescale.com

E-mail:[email protected]

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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor,

Inc. All other product or service names are the property of their respective owners.

This product incorporates SuperFlash® technology licensed from SST.

© Freescale Semiconductor, Inc. 2005. All rights reserved.

DSP56F827EVMUMRev. 207/2005

Information in this document is provided solely to enable system and

software implementers to use Freescale Semiconductor products. There are

no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits or integrated circuits based on the

information in this document.

Freescale Semiconductor reserves the right to make changes without further

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incidental damages. “Typical” parameters that may be provided in Freescale

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