Dsp48 Numbers Rounding 1
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Transcript of Dsp48 Numbers Rounding 1
T i i CTraining Courseon
Advance FPGA based Digital System Design
by
Fahad Al Ghazali
(Ministry of Professional & Technical Training Govt. of Pakistan)*Organized by Skill Development Council Islamabad
Xilinx Xtreme DSPXilinx Xtreme DSP ArchitectureArchitecture
DSP I l t tiDSP Implementation
Digital Signal Processing can be implemented in both hardware and psoftwareSoftware based approach implements inSoftware based approach implements in general purpose ProcessorPrograms the processor for the tasks ofPrograms the processor for the tasks of particular application
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
DSP I l t ti (2)DSP Implementation (2)
Second approach is to use a special purpose , hard wired high performance , p p , g p ,customized processor whose architecture supports special signal processing tasks in pp p g p gform of libraries
e.g. Texas Instruments, Tiger Shark, Da Vincie.g. Texas Instruments, Tiger Shark, Da Vinci etc.
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
DSP I l t ti (3)DSP Implementation (3)
Application Specific Integrated circuits can be fabricated for a unique .qFeasible only if large number of units are requiredrequired
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
DSP I l t ti (4)DSP Implementation (4)
DSP on FPGAsBenefitsBenefits
Reduced Chip count in case design already requires programmable logicrequires programmable logicUseful in case of greater number of channelsFlexibilityFlexibility Debugging
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
DSP D i Ch llDSP Design Challenges
High ThroughputMultiple Concurrent operationsMultiple Concurrent operationsMultiple ALUs R i t f M i MACRequirement of Memories , MACs
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
DSP T i l O tiDSP Typical Operations
DSP operate on fixed-word length data that arrive at regular intervals of timeMultiplication and Addition commonly knownMultiplication and Addition commonly known as MAC operationMAC functional units must be implementedMAC functional units must be implemented efficiently and must give high performanceFloating point/ Fixed point arithmeticsMemory read/writeNumber of channels
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
Ti iTiming The operations can be distributed spatially inThe operations can be distributed spatially in different blocks or one block . Depends upon how many clock cycles we have before next y ysampleIn case whole of the binary word is being y gprocessed at the same time, then hardware resources ensure in- time delivery of the resultsThe operations can be distributed over latency factor i.e. time between first input and first valid
t tFPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
output
High Speed processingHigh Speed processing requirement in DSP algorithms
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )10
*Source: Jan Rabaey, BWRC
DSP Architecture Support inDSP Architecture Support in Xilinx FPGAs
Today’s FPGA architecture address DSP implementation issues and offer specialized architectures. Reasons:
Market is flowing more towards reduced chip count solution to decrease the the sizes of devicessolution to decrease the the sizes of devicesTo extract market share of devices used in booming communication industryyTo exploit the parallel architecture offered by FPGAs
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )11
DSP ti i FPGADSP options in FPGAs
The options are DSP48 slice introduction in architectureDSP48 slice introduction in architectureBuilt in cores of DSP functions so that user does not have to start design from scratchgOn-chip soft/hard processor I.Ps with Floating point unit and support for C
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )12
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
Xtreme DSP : DesignXtreme DSP : Design Considerations
The DSP48 slice is a new element in the Xilinx development model referred to as Application Specific Modular Blocks (ASMBL™) architectureModular Blocks (ASMBL™) architectureDelivers off-the-shelf programmable devices with the best mix of logic, memory, I/O, processors, clock g y pmanagement, and digital signal processingEach XtremeDSP tile contains two DSP48 slices to form the basis of a versatile coarse grain DSP architecturethe basis of a versatile coarse-grain DSP architectureSupport independent functions, including multiplier, multiplier-accumulator (MACC), multiplier followed by an
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
p ( ), p yadder, three-input adder, barrel shifter,
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DSP48 A hit tDSP48 Architecture
The DSP48 slice is an 18 x 18 bit two’s complement multiplier followed by a 48-bit sign-extended adder/subtracter/accumulator, a function that is widely used in digital signal processing (DSP)processing (DSP)Its predecessors which came in Spartan –III/IIIE were with the name of MULT18x18were with the name of MULT18x18Inherent Pipeline bases architecture enhanced throughput
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
throughput48-bit bus internal offers high aggregation
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FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
F tFeatures
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
Xilinx XtremeDSPStarting with Virtex 4 family, Xilinx introduced DSP48 block for high-speed DSP on FPGAsEssentially a multiply-accumulate core with many other featuresNow also Spartan 3A and Virtex 5 have DSP blocksNow also Spartan-3A and Virtex 5 have DSP blocks
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
Xtreme DSP Interconnect in VirtexXtreme DSP Interconnect in Virtex
DSP48 and Block RAM have dedicated interconnect
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
to prevent interconnect bandwidth issues
F tFeatures 1. The 18-bit A bus and B bus are concatenated, with the A bus being
the most significant.2. The X,Y, and Z multiplexers are 48-bit designs. Selecting any of the2. The X,Y, and Z multiplexers are 48 bit designs. Selecting any of the
36-bit inputs provides a 48-bit sign-extended output.3. The multiplier outputs two 36-bit partial products, sign extended to 48
bits. The partial products feed the X and Y multiplexers. Whenbits. The partial products feed the X and Y multiplexers. When OPMODE selects the multiplier, both X and Y multiplexers are utilized and the adder/subtracter combines the partial products into a valid multiplier result.
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )25
F tFeatures4. The multiply-accumulate path for P is through the Z multiplexer. The
P feedback through the X multiplexer enables accumulation of P cascade when the multiplier is not used
5. The Right Wire Shift by 17 bits path truncates the lower 17 bits, and sign extends the upper 17 bits
6. The gray-colored multiplexers are programmed at configuration time6. The gray colored multiplexers are programmed at configuration time7. The shared C register supports multiply-add, wide addition, or
rounding8 Enabling SUBTRACT implements Z – (X+Y+CIN) at the output of the8. Enabling SUBTRACT implements Z – (X+Y+CIN) at the output of the
adder/subtracter
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )26
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
Si lifi d DSP Sli M d lSimplified DSP Slice Model
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )32
A i t L iA input Logic
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )33
B i t l iB input logic
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )34
C i t L iC input Logic
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )35
P t t L iP output Logic
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )36
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
DSP48 Slice: Virtex 4
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
DSPDSP48 TilTile
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )40
DSP48E Slice : Virtex5
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
DSP48 F ti litDSP48 Functionality
Full speed operation is 500 MHz when using the pipeline registersEquation 1 1 summarizes the combination of XEquation 1-1 summarizes the combination of X, Y, Z, and CIN by the adder/subtracter.
The CIN, X multiplexer output, and Y multiplexer output are always added togetheroutput are always added together. This combined result can be selectively added to or subtracted from the Z multiplexer output.Add O t (Z (X Y CIN))Adder Out = (Z ± (X + Y + CIN))
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
DSP48 F ti litDSP48 FunctionalityA and B are multiplied and the result is added to or subtracted from the C register. Selecting the multiplier function consumes both X and Y multiplexer outputs to f d th ddfeed the adder.
The two 36-bit partial products from the multiplier are sign extended to 48 bits before being sent to the adder/subtracter.Adder Out = C ± (A × B + CIN)Adder Out = C ± (A × B + CIN)
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
Si lifi d F f DSP48Simplified Form of DSP48
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
M th ti l F tiMathematical FunctionsDSP 48 can perform mathematical functions such as:
Add/SubtractAccumulateMultiplyp yMultiply-AccumulateMultiplexerBarrel ShifterCounterDi id ( lti l )Divide (multi-cycle)Square Root (multi-cycle)
Can also create filters such as:Serial FIR Filter (Xilinx calls this MACC filters)P ll l FIR FiltParallel FIR FilterSemi-Parallel FIR FilterMulti-rate FIR Filters
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
MACC Filter
Xilinx implementation of a serial FIR filter called a MACC ( lti l l t filt )MACC (multiply accumulate filter)This example has 96 coefficientsMax input sample rate = clock speed / number of t
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
p p ptaps
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )47
DSP 48E1 i Vi t 6DSP 48E1 in Virtex-6
Enhancements to the DSP48E1 slice provide improve flexibility and utilization, improved efficiency of applications, reduced overall power consumption, and increased maximum frequencyfrequency. The high performance allows designers to implement multiple slower operations in a singleimplement multiple slower operations in a single DSP48E1 slice using time-multiplexing methods
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
F t f DSP48E1Features of DSP48E1The DSP48E1 slice supports many independent functions. These functions include :
Multiplyp yMultiply accumulate (MACC)Multiply addThree-input add ee pu addBarrel shift Wide-bus multiplexing Magnitude comparatorMagnitude comparator Bit-wise logic functions, pattern detect, and wide counter
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
Vi t 6 DSP 48E1 SliVirtex-6 DSP 48E1 Slice
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
E h d F tEnhanced FeaturesThe Virtex 6 FPGAThe Virtex-6 FPGA DSP48E1 slice includes all Virtex-5 FPGA DSP48EFPGA DSP48E features plus a variety of enhancements
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
E h d F t (C t’d)Enhanced Features (Cont’d)
The enhanced features in the Virtex-6 FPGA DSP48E1 slice are:
25 bit dd ith D i t t h th• 25-bit pre-adder with D register to enhance the capabilities of the A path• INMODE control supports balanced pipelining when INMODE control supports balanced pipelining when dynamically switching betweenmultiply (A*B) and add operations (A:B)
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
DSP48E1 Tile and InterconnectDSP48E1 Tile and Interconnect
Two DSP48E1 slices and dedicatedTwo DSP48E1 slices and dedicated interconnect form a DSP48E1 tile .The DSP48E1 tiles stack vertically in a DSP48E1 column. The height of a DSP48E1 tile gis the same as five configurable logic blocks (CLBs) and also matches the height of one block RAM. Th bl k RAM i Vi t 6 d i b litThe block RAM in Virtex-6 devices can be split into two 18K block RAMs. Each DSP48E1 slice aligns horizontally with an 18K block RAM. Virtex-6 family members have 1 2 6 or 10Virtex 6 family members have 1, 2, 6, or 10 DSP48E1 columns.
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
No. of DSP48E1 Slices offeredNo. of DSP48E1 Slices offered in Virtex-6 Family
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
SMU CSE 5349/7349
DSP48E1 Sli P i itiDSP48E1 Slice Primitive
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
CSE 5349/7349
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
A ith tiArithmetics ….
Floating point/Fixed Point Double/single precisionDouble/single precisionSquare Root, Multiply, Divide(float/fixed)M t h ith MATLAB lt i th tMatch with MATLAB results in the next session …..
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )58
Fi d P i t R t tiFixed Point Representation
Qn.m FormatN bits are in integer part and 5 bits are inN bits are in integer part and 5 bits are in mantissa part 10/15 = 0000000 1 0 1 0 1 0 110/15 = 0000000….. . 1 0 1 0 1 0 1
Weights of mantissa part-1 -2 -3 -4 -5 -6 -70.5+0.125+0.03125
+0.015625 = 0.6666777
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )59
Fi d P i t Di id i CFixed Point Divider via Coregen
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )60
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
Optimize Your Design forXili A hiXilinx ArchitectureCORE Generator Systemy
What are Cores?What are Cores?
A core is a ready-made function that you can instantiate into your design
as a “black box”as a black box• Cores can range in complexity– Simple arithmetic operators, such as adders, accumulators, and
multipliersmultipliers– System-level building blocks, including filters, transforms, and
memoriesSpecialized functions such as bus interfaces controllers and– Specialized functions, such as bus interfaces, controllers, and
microprocessors• Some cores can be customized
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )65
Benefits of Using CoresBenefits of Using Cores
Save design timeCores are created by expert designers who have in-depth knowledge of Xilinx FPGA architectureknowledge of Xilinx FPGA architectureGuaranteed functionality saves time during simulationIncrease design performanceCores that contain mapping and placement information haveCores that contain mapping and placement information have predictableperformance that is constant over device size and utilization
f fThe data sheet for each core provides performance expectationsUse timing constraints to achieve maximum performance
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )66
What is the COREWhat is the COREGenerator System?Graphical User Interface (GUI) that allows central access to the coresthemselves, plus:– Data sheets– Data sheets– Customizable parameters (available for some cores)• Interfaces with design entry tools– Creates graphical symbols for schematic-based designs– Creates instantiation templates for HDL-based designs• Web access from the Help menu– The IP Center contains new cores to download and install• You always have access to the latest cores– Direct access to http://support xilinx com
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
Direct access to http://support.xilinx.com
67
Invoking the COREInvoking the COREGenerator Systemselect Project → New Source• Select IP (CoreGen & Select IP (CoreGen &Architecture Wizard) and
t filenter a filename• Click Next, then select the typeof core
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )68
C G t GUICore Generator GUI
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )69
Xilinx CORE GeneratorXilinx CORE GeneratorSystem GUI
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )70
Core Customize WindowCore Customize Window
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )71
CORE Data SheetsCORE Data Sheets
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )72
Schematic Design FlowSchematic Design Flow
Generate a core– Use the Edit → ProjectOptions to select a schematicpsymbol instead of HDLtemplates– Creates an EDIF file andschematic symbol• Instantiate symbol onto yourschematic– Treated as a “black box” - nounderlying schematic• Proceed with normal
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
schematic flow
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HDL Design Flow:HDL Design Flow:Compile Simulation LibraryBefore your first behavioral simulation, you must run
compxlib.exe toil th Xili C Lib i l ti libcompile the XilinxCoreLib simulation library
– Located in $XILINX\bin\<platform>– Supports ModelSim Cadence NC-Verilog VCS– Supports ModelSim, Cadence NC-Verilog, VCS,
Speedwave, and Scirocco• If you download new or updated cores, additional
simulation models willbe automatically extracted during installation
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )74
HDL Design Flow: CoreHDL Design Flow: CoreGeneration and IntegrationGenerate or purchase a core– Netlist file (EDN)– Instantiation template files (VHO or VEO)p ( )– Behavioral simulation wrapper files (VHD or V)• Instantiate the core into your HDL source– Cut and paste from the templates provided in the VEO or VHO filep p p• Design is ready for synthesis and implementation• Use the wrapper files for behavioral simulation– ISE automatically uses wrapper files when cores are present in the designy pp p g– VHDL: Analyze the wrapper file for each core before analyzing the file thatinstantiates the core
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )75
DSP48 i Xili ISEDSP48 macro in Xilinx ISE
DSP48 macro provides an easy-to-use interface thatabstracts the XtremeDSP™ slicei lifi it d i ti b bli thsimplifies its dynamic operation by enabling the
specification of multiple operations via a set of user-defined arithmetic expressionspSupport for up to 64 instructionsConfigurable latencyChoose between XtremeDSP Slice or fabricImplementationSupport of signed two’s complement input data
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
Support of signed, two s complement input data
76
DSP48 macro in XilinxDSP48 macro in Xilinx ISE(Cont’d)
The user specifies 1 to 64 instructions in the core GUI that are translated into the various control signals for the XtremeDSPslice of the target devicegThe instructions are stored in a ROM from which the user selects the appropriatewhich the user selects the appropriate instruction using the SEL port
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )77
B i C I/OBasic Core I/OsName Direction Optional DescriptionCLK Input No Clock – active rising edge
SCLR Input Yes Synchronous Clear – synchronous reset (activeHigh). Asserting SCLR synchronously with CLKresets all registersresets all registers
A Input Yes A Port – input of operand to Xtreme DSPACIN Input Yes Cascaded A port . Driven by ACOUTB Input Yes B Port – input of operand to Xtreme DSPCONCAT Input Yes Concatenation of A and B portsC Input Yes C port – input to XtremeDSP slice add/sub.CARRYIN Input Yes Carry in value from fabricSEL Input Yes SEL port – Selects the instruction width as
per no. of instructions
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
pP Output No P port – output from XtremeDSP slice
add/sub, provides the selected instructions result. Max : 48 bits 78
B i C I/OBasic Core I/OsName Direction Optional DescriptionP Output No P port – output from XtremeDSP slice
add/sub, provides the selected instructions result. Max : 48 bits
CARRYO O t N CARRYOUT f b/ dd tiCARRYOUT
Ouput No CARRYOUT of sub/add operation
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )79
C S h ti S b lCore Schematic Symbol
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )80
C fi ti f CConfiguration of Core
A Graphical user interface appears when DSP48 macro is selected to be generated gvia CoreGenFirst Component name is provided by userFirst Component name is provided by userA number of instructions copied from available instructions can be pasted on toavailable instructions can be pasted on to user-defined instructionsTh 64 i t ti
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
There are 64 instructions81
Pi li O tiPipeline Options
There are 3 options ,Automatic : Fully automated (as per ISE)Automatic : Fully automated (as per ISE)Tier1 : Configurable upto one tier ( one axis Expert : Fully configurable
Checkboxes appear as to select whetherCheckboxes appear as to select whether pipeline is to be inferred or not at a certain point of hardware
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
point of hardware
82
Implementation
DSP 48 th h C GDSP 48 through CoreGen
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )84
DSP48 C tiDSP48 Consumption
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )85
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )86
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )87
I t ti ti T l tInstantiation Template
dsp481 YourInstanceName (.clk(clk),( ).sel(sel), // Bus [2 : 0] .carryin(carryin),y ( y ),.a(a), // Bus [17 : 0] b(b) // Bus [17 : 0].b(b), // Bus [17 : 0]
.c(c), // Bus [47 : 0] p(p)); // Bus [47 : 0]
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )
.p(p)); // Bus [47 : 0]
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Hi h f th iHigh frequency synthesis
Timing Summary:---------------Speed Grade: -12
Mi i i d 1 244 (M i FMinimum period: 1.244ns (Maximum Frequency: 804.001MHz)
Minimum input arrival time before clock: 2.514nspMaximum output required time after clock: 4.152ns
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )89
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )90
Device Utilization Summary ofDevice Utilization Summary of the design with 3 instructions
Device utilization summary:---------------------------
Selected Device : 4vfx12ff668-12
Number of Slices: 61 out of 5472 1% Number of Slice Flip Flops: 112 out of 10944 1%Number of Slice Flip Flops: 112 out of 10944 1% Number of 4 input LUTs: 53 out of 10944 0% Number of IOs: 54Number of bonded IOBs: 53 out of 320 16% Number of GCLKs: 1 out of 32 3% Number of DSP48s: 1 out of 32 3%
FPGA based Digital Design using Verilog HDL( f p g a c o u r s e @ y a h o o . c o m )91
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