DSP_2_Lowpassfilter

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For Academic Use Only

Step by step tutorial on DSP using Xilinx SystemGenerator (NOT HOMEWOR !

DSP design using System Generator 1


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DSP using Xilinx System Generator

Introduction

This Tutorial will introduce the design of DSP systems using Simulink, Matlab,and Xilinx System Generator tool Xilinx offers a !ariety of high "uality state ofthe art #roducts for DSP design $e will work with field%#rogrammable gatearrays &'PG(s) *n order to do so, we need Simulink for de!elo#ment and!erification of the design+ and once we are ha##y with the results, SystemGenerator will translate faithfully our design into 'PG(s SysGen will create the

#ro ect files &-D.) that we can then synthesi/e, simulate, im#lement anddownload to the 'PG( with Xilinx *S0 Pro ect a!igator$e will become familiar with the Xilinx tools using an exam#le based a##roach'or this #ur#ose, we will im#lement a digital filter using The Multi#lier(ccumulator &M(2) unit which is the basic element to im#lement a Digital filteron a 'PG(

Objectives

(fter com#leting this tutorial, you will be able to $ork with Xilinx3s tools for DSP 4nderstand the basics of DSP design using System Generator Generate -D. code for a design through System Generator *m#ort System Generator design to *S0 Pro ect a!igator Generate a bit stream file to download to a 'PG( using *S0

Design Description

4se System Generator under Simulink en!ironment in Matlab to im#lement a '*5 Digital 'ilter

Ty#e%* '*5 .ow #ass filter 'ilter of 6 th order 4se of multi#le M(2s to im#lement design



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Procedure

This tutorial will guide you through 6 ste#s8 the first ste# will co!er the basics ofSimulink and System Generator and the remaining 9 will co!er how to createyour design using System Generator and im#lement it with Xilinx *S0 Pro ect

a!egator Ste# one is about Simulink, and ste# two goes o!er the Xilinx blockset es#ecially the Xilinx Gateways *n ste# :, you will learn the different ty#es of"uanti/ation and the effects of the sam#ling #eriod Se#t ; is about designing aDigital 'ilter using multi#le M(2s *n ste# 9, you will simulate the design whileon ste# will teach you how to create


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*# 2hange the work directory to the folder 28?DSP?Tutorial by cd c+,DSP,&utorialty#ing in the command window

-# .aunch Simulin + Ty#e simulin at the M(T.(= command #rom#t or click onthe simulink button on the M(T.(= tool bar to o#en the Simulin librarybro.ser#

Figure *

/# .ook at the blocks a!ailable in the Simulink .ibrary =rowser The followingelements, among others, should a##ear8

Simulin &sources and sinks) Signal Processing (loc set Xilinx (loc set Xilinx 0e1erence (loc set

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Figure -2# 5ight%click any block in the library browser, and choose -el# from the M(T.(=

menu



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Figure /

ote8 This #ro!ides details about the block @ou can also use -el# with theXilinx blockset elements

3# 2reate a Anew modelB blank sheet by clicking the 4reate a ne. model button ofthe Simulin 'ibrary (ro.ser

Figure 2

)# *n the library bro.ser window, ex#and the Simulin 'ibrary , and clickSources

5# (dd the Sine !ave source on the worksheet8 Scroll through the library to findthe Sine !ave , left click Sine !ave , and drag it onto the worksheet

6# (dd the Scope sink element and write it to the Sine !ave source on theworksheet8 'rom Simulink Simulin % Sin s , add the Scope block, and draw awire from the Sine !ave to the Sco#e block



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Figure 3

ote8 To draw a wire, left%click source and drag mouse to destination

(ssign a fre"uency of 7C#iC&1 19E) to the Sine $a!e element, show #ort dataty#es, and change simulation #arameter3s stop time to in1 &infinity)

"# Double%click the Sine !ave block

The (loc Parameters dialog box o#ens

*# 2hange the fre"uency to *7pi78"9"2:; and click >F to close the dialog box

Figure )

-# >n the worksheet, go to Format % Port9Signal Displays and click Port Data&ypes#

The signal width is dis#layed on the wire as shown in the following #icture

DSP design using System Generator


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Figure 5

/# 'rom your #ro ect sheet, #ull down the Simulation menu and select

4on1iguration Parameters

2# 'rom the Simulation Parameters dialog box, select Solver in the left handwindow and change the sto# time to in1 , and click >F

This allows your simulation to run to infinity &until you manually sto# thesimulation)

Figure 6

Parameteri/e the Scope block, and run the simulation

"# Double%click the Scope block

*# 2lick the Scope Parameters button

Figure ":

-# *n the Sco#e Parameters box, set the time range to 9EE, and click >F

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/# 5un the simulation8 'rom your Simulin #ro ect worksheet, click StartSimulation button, or use Simulation % Start

Figure ""

2# >n the Sco#e dis#lay, click Autoscale button so the out#ut will fit into theScope

Figure "*

3# ut, System Generator, and M4X blocks, asshown below, which #ro!ide interface to Xilinx =locksets in Simulink

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1 4sing Simulation % 4on1iguration Parameters dialog box, set the sto# time to2:: , and click >F

7 'rom the Xilinx (loc set &in the Simulin 'ibrary (ro.ser ), o#en (asicut blocks are re"uired to con!ert double%#recisionfloating #oint numbers used by Simulink in a simulation to bit fix #oint numbersused by Xilinx blocks Thus, a con!ersion is re"uired when communicating withXilinx blocks and Simulink blocks

: Double%click Gate.ay In to o#en the (loc Parameters

; Set the =umber o1 bits to 5 and (inary Point to *

9 Similarly, drag a Gate.ay Out block onto the sheet, and dro# it between theGate.ay In block and the out#ut Scope block

Figure "-

6 (dd and connect a Simulink $UX between the Gate.ay Out and the Scope byusing Simulin % Signal 0outing

(dd an additional net between t>e Sine !ave and the $UX

ote8 This will make the sco#e dis#lay both the double%#recision sine wa!e andthe user%defined #recision sine wa!e that has gone into and back out of the Xilinxgateways

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H (dd a system generator token from t>e Xilinx (loc set % (asice Format % Port9SignalDisplays menu

Figure "/

1E 4#date the diagram8 select


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Analy?e Precision@ uanti?ation and Sample 0ate Ste# :

5un the simulation with default settings and understand and understand theout#ut 2hange the data ty#e and simulate, and analy/e the simulation out#ut2hange the sam#ling #eriod from one to fi!e and see effect on the "uanti/ation

Implement a &ypeBI FI0 Filter Ste# ;

*m#lement a Ty#e%* '*5 'ilter using Xilinx =lockset in Simulink The designcharacteristics are the following8

Se#arate multi#lier and accumulator #er filter coefficient .ow Pass 'ilter of order 6 2oefficients generated using the 'D( Xilinx Tool Sam#ling fre"uency of 1k-/

"# *n the #ro ect sheet, select File % =e. % $odel

( new Simulink #ro ect o#ens

*# (dd two Sine in#uts to the worksheet

-# (dd the Sum block from the Simulink Math >#erations .ibrary and connect it tothe sine blocks



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Figure *-

/# (dd the Xilinx Gate.ay In block

2# (dd the Delay block from the =asic 0lements library of the Xilinx =lockset

3# (dd the Xilinx 4onstan t =lock from the =asic 0lements Xilinx =lockset

)# (dd the Xilinx $ultiplier =lock form the *ndex Xilinx =lockset

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Figure */

5# 5e#eat ste# 9, 6,

6# (dd the Xilinx Adder9Substractor from the *ndex Xilinx =lockset

Figure *2

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":# 5e#eat ste#s 9, 6, , H until the design looks like figure

Figure *3

""# (dd the Xilinx Gate.ay Out block

"*# (dd two Scope blocks and connect one to the sine in#uts and the other to theout#ut of the Gateway out and the out#ut of the Sum block

To increase the number of in#uts to the sco#e, double%click on it, on the menuclick on Parameters and change the number of axis

Figure *)

"-# $ire all the blocks and add the System Generator token from the Xilinx =asic0lements .ibrary as well as the 'D( Tool from the Xinlinx DSP .ibrary



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The final diagram should look like figure 76

Simulate t>e &ypeBI FI0 Filter Using Simulin Ste# 9

2onfigure the in#uts and simulation #arameters as s#ecified below ext, simulate the'ilter in Simulink and !erify the design functionality

Two Sine in#uts8 low and high fre"uencies 16 bit in#ut8 signed data &73s com#lement) binary #oint 1:, and sam#ling #eriod

of E EE1 seconds Multi#lier =lock latency of 1 and 'ull #recision .ow#ass Ty#e%* '*5 filter of order 6 Simulation #arameters8 Sto# time E 9 seconds

1 Set the fre"uencies of the sine in#uts >ne to 9-/ and the other to :EE -/

7 2onfigure the in#uts by double%clicking the Gate.ay In blocks to o#en theirParameters dialog box

: Set t>e =umber o1 bits to 16 and the (inary Point to 1;

; Set the Over1lo. to Saturate and Sample period to E EE1 seconds

9 Design the six order low #ass filter by double%clicking on the FDA &ool block

6 >n 0esponse &ype choose .ow#ass

Set the Desing $et>od to '*5 and from the bottom down menu select 'eastBsCuares#

H Set theFilter Order to 6

I >n FreCuency Speci1ications select ormali/ed for the units and set the w#assto E 1 and the wsto# to E 79



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Figure *5

1E 2lick on the Design 'ilter button

11 2lick on the File menu % n the same block, edit the 4onstant value to the !alues of the 1ilterEcoe11 !ariable accordingly to their #osition in the array

ote8 Do this for the se!en coefficients Do not change the order of thecoefficients since each one of them is associated to a s#ecific delay !alue andkee# in mind that Matlab index start at 1 that corres#onds to the first coefficient!alue which has no delay



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Figure *6

1 Double click on the System Generator block and se the Simulink System Periodto 1 1EEE

1H Sa!e the design on your work directory as .ow#ass mdl and run the simulation by clicking on the Start Simulation button

1I The gra#hs of the in#ut and out#ut should look like figure :E

DSP design using System Generator 1H


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DSP design using System Generator 1I


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Figure -:

DSP design using System Generator 7E

DSP_2_Lowpassfilter

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