SUBMITTED BY

Avinash SrivastavaMTech 2nd SEM (CAID)

DSP IntroductionDSP TasksDSP ApplicationsDSP vs. General Purpose MPUTMS DSP ICTMS DSP TypesTMS GenerationsMOTOR control applicationConclusion

Digital Signal Processing: application of mathematical operations to digitally represented signalsSignals represented digitally as sequences of samples.Digital Signal Processor (DSP): electronic system that processes digital signals

Most DSP tasks require: Repetitive numeric computations Real-time processing High memorySystem Flexibility DSPs must perform these tasks efficiently while minimizing: Cost Power Memory use Development time

Digital cellular phonesDigital camerasSatellite communicationVoice mailMusic synthesisModemsRADARMotor Control

DSPs tend to be written for 1 program, not many programs. Hence OSes are much simpler, there is no virtual memoryDSPs run real-time appsYou must account for anything that could happen in a time slot All possible interrupts or exceptions must be noticed.DSPs have an infinite continuous data stream

TMS 320 C5X TMX : Experimental deviceTMP : PrototypeTMS : Qualified deviceC: CMOS Tech with on chip non- volatile memory as ROME: CMOS tech with on-chip non volatile memory as EPROMnothing : NMOS tech with on-chip non volatile mem as ROM 5 : Generation X : Version number- 0,1,2,3,4x,5,6,7

Fixed Point DSPsTMS320C5x & 54x16-bit DSPs Floating Point DSPs TMS320C3x, 4x & 6x16 & 32-bit DSPsMultiprocessor DSPsTMS320C8x

A DSP has to perform fast arithmetic operations and should handle mathematical intensive algorithms in real time. This was achieved by these basic concepts-Harvard architecture ( increased memory access/cycle)extensive pipelining,dedicated hardware multiplier,special DSP instructions( DMOV delay)fast instruction cycle

Instruction cycle timing: -160 ns -200 ns -280 ns.5 MIPS20 MHzOn chip data RAM: -144 words -256 words (TMS320C17).On chip program ROM: -1.5K words 4 K words (TMS320C17).4K words of on chip program EPROM( TMS320E17).16 x I6 bit multiplier with 32-bit result.16-bit barrel shifter for shifting data memory words into the ALU.4 x 12-bit stack.Two auxiliary registers for indirect addressing.Eight 16 bit I/O portOperating Temperature . . . 0C to 70C

Reduced Instruction cycle timing: -100 ns (TMS320C25) 10 MIPS, 40 MHz4K words of onchip masked ROM (TMS320C25).544 words of onchip data RAM.128K words of total program data memory space. Eight auxiliary registers with a dedicated arithmetic unit.Serial port for multiprocessing or interfacing to codecs.Bit-reversed addressing modes for fast Fourier trans-forms (TMS320C25).Extended-precision arithmetic and adaptive filtering support (TMS320C25).

60-ns single cycle execution time20 -30 MIPSTwo 1K x 32-bit single cycle dual-access RAM blocks.One 4K x 32-bit single cycle dual-access ROM block.64 X 32-bit instruction cache.32-bit instruction and data words, 24-bit addresses.32*32 bit floating-point and integer multiplier ( 40 bit product ).32-bit floating-point, integer, and logical ALU.32-bit barrel shifter.Eight extended-precision registers.Two address-generators with eight auxiliary registers.On chip Direct Memory Access (DMA) controller. High-level language support.

The TMS320C4x devices are 32-bit floating-point digital signal processors optimized for parallel processing.33-/40-ns instruction cycle times40 MIPSANSI C compilerThe C4x family accepts source code from the TMS320C3x family of floating-point DSPs. Key applications of the C4x family include 3-dimensional graphics, image processing, networking, and telecommunications base stations.

Fixed Point DSPPower Efficient (1.15mA/MIPS)20-50 MIPS20-35ns single cycle execution timeBit reversed /index addressing mode for FFTPower Down modes8 Auxiliary registersSingle Cycle 16*16 bit parallel multiplier (32 bit product)32 bit accumulator ,32 bit ALU

16-bit fixed pointPower < 40 mW300 to 532 MIPS3 Power down modesRAM 16 Kb to 1280Kb(TMS320C5441-175)ROM max 256KBApplications Digital Cellular Base stationsPDAsDigital Cordless PhonesModems

16 & 32 bit fixed pointMost power efficient in the industry with 0.12mW (stand by)600 MIPSDual ProcessorRAM 320KbROM 32 to 64KbNewest in series TMSC5506-108Applications 2G,2.5G,3G cellular phones and base stationsDigital audio playersDigital still camerasGPS receiversWireless modems

First to feature VelociTI architecture.TMS320C62Xmulti-channel, multi-function applications Advanced VLIW architecture Medical, industrial applications, digital imaging, 3D graphics, speech recognition and voice-over packet.Frequency 150 to 300 MHzRAM up to 1 MB (min 128Kb)Greater than 1600 MIPS

TMS320C64x (highest level of performance )Speeds up to 1GHzUp to 8000 MIPS digital communications infrastructure video and image processing TMS320C67x (high-precision applications )First floating point processor in 6x series6 ns cycle timing1billion floating point operations per second (Flops)audio, medical imaging, instrumentation and automotive.

A DSP motor drive system consists of Input power supply stagePower inverterGate driversDSP controllerMotor

DSP performance has increased according to the applications involved.DSP friendly ness is an important factor because the applications complexity is increasing.With the DSP-Controller an intelligent control approach is possible to reduce the overall system costs and to improve the reliability of the drive system.

S. Bejerke, Digital Signal Processing Solutions for Motor Control Using the TMS320F240 DSP-Controller, ESIEE, Texas Instrument, Paris September 1996 SPRA345 Edwin J. Tan, Wendi B. Heinzelman, DSP Architectures: Past, Present and Future, Department of Electrical and Computer Engineering University of Rochester, Rochester, NY 14627Zhenyu Yu, 3.3V DSP for Digital Motor Control, Application Report SPRA550 Digital Signal Processing Solutions Texas Instrument, June 1999

*