DSP Project Purchases - saaubi.people.wm.edu
Transcript of DSP Project Purchases - saaubi.people.wm.edu
![Page 1: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/1.jpg)
DSP Project PurchasesDSP Project PurchasesBudget = $200.00 USD per team.
All purchases will go through the instructor to Sylvia Stout.
You must provide an internet shopping cart printout with all the part numbers. An electronic version is useful and will help speed up the purchase.
If you buy a part at a local store, then you must keep the receipt and submit it to the instructor at the end of the course.
You are encouraged to use the parts in the lab to perfect your design, however your final device should include only new non-lab parts (except wire).
![Page 2: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/2.jpg)
State MachineState Machine
RegisterD-type
flip-flopsQ0Q1
Qn
D0D1
Dn
Logic Gates
+
addressable
memory
INPUTS OUTPUTS
system clock
RegisterD-type
flip-flopsQ0Q1
Qn
D0D1
Dn
RegisterD-type
flip-flopsQ0Q1
Qn
D0D1
Dn
Logic Gates
+
addressable
memory
INPUTS OUTPUTS
system clock
Definition:Definition: A machine that makes predictable transitions through a sequence ofstates, based on external inputs and the current state of the machine.
![Page 3: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/3.jpg)
State Machines in State Machines in VerilogVerilog
![Page 4: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/4.jpg)
State Machines in State Machines in QuartusQuartus IIIITools > Netlist Viewers > State Machine Viewer
Note: The Note: The QuartusQuartus II compiler will only find the State Machine if you follow the II compiler will only find the State Machine if you follow the VerilogVerilog example code fairly closely.example code fairly closely.
![Page 5: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/5.jpg)
Shift Register CircuitShift Register Circuit
D QC
D QC
D QC
bit-0 OUT bit-1 OUT bit-2 OUT
Clock trigger
serial input serial outputD QC
D QC
D QC
bit-0 OUT bit-1 OUT bit-2 OUT
Clock trigger
serial input serial output
![Page 6: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/6.jpg)
Shift Register in Shift Register in VerilogVerilog
![Page 7: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/7.jpg)
Shift Register in Shift Register in VerilogVerilog
use the left bit shift operator <<
![Page 8: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/8.jpg)
MicroprocessorsMicroprocessors
Microprocessors are a generalization of a state machines which fit on a single IC. They have the following components:
Instruction set: These are the basic instructions that the CPU can perform (add, multiply, store memory, retrieve memory, etc …)
Memory: this is generally a 2-d array of shift registers (FIFO) where a program (i.e. a series of instructions) and the bits that it manipulates are stored. Exact memory architecture varies.
Memory for program
Memory for bits
Attached peripherals (input/output) are treated as memory locations.
Microprocessors perform 1 instruction at a time. A single instruction can take mutiple clock cycles. All operations are performed in a sequential manner.
[image from jkslade.net]
![Page 9: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/9.jpg)
Microprocessor (vs. Microprocessor (vs. FPGAsFPGAs))
Advantages: - Conceptually simple sequential operation.
- Easy to program (i.e. C, Basic, Java, Fortran …).
- Enormous number of function libraries to use.
- It’s a computer minus screen, keyboard, and mouse.
Disadvantages: - Slow (multiple clock cycles per instruction).
- Non-parallel … only sequential.
- Operating systems can be unreliable.
- Non-deterministic timing operation (interrupts …).
[image from jkslade.net]
![Page 10: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/10.jpg)
NiosNios II microprocessorII microprocessor
You can program a microprocessor(s) onto an FPGA.
The Altera soft-processor is called Nios II and is programmed onto the FPGA using the SOPC builder (SOPC = System On a Programmable Chip).
I found that Nios II was not well supported by the Quartus II Web Edition (v7.1)
Use the Quartus II full subscription version
(Electronics lab, Morton 240, Swem 134)
The SOPC builder can be found in Quartus II at
Tools > SOPC Builder …
![Page 11: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/11.jpg)
![Page 12: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/12.jpg)
![Page 13: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/13.jpg)
![Page 14: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/14.jpg)
![Page 15: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/15.jpg)
![Page 16: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/16.jpg)
![Page 17: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/17.jpg)
![Page 18: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/18.jpg)
![Page 19: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/19.jpg)
![Page 20: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/20.jpg)
![Page 21: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/21.jpg)
![Page 22: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/22.jpg)
![Page 23: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/23.jpg)
![Page 24: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/24.jpg)
![Page 25: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/25.jpg)
![Page 26: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/26.jpg)
![Page 27: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/27.jpg)
![Page 28: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/28.jpg)
![Page 29: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/29.jpg)
Main Nios II module is called
nios_system
The code for nios_system is in
nios_system.v
![Page 30: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/30.jpg)
![Page 31: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/31.jpg)
![Page 32: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/32.jpg)
![Page 33: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/33.jpg)
Compile project (1st compilation)
![Page 34: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/34.jpg)
![Page 35: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/35.jpg)
![Page 36: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/36.jpg)
![Page 37: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/37.jpg)
We will use the Altera Monitor Program is used to download a program into the Nios II microprocessor embedded in the FPGA. It uses the JTAG protocol.
We will program with C (the post popular programming language).
Nios II IDE program is used by professional circuit designer to test program on the Nios II processor.
Programming Programming NiosNios IIII
![Page 38: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/38.jpg)
![Page 39: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/39.jpg)
![Page 40: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/40.jpg)
![Page 41: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/41.jpg)
![Page 42: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/42.jpg)
![Page 43: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/43.jpg)
![Page 44: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/44.jpg)
![Page 45: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/45.jpg)
Remember to keep reset line HIGH
![Page 46: DSP Project Purchases - saaubi.people.wm.edu](https://reader033.fdocuments.in/reader033/viewer/2022042417/625f5727e6b84432850bdba9/html5/thumbnails/46.jpg)