Dsp Manual Final

RAMAPPA ENGINEERING COLLEGE DSP Lab

CODE OF CONDUCT FOR THE LABORATORIES

All students must observe the Dress Code while in the laboratory. Sandals or open-toed shoes are NOT allowed. Foods, drinks and smoking are NOT allowed. All bags must be left at the indicated place. The lab timetable must be strictly followed. Be PUNCTUAL for your laboratory session. Program must be executed within the given time. Noise must be kept to a minimum. Workspace must be kept clean and tidy at all time. Handle the systems and interfacing kits with care. All students are liable for any damage to the accessories due to their own negligence. All interfacing kits connecting cables must be RETURNED if you taken from the lab

supervisor. Students are strictly PROHIBITED from taking out any items from the laboratory. Students are NOT allowed to work alone in the laboratory without the Lab Supervisor USB Ports have been disabled if you want to use USB drive consult lab supervisor. Report immediately to the Lab Supervisor if any malfunction of the accessories, is

there.

Before leaving the lab

Place the chairs properly. Turn off the system properly Turn off the monitor. Please check the laboratory notice board regularly for updates.

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GENERAL LABORATORY INSTRUCTIONS

You should be punctual for your laboratory session and should not leave the lab without the permission of the teacher.Each student is expected to have his/her own lab book where they will take notes on the experiments as they are completed. The lab books will be checked at the end of each lab session. Lab notes are a primary source from which you will write your lab reports.

Organization of the LaboratoryIt is important that the programs are done according to the timetable and completed within the scheduled time.You should complete the pre lab work in advance and utilize the laboratory time for verification only.The aim of these exercises is to develop your ability to understand, analyze and test them in the laboratory. A member of staff and a Lab assistant will be available during scheduled laboratory sessions to provide assistance.Always attempt program first without seeking help. When you get into difficulty; ask for assistance.

Assessment

The laboratory work of a student will be evaluated continuously during the semester for 25 marks. Of the 25 marks, 15 marks will be awarded for day-to-day work. For each program marks are awarded under three heads:

Pre lab preparation – 5 marks Practical work – 5marks, and Record of the Experiment – 5marks

Internal lab test(s) conducted during the semester carries 10 marks.End semester lab examination, conducted as per the JNTU regulations, carries 50 marks.At the end of each laboratory session you must obtain the signature of the teacher along with the marks for the session out of 10 on the lab notebook.

Lab ReportsNote that, although students are encouraged to collaborate during lab, each must individually prepare a report and submit. They must be organized, neat and legible. Your report should be complete, thorough, understandable and literate. You should include a well-drawn and labeled engineering schematic for each circuit investigatedYour reports should follow the prescribed format, to give your report structure and to make sure that you address all of the important points. Graphics requiring- drawn straight lines should be done with a straight edge. Well drawn free-hand sketches are permissible for schematics. Space must be provided in the flow of your discussion for any tables or figures. Do not collect figures and drawings in a single appendix at the end of the report.Reports should be submitted within one week after completing a scheduled lab session.

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http://www.soe.ucsc.edu/classes/ee171/Spring05/Lab_reportFormat.html


PresentationExperimental facts should always be given in the past tense. Discussions or remarks about the presentation of data should mainly be in the present tense. Discussion of results can be in both the present and past tenses, shifting back and forth from experimental facts to the presentation. Any specific conclusions or deductions should be expressed in the past tense.

Report Format: Lab write ups should consist of the following sections:

Aim: Here you need to write in brief what you are doing in the laboratory in a line or two.

Software used: Here we want you to specify the version of the software used.

Program(s): Programs have to be written without errors and with comments.

Error encountered :You are expected to note down the errors got in the lab so that you will have an idea of common mistakes you make in the lab.(It would be even better to copy the errors and reproduce as it is.)

Simulated Waveforms: A printout of the programs has to be attested.

Conclusion: Your observations have to be given.

NOTE: Diagrams if any must be drawn neatly on left hand side.

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LIST OF EXPERIMENTS

Introduction

i. To study the architecture of DSP chips – TMS 320C 5X/6X Instructions

ii. Code Composer Studio.

iii. Generation of various signals and sequences.

1. To find DFT/IDFT of a given DT signal

2. To find the frequency response of a given system.

3. i. To verify Linear convolution

ii. To verify circular convolution

4. Implementation of FFT of a given sequence.

5. Determination of power spectrum of a given signal.

6. Implementation of LP FIR filters.

7. Implementation of HP FIR filter

8. Implementation of LP IIR filter

9. Implementation of HP IIR filter

10. Implementation of Decimation process.

11. Implementation of interpolation process.

12. Impulse response of first order and second order systems.

13. Implementation of I/D sampling rate conversion

INTRODUCTION

I. TO STUDY THE ARCHITECTURE OF DSP CHIPS –TMS 320C 5X/6X

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The programmable digital signal processors are designed with features that are specially and specifically required for digital signal processing applications. The conventional microprocessors are meant for general purpose applications and hence they do not have these features. However, an advanced microprocessor or a RISC processor may use some of the techniques adopted in P-DSP’s or may even have instructions that are specifically required for performing digital signal processing operations efficiently, they are

a) Multiplier Accumulator :

One of the most common operations required in digital signal processing applications is array multiplication. E.g.:- convolution and correlation. One of requirements of array multipliers is that they have to process the signals in real time. Before the next sample of the input signal arrives at the input of the array, the array multiplication should be completed. This can be done in two ways; the first approach uses a dedicated MAC unit, implemented in hardware, which integrates multiplier and accumulator in a single hardware unit. This approach is adopted by Motorola DSP processor. The second approach is to have multiplier and accumulator separate. This is adopted in Texas instruments DSP processor, 320 c5x. In both approaches MAC operation can be completed in one clock cycle.

b) Bus Structure & Memory Access Schemes :

MAC operation with data move requires four memory access per instruction cycle. The four memory access/clock period required for the MACD instructions are

1) Fetch the MACD instruction from the program memory2) Fetch one of the operands from the program memory3) Fetch the second operand from the data memory4) Write the content of the data memory with address DMA into the location with the

address DMA+1There are two types of architectures for this purpose

1) Von Neumann Architecture2) Harvard Architecture.

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In von Neumann architecture there is a single address bus and a single data bus for accessing program as well as data memory where as in Harvard architecture we have two separate buses for program and data memories which reduce the number of clock cycles required for memory access. If the MACD instruction is to be executed in a machine with Von Neumann architecture, it requires four clock cycles. This is because in the Von Neumann architecture, it requires four clock cycles. This is because in the von Neumann architecture we have a single address bus and a single data bus for accessing the program as well as data memory area. One of the ways by which the number of clock cycles required for the memory access can be reduced is to use more than one bus for both address and data. In Harvard architecture we have two separate buses for the program and data memory. Hence the content of program memory and data memory can be accessed in parallel.

Since the cost of an IC increases with the number of pins in the IC, extending a number of buses outside the chip would unduly increase the price. Hence P-DSP’s use multiple buses only for connecting the on-chip memory to the control unit and data path. For accessing off-chip memory only a single bus is used for accessing both the program memory and data memory. Because of this, any operation that involves an off-chip memory is slow compared to that using on-chip memory.

C) Multiple Access Memory : The number of memory accesses/clock period can also be increased by using a high speed memory that permits more than memory access/clock period. For example, the DARAM, the dual access RAM, permits two memory access/clock period. Multiple access RAM may be connected to the processing unit of the P-DSP by using the Harvard architecture. For example DARAM connected a P-DSP with two independent data and address buses can be used to achieve four memory accesses/clock period.

D) Multiported Memory : The number of memory accesses/clock period can also be increased by using a high speed memory that permits more than one memory access/clock period. For example the dual port memory has two independent data and address buses and hence two memory accesses can be achieved in a clock period. Multiported memories dispense with the need for storing the program and data in two different memory chips in order to permit simultaneous access to both program and data memory. However, one of the major limitations of the dual ported memory is the increase in the cost compared to two single port memory of the same total capacity. This is because

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of the increased number of pins and larger chip area required for the dualported memory.

E) VLIW Architecture : VLIW architecture is nothing but very long instruction word architecture. These P-DSP’s have a number of processing units (data paths) i.e., they have a number of ALU’s, MAC units, shifter etc.The VLIW is accessed from memory and is used to specify the operand and operations to be performed by each of the data paths. Parallel random access by the functional units to the register file is facilitated by the read /write cross bar. The performance gains that can be achieved with VLIW architecture depends on the degree of parallelism in the algorithm selected for a DSP application and the number of functional units. The throughput will be higher only if the algorithm involves execution of independent operations. However, it may not always be possible to have independent stream of data for processing. Further the number of functional units is also limited by the hardware cost for the multiported register file and cross bar switch.

F) Pipelining : One of the approaches adopted for increasing the efficiency of the advanced microprocessors as well as P-DSP’s is instruction pipelining. An instruction cycle requiring four micro instructions can be said to be in four phases.

1) Fetch phase in which the instruction is fetched from the program memory.2) Decode phase in which the instruction is decoded.3) Memory read phase in which the operand required for the execution of the

instruction may be read from the data memory.

4) Execution phase in which execution as well as the storage of the results in either of the registers or memory is carried out.

value of T Fetch Decode Read Execute1 I12 I2 I13 I3 I2 I14 I4 I3 I2 I15 I5 I4 I3 I26 I6 I5 I4 I37 I7 I6 I5 I48 I8 I7 I6 I59 I9 I8 I7 I610 I8 I711 I9 I812 I9

Each of these instructions can be carried out separately by four functional units. The initial latency of a machine with four phases can be given as 4T.

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Hence for executing a program with N instructions, the time required for execution is (N+4) T. with a non-pipelined machine, the time required for executing N instructions is 4NT. In case of processors requiring a single clock cycle for execution for each of the instruction in the program, the throughout required could be achieved. This is normally achieved with restricted instruction set computers (RISC). However, in complex instruction set computers(CISC), there are also instructions with multiple word requiring multiple clock cycles for execution. The throughput efficiency of the pipeline may also be reduced because of conflicts between the instructions in the instruction pipeline in different phases. This happens if the same memory is used to store the data and program and there is only a single address bus for addressing both the program and data memory. This is true in case of the off-chip memory. The number of instructions that are processed simultaneously in the CPU, also referred to as depth of the instruction pipeline, differs in different families of P-DSP’s.

G) Special Addressing Modes In P-DSP’s : In addition to the addressing modes such as direct, indirect and immediate supported by the conventional microprocessors, P-DSP’s have special addressing modes that permit single word/instruction format and thereby speed up the execution by making effective use of the instructions pipelining. These instructions are as follows:

SHORT IMMEDIATE ADDRESSING: This permits the operand to be specified using a short constant that forms part of a single word instruction. The length of the short constant depends on the instruction type and the P-DSP. The 8-bit constant in the TMS320C5X can be specified as one of the operands in the single word instructions for addition, subtraction, AND, OR, XOR, etc.

SHORT DIRECT ADDRESSING: This permits the lower order address of the operand of an instruction to be specified in the single word instruction. In the TI TMS320 DSPs, the higher order 9 bits of the memory are stored in the data page pointer and only the lower 7 bits are specified as a part of the instruction. Each contiguous block of 128 words is referred to as one page in the TI DSPs.

MEMORY-MAPPED ADDRESSING: The CPU registers and the I/O registers of the P-DSPs are also accessible as memory location. This is achieved by storing them in either the starting page or the final page of the memory space. For example, in TMS320C5X, page 0 corresponds to the CPU registers and I/O registers. When these registers are accessed using memory mapped addressing modes, the higher address bits are not taken from the data page pointer and instead made to be 0 in the care of TI DSPs and made top be 1 in Motorola DSPs.

INDIRECT ADDRESSING: It permits an array of data to be processed in P-DSP to be efficiently fetched and stored. The address of the operands can be stored in one of the registers called indirect address registers. In case of the T1 processors, the indirect address registers are called auxiliary registers ARS. Any of these registers can be updated when the operand fetched using these registers are being executed. This is made possible by having an additional ALU in the CPU core specifically for the indirect address registers of ARs. In case of TI processors, the offset register is called

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an INDX register. The indirect addressing mode in TI 5X P-DSPs is called indirect addressing mode with post increment/decrement.

BIT REVERSED ADDRESSING MODE: The binary pattern corresponding to a particular decimal number is obtained by writing the natural binary equivalent of the number in the reverse order so that the most significant bit of the natural binary number becomes the least significant bit of the bit reversed no and vice versa. For the computation of the FFT, the data is to arranged in the bit reversed order and 2-point DFT of the resulting sequence is to be computed first. In the bit reversed addressing mode the address is incremented/decremented by the number represented in the bit reversed form.

CIRCULAR ADDRESSING: in real time processing of signals, the input signal is continuously stored in the memory. The processed data is stored in another memory space continuously and may be written onto the output device. In this case input as well as output program will be simple. However, since the input as well as output memory space will be finite in size, the entire memory space would be exhausted after processing the input signal for some time, if the data is written into the memory by using linear addressing mode. One way to overcome this problem is to keep checking whether the range of either the input or the output memory space is exceeded. In this mode, the memory can be organized as a circular buffer with the beginning memory address and the ending memory address corresponding to this buffer defined by the programmer. In this circular addressing mode, when the address pointer is incremented, the address will be checked with the ending memory address of the circular buffer.

H) On-Chip Peripherals : The P-DSPs have a number of on-chip peripherals that relieve the CPU from routing functions. Further they also help to reduce the chip count on the DSP system around P-DSP. Some of the on-chip peripherals in the P-DSPs can be given as follows,

(i) On-chip timer(ii) Serial port(iii) TDM serial port(iv) Parallel port (v) Bit I/O ports(vi) Host port(vii) Communication ports(viii) On-chip A/D and D/A converters(ix) P-DSPs with RISC and CISC

I) RISC Advantages :

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The chip area dedicated to the realization of the control unit is considerably reduced because of the reduced number of instructions. About 20% of the chip area may be used for the control unit in RISC. In CISC processors about 30-40% of the chip area is used up for the control unit. Therefore in a RISC there is more area available for incorporating other features. In a RISC, all the instructions are of uniform length and take the same time for execution. Hence dummy periods or hold periods in the instruction pipeline are reduced to the minimum. This increases the computational speed. A simpler and smaller control unit in RISC has fewer gates. This reduces the propagation delay and increases the speed. Reduced number of instructions, formats and addressing modes result in simpler and smaller decoder, which, in turn, increases the speed. In RISC processors, the delayed branch and call instructions can be effectively used and they improve the speed.

J) CISC Advantages :

The CISC processors have a very rich instruction set that even support high level language constructs similar to “if condition true then do” , “for” and “while”. The P-DSPs with CISC also have instructions specifically required for DSP applications such as MACD, FIRS, etc. this makes the application program written in the assembly language to be shorter and easy to follow. Since RISC has a smaller number of instructions, implementation of a single CISC instruction might requires a number of instructions in RISC. This increases the memory required for storing the program and the traffic between CPU and memory is increased. This is on the one hand increases the computation time and on the other hand makes the program difficult to debug.

TMS320 C5X DSP

INTRODUCTION : The TMS320 DSP family consists of two types of single chip DSPs, 16-bit fixed point and 32 bit floating point. These DSPs possess the operational flexibility of high speed controllers and the numerical capability of array processors. Combining these two qualities, the TMS320 processors are inexpensive alternatives to custom fabricated VLSI and multichip bit slice processors. TMS320 C5X belongs to the fifth generation of the TI’s TMS320 family of DSPs. The first five generations of TMS320 family are C1X, C2X, C3X, C4X and C5X. The C1X, C2X, C2XX, C5X are 16-bit fixed point processors. The typical applications of TMS320C5X processors are in toys, hard disk drives, modems, cellular phones and active car suspensions. C5X has three processors `C50, `C51 and `C5X that have identical instruction set but have differences in the capacity of on-chip ROM and RAM. The TI DSP chips have IC numbers with the prefix TMS320. if the next letter is c it indicates the CMOS technology is used for the IC and the on-chip non-volatile memory is a ROM. If it is E, it indicates that the technology used is CMOS and the on-chip non-volatile memory is an EPROM. If it is neither, it indicates that NMOS technology is used for the IC and the on-chip non-volatile memory is a ROM. The instruction set of TMS320C5X and other DSP chips is superior to the

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instruction set of conventional microprocessors such as 8085, Z80 etc., as most of the instructions require only a single cycle for execution.

ARCHITECTURE OF TMS320C5X DSPs:

The block diagram of the internal architecture of C5X is as shown. The TMS320C5X DSPs are said to have advanced architecture because they have separate memory bus structures for program and data and have instructions that enable data transfer between the program and data memory area.

A) Bus Structure : Separate program and data buses allow simultaneous access to program instructions and data, providing a high degree of parallelism. For example, while data is multiplied, a previous product can be loaded into, added to or subtracted from the accumulator and, at the same time, a new address can be generated. Such parallelism supports a powerful set of arithmetic, logic and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the `C5X includes the control mechanisms to manage interrupts, repeated operations and function calling. The `C5X architecture has four buses and their functions are as follows:

a. PROGRAM BUS: it carries the instruction code and immediate operands from program memory space to the CPU.

b. PROGRAM ADDRESS BUS: It provides addresses to program memory space for both reads and writes.

c. DATA READ BUS: It interconnects various elements of the CPU to data memory space.

d. DATAREAD ADDRESS BUS: It provides the address to access the data memory space. The program and data buses can work together to transfer data from on-chip data memory and internal or external program memory to the multiplier for single-cycle multiply/accumulate operations.

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B) Central Arithmetic Logic Unit : It consists of 16x16 bit parallel multiplier, arithmetic logic unit, accumulator, accumulator buffer, product register each with 32 bits and 0-16 bit left barrel shifter and right barrel shifter. One of the operands for the ALU operation comes from ACC. The result of operations performed in central ALU are stored in ACC. Either the higher order word or lower order word of ACC can be loaded from memory. The hardware multiplier unit in the C%X processors performs 16x16 multiplication of numbers represented in 2`s complement form. 0-16 bit left barrel shifter and right barrel shifter in CALU permit the contents of memory to be left shifted by 0 to 16 bits before they are either fed to ALU or stored from ALU to memory. The 32-bit PREG holds the result of multiplication. The 16-bit temporary register holds the multiplicand and the other operand for the multiplication can be specified using one of the addressing modes.

C) Auxiliary Register ALU : It consists of eight 16-bit auxiliary registers AR0-AR7, a 3-bit auxiliary register pointer and an unsigned 16-bit ALU. ARAU calculates indirect addresses by using inputs from ARs, 16-bit index register and auxiliary register compare register. The ARAU can auto index the current AR while the data memory location is being addresses and can index either by + or- 1 or by the contents of the INDX. Any of the auxiliary registers can be used as the address pointer and incremented by the above instruction. The register that will be used is specified by the content of the ARP. The auxiliary registers AR0-AR7 may also be used as the general purpose registers for holding the operands for arithmetic and logical operations in CALU. Some of the registers can be given as follows,

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INDEX REGISTER: the 16-bit INDX is used by the ARAU as a step value to modify the address in the ARs during indirect addressing. For example, when the ARAU steps across a row of a matrix, the indirect address is incremented by 1. However, when the ARAU steps down a column, the address is incremented by the dimension of the matrix. INDX can also map the dimension of the address block used for bit-reversal addressing.

AUXILIARY REGISTER COMPARE REGISTER: The 16-bit ARCR is used for address boundary comparison. The CMPR instruction compares the ARCR to the selected AR and places the result of the compare in TC bit of ST1.

BLOCK REPEAT REGISTERS: Block repeat registers contains RPTC, BRCR, PASR, and PAER. All these registers are 16-bit wide. Repeat counter register holds the repeat count in a repeat single instruction operation and is loaded by the RPT and RPTZ instructions. Block repeat counter register holds the count value for the block repeat future. This value is loaded before a block repeat operation is initiated. Block repeat program address start register indicates the 16-bit address where the repeated block of code starts. The block repeat program address end register indicates the 16-bit address where the repeated block of code ends.

BLOCK MOVE ADDRESS REGISTER: The 16-bit BMAR holds an address value to be used with block moves and multiply/ accumulate operations. This register provides the 16-bit address for an indirect addressed second operand.

PARALLE LOGIC UNIT: It performs boolean operations or the bit manipulations required of high speed controllers. The PLU can set, clear, test or toggle bits in a status registers control register, or any data memory location. The PLU allows logic operations to be performed on data memory values directly without affecting the contents of the ACC or PREG.

MEMORY MAPED REGISTERS: The `C5X has 96 registers mapped into page0 of the data memory space. All `C5X DSPs have 28 CPU registers and 16 input/output port registers but have different numbers of peripheral and reversed registers. Since the memory-mapped registers are a component of the data memory space, they can be written to and read from in the same way as any other data memory location.

D) Program Controller : the program controller contains logic circuitry that decodes the instructions, manages the CPU pipeline, stores the status of CPU operations and decodes the conditional operations. Parallelism of architecture lets the `C5X perform three concurrent memory operations in any given machine cycle: fetch an instruction, read an operand and write an operand.The program controller consists of the following elements

1. 16-bit program counter(PC)2. 16-bit status registers ST0, ST1, processor mode status register and circular

buffer control register(CBCR)3. (16x16)-bit hardware stack4. Address generation logic

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5. Instruction register6. Interrupt flag register and interrupt mask register.

E) Flags in the Status Registers : The status registers can be stored into data memory and loaded from data memory, thereby allowing the `C5X status to be saved and restored for subroutines. The ST0 and ST1 each have an associated 1-level deep shadow register stack for automatic context-saving when an interrupt trap is taken.The functions of the bits in ST0 and ST1 can be given as

ARP(Auxiliary Register Pointer): These bits select the AR to be used in indirect addressing. When the ARP is loaded, the previous ARP value is copied to the auxiliary register buffer in ST1.

OV(Overflow) Flag bit: This bit indicates that an arithmetic operation overflow in the ALU.

OVM(Overflow Mode)bit: this bit enable/disables the accumulator overflow saturation mode in the ALU.

INTM(Interrupt Mode)bit: This bit globally masks or enables all interrupts. The INTM bit has no effect on the non-maskable active low RS and NMI interrupts.DP (Data Memory Page Pointer) bits: These bits specify the address of the current data memory page. The DP bits are concatenated with the LSBs of an instruction word to from a direct memory address of 16 bits.

ARB (Auxiliary Register Buffer): This 3-bit field holds the previous value contained in the ARP in ST0. Whenever the ARP is loaded, the previous ARP value is copied to the ARB, except when using the LST#0 instruction. When the ARB is loaded using the LST#1 instruction, the same value is also copied to the ARP.

CNF (On-Chip RAM Configuration Control Bit): The CNF bit can be modified by the LST#1 instruction. When CNF is 0, on-chip DARAM block 0 is mapped to data memory and CNF is 1, on-chip DARAM block 0 is mapped to program memory.

TC (Test/Control) Flag Bit: this 1-bit flag stores the results of the ALU or parallel logic unit test bit operations. The status of the TC bit determines if the conditional branch, call and return instructions are to be executed.

SXM (Sign Extension Mode Bit): The SXM bit does not affect the operations of certain arithmetic of logical instructions. This bit enable/disables sign extension of an arithmetic operation.

C (Carry Bit): This bit indicates an arithmetic operation carry or borrows in the ALU. The single bit shift and rotate instructions affect the C bit.

HM (Hold Mode) bit: This bit determines whether the central processing unit stops or continues execution when acknowledging an active low HOLD signal.

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XF (Pin Status Bit): this bit determines the level of the external flag (XF) output pin.

PM (Product Shift Mode) bits: These bits determine the product shifter (P-Scaler) mode and shift value for the PREG output into the ALU.

F) On-Chip Memory : The `C5X architecture contains a considerable amount of on-chip memory to aid in system performance and integration. These are

PROGRAM ROM: All the `C5X DSPs carry a 16-bit on-chip maskable programmable ROM. This memory is used for booting program code from slower external ROM or EPROM to fast on-chip or external RAM. Once the custom program has been booted into RAM, the boot ROM space can be removed from program memory space by setting the MP/MC bit in the processor mode status register. The on-chip ROM is selected at reset by driving the MP/MC pin low. If the on-chip ROM is not selected, the `C5X devices start execution from off-chip memory.

DATA/PROGRAM DUAL-ACCESS RAM: All `C5X DSPs carry a 1056-word X 16-bit on-chip dual-access RAM (DARAM). The DARAM is divided into three individually selectable memory blocks. 512-word data or program DARAM block B0, 512-word data DARAM block B1 and 32-word data DARAM block B2. The DARAM is primarily intended to store data values but, when needed, can be used to store programs as well. DARAM block B0 can be configured by software as data or program memory.

DATA/PROGRAM SINGEL-ACCESS RAM: `C5X DSPs carry a 16-bit on-chip single access RAM (SARAM) of sizes varying from 1-9Kx16 words. The SARAM can be configured by software as data memory, as program memory or combinations of both data memory and program memory. The SARAM is divided into 1K and/or 2K word blocks contiguous in address memory space. All `C5X CPUs support parallel accesses to these SARAM blocks. One SARAM block can be accessed only once per machine cycle.

G) On-Chip Peripherals : All `C5X DSPs have the same CPU structure; however, they have different on-chip peripherals connected to their CPUs. The `C5X DSPs on-chip peripherals available are

CLOCK GENERATOR: The clock generator consists of an internal oscillator and a phase locked loop circuit. The PLL circuit can generate an internal CPU clock by multiplying the clock source by a specific factor and so a clock source with a frequency lower than that of the CPU can be used.

HARDWARE TIMER: A 16-bit hardware timer with a 4-bit prescaler is available. This programmable timer clocks at a rate that is between ½ and 1/32 of the machine cycle (CLKOUT1), depending upon the timer’s divide-down ration. The timer period register defines the period for the timer. The 16-bit timer control register controls the operations of the timer.

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SOFTWARE PROGRAMMABLE WAIT STATE GENERATOR: Software programmable wait state logic is incorporated in `C5X DSPs allowing wait state generator without any external hardware for interfacing with slower off-chip memory and I/O devices. Each circuit is user programmable to operate in different wait states for off-chip memory accesses.

PARALLEL I/O PORTS: A total of 64K I/O ports are available, 16 of these ports are memory mapped in data memory space. The memory-mapped I/O ports can be accessed with any instruction that reads from or writes to data memory. The IS signal indicates a read or write operation through an I/O port.

HOST PORT INTERFACE: The HP1 is available on the `C57s and `LC57. it is an 8-bit parallel I/O port that provides an interface to a host processor.

SERIAL PORT: Three different kinds of serial ports are available; a general purpose serial post, a time division multiplexed (TDM) serial port and a buffered serial port (BSP). Each`C5X contains at least one general purpose, high speed synchronous, full duplexed serial port interface that provides direct communication with serial devices such as codecs, serial A/D converters and other serial systems. The serial port transmitter and receiver are double-buffered and individually controlled by maskable external interrupt signals. The serial port is capable of operating at up to one-fourth the machine cycle rate.

BUFFERED SERIAL PORT: The BSP is available on the `C56 and `C57 devices. It is a full duplexed, double-buffered serial port and an auto buffering unit. The BSP provides flexibility on the data stream length. The BSP has a 2K word buffer, which resides in the `C5X internal memory.

TDM SERIAL PORT: The TDM serial port available on the `C50, `C51 and `C53 devices are a full-duplexed serial port that can be configured by software either for synchronous operations or for time division multiplexed operations. The TDM serial port is commonly used in multiprocessor applications.

USER MASKABLE INTERRUPTS: Four external lines (active low INT1-INT4) and five internal interrupts, a timer interrupt and four serial port interrupts are user maskable. When an ISR is executed, the contents of the program counter are saved on an 8-level hardware stack, and the contents of 11 specific CPU registers, ACC, ACCB, PREG, ST0, ST1, PMST, TREG0, TREG1, INDX and ARCR are saved in one deep stack.

TMS 320C 67X

The C6000 devices execute up to eight 32-bit instructions per cycle. The C67x device’s core CPU consists of 32 general –purpose registers of 32-bit word length and eight functional units. These eight functional units contain:

Two multipliers Six ALUs

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The C600 generations has a complete set of optimised tools, including an efficient C compiler, an assembly optimiser for simplified assembly language programming and scheduling and a window based debugger interface for visibility into source code execution characteristics .A hardware emulation board, compatible with the TI XDS510E emulator interface is also available. This tool compiles with IEEE Standard Test Port and Boundary –scan Architecture.

Features of the C6000 devices include:

Advanced VLIW CPU with eight functional units, including two multipliers and six arithmetic units.

Executes up to eight instructions per cycle for up to tn times the performance of typical DSPs.

Allows designers to develop highly effective RISC-like code for fast development time

Instructions packing Gives code size equivalence for eight instructions executed serially or in parallel Reduces code size, program fetches, and power consumption Conditional execution of all instructions Reduces costly branching Increases parallelism for higher sustained performance Efficient code execution on independent functional units Industry’s most efficient C compiler on DSP benchmark suite Industry’s first assembly optimiser for fast development and improved

parallelization 8/16/32-bit data support, providing efficient memory support for a variety of

applications.

40-bit arithmetic options add extra precision for vocoders and computationally intensive applications.Saturation and normalization provide support for key arithmetic operationsField manipulation and instruction extract, set, clear and bit counting sup-port common operation found in control and data manipulation applications. The C67s has these additional features:Hardware support for single-precision (32-bit) , double-precision (64-bit) IEEE floating-point operations and 32_32-bit integer multiply with 32-or 64-bit result.

ARCHITECTURE OVERVIEW

The C6000 devices come with program memory, which, on some devices, can be used as a program cache. The devices also have varying sizes of data memory. Peripherals such as a direct memory access (DMA) controller, power down logic, and external memory interface (EMIF) usually come with the CPU, while peripherals such as serial ports are on only certain devices.

17


CENTRAL PROCESSING UNIT (CPU):

The C67x CPU, shaded in figure 1,is common to all the C67x devices. The CPU contains:

1. Program fetch unit 2. Instruction dispatch unit, advanced instruction packing (C64 only).3. Instruction decode unit4. Two data paths, each with four functional units5. 32-32bit registers,6. Control registers7. Control logic8. Test, emulation, and interrupt logic

The program fetch, instruction dispatch, and instruction decode units can deliver up to eight 32-bit instructions to the functional units every CPU clock cycle. The processing of instructions occurs in each of the two data paths(A and B), each of which contains four functional units (.L, .S, .M, and .D) and 16 32-bit general purpose registers for the C67x. A control register file provides the means to configure and control various processor operations. To understand how instructions are fetched, dispatched, decoded, and executed in the data path.

INTERNAL MEMORY:

18


The C67x have a 32-bit, byte-addressable address space. Internal (on-chip) memory is organized in separate data and program spaces. When off-chip memory is used, these spaces are unified on most devices to a single memory space via the external memory interface(EMIF). The C67x have two 32-bit internal ports to access internal data memory. The C67x have a single internal port to access internal program memory, with an instruction- fetch width of 256 bits.

MEMORY AND PERIPHERAL OPTIONS:o A variety of memory and peripheral options are available for the C6000 plat-

form:

Large on-chip RAM, up to 7M bits. Program cache. 2-level caches. 32-bit external memory interface supports SDRAM, SBRAM, SRAM

and other asynchronous memories for a broad range of external memory requirements and maximum system performance.

o DMA controller transfers data between address ranges in the memory map without intervention by the CPU. The DMA controller has four programmable channels and a fifth auxiliary channel.

o EDMA Controller performs the same functions as the DMA controller. The EDMA has 16 programmable channels, as well as a RAM space to hold multiple configurations for future transfers.

o HPI is a parallel port through which a host processor can directly access the CPU’s memory space. The host device has ease of access because it is the master of the interface. The host and the CPU can exchange information via internal or external memory. In addition, the host has direct access to memory-mapped peripherals.

o Expansion bus is a replacement for the HPI, as well as an expansion of the EMIF.

o The expansion provides two distinct areas of functionality (host port and I/O port) which can co-exist in a system. The host port of the expansion bus can operate in either asynchronous slave mode, similar to the HPI, or in synchronous master/slave mode. This allows the device to inter-face to a variety of host bus protocols. Synchronous FIFO and asynchronous peripheral I/O devices may interface to the expansion bus.

o McBSP (multichannel buffered serial port) is based on the standard serial port interface found on the TMS320C2000 and C5000 platform devices. In addition, the port can buffer serial samples in memory automatically with the aid of the DMA/EDNA controller.

19


o Timers in the C6000 devices are two 32-bit general-purpose timers used for these functions:

1. Time events2. Count events3. Generate pulses4. Interrupt the CPU5. Send synchronization events to the DMA/EDMA controller.

Power-down logic allows reduced clocking to reduce power consumption. Most of the operating power of CMOS logic dissipates during circuit switching from one logic state to another. By preventing some or all of the chip’s logic from switching, you can realize significant power savings without losing any data or operational context.

20


21


GENERAL-PURPOSE REGISTER FILES: ~ There are two general-purpose register files (A and B) in the C600 data paths.

Register files Applicable Devices A B A1:A0 B1:B0

C62x/C64x/C67x

A3:A2 B3:B2 A5:A4 B5:B4 A7:A6 B7:B6 A9:A8 B9:B8A11:A10 B10:B11A13:A12 B13:B12A15:A14 B15:B14

For the C67x DSPs, each of these files contains 16 32-bit registers (A0-A15 for the file A and B0-B15 for B file). The registers can be used for data, data address pointers, or condition registers.

The C67x general –purpose register files support data ranging in size from packed 16-bit data through 40-bit fixed-point and 4-bit floating point data.

Values larger than 32bits, such as 4-bit long and 64-bit float quantities are stored in register pairs. In these the 32 LSBs of data are placed in an even-numbered register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

There are 16 valid register bits for 40-bit and 64-bit data in the C67x cores as shown in Table below. In assembly language syntax, a colon between the register names denotes the register pars, and the odd-numbered register is specified first.

Operations requiring a long input ignore the 24MSBs of the odd-numbered register. Operations producing a long result zero-fill the 24 MSBs of the odd-numbered

register. The even-numbered register is encoded in the opcode.

TMS320C6713 DSP Features Highest-Performance Floating-Point Digital Signal Processor (DSP): Eight 32-Bit Instructions/Cycle 32/64-Bit Data Word 300-, 225-, 200-MHz (GDP), and 225-, 200-, 167-MHz (PYP) Clock Rates 3.3-, 4.4-, 5-, 6-Instruction Cycle Times 2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS /MFLOPS Rich Peripheral Set, Optimized for Audio

22


Highly Optimized C/C++ Compiler Extended Temperature Devices Available

Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core Eight Independent Functional Units: Two ALUs (Fixed-Point) Four ALUs (Floating- and Fixed-Point) Two Multipliers (Floating- and Fixed-Point) Load-Store Architecture With 32 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional

Instruction Set Features Native Instructions for IEEE 754 Single- and Double-Precision Byte-Addressable (8-, 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization

L1/L2 Memory Architecture 4K-Byte L1P Program Cache (Direct-Mapped) 4K-Byte L1D Data Cache (2-Way) 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-

Byte Additional L2 Mapped RAM

Device Configuration Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot Endianness: Little Endian, Big Endian

32-Bit External Memory Interface (EMIF) Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM 512M-Byte Total Addressable External Memory Space

Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)

16-Bit Host-Port Interface (HPI)

Two Multichannel Audio Serial Ports (McASPs)

Two Independent Clock Zones Each (1 TX and 1 RX)

Eight Serial Data Pins Per Port:

23


Individually Assignable to any of the Clock Zones

Each Clock Zone Includes: Programmable Clock Generator Programmable Frame Sync Generator TDM Streams From 2-32 Time Slots Support for Slot Size: 8, 12, 16, 20, 24, 28, 32 Bits Data Formatter for Bit Manipulation

Wide Variety of I2S and Similar Bit Stream Formats

Integrated Digital Audio Interface Transmitter (DIT) Supports: S/PDIF, IEC60958-1, AES-3, CP-430 Formats Up to 16 transmit pins Enhanced Channel Status/User Data

Extensive Error Checking and Recovery

Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces Two Multichannel Buffered Serial Ports: Serial-Peripheral-Interface (SPI) High-Speed TDM Interface AC97 Interface Two 32-Bit General-Purpose Timers Dedicated GPIO Module With 16 pins (External Interrupt Capable) Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module

IEEE-1149.1 (JTAG ) Boundary-Scan-Compatible Package Options:

208-Pin Power PAD™ Plastic (Low-Profile) Quad Flatpack (PYP) 272-BGA Packages (GDP and ZDP) 0.13-µm/6-Level Copper Metal Process

CMOS Technology

3.3-V I/Os, 1.2 -V Internal (GDP & PYP) 3.3-V I/Os, 1.4-V Internal (GDP)(300 MHz only

24


II. CODE-COMPOSER STUDIO

Code composer studio is used to build and debug embedded real time software applications. Code composer studio setup establishes the interface that allows code composer studio to communicate with target board or simulator. All windows (except edit windows) and all tool bars are dockable within the code composer studio environment. Hence we can move and align a window or toolbar to any portion of the code composer studio main window. We can also move dockable windows and toolbars out of the code composer studio main window and place them any where on the desktop. All code composer studio windows contain context menus. To open a context menu, right click within the window. Context menus provide a list of options and/or commands that can be applied to that particular window.

When program is loaded onto the target or simulator, the code composer studio debugger automatically opens a dis-assembly window. The dis-assembly window displays disassembled instructions and symbolic information needed for debugging. For each assembly language instruction, the dis-assembly window displays the disassembled instruction, the address at which the instruction is located, and the corresponding opcodes. In addition to view disassembled instructions in the dis-assembly window, the code composer studio debugger enables us to view the c source code interleaved with disassembled code.We can edit the memory locations in one of the following ways:-

1) In the memory window, double click on the data you wish to edit.2) Select the edit-> memory-> edit command.

Both of these methods open the edit memory dialog box.

Code composer studio incorporates an advanced signal analysis interface that enables developers to monitor signal data critically and thoroughly. The new features are useful in developing applications for communications, wireless, image processing, as well as general DSP applications. The graph menu contains many options that allow us to be flexible in how we display the data. We can use a time/frequency graph to view signals in either time or frequency domain.

The memory map tells the code composer studio debugger which areas of memory it can and cannot access. Typically, the map matches the memory definition in the linker command file. The watch window allows us to examine and edit variables and C expressions. In the watch window, we can expand and collapse complex expressions. We can also evaluate terms and display results in different formats. The quick watch feature allows to quickly adding variables to the watch window. Code composer studio provides integrated program management that is needed to build a target program or library.

A project records a) Filenames of source code and object libraries. b) Compiler, assembler and linker options c) Include file dependencies.

Code composer studio allows to collect execution statistics about specific areas in the code which is called as profiling.

PROCEDURE:

25


1. To run the CCS code software go to start -> programs -> Texas instruments and then code composer studio.

2. In setup code composes select functional little Indian, import, save and quit.3. Go to project, new and give the file name.4. Go to file, new and source file.5. Give or write the code in C language.6. Go to file and save it.7. Go to C drive -> ti-> my projects-> name->newname.c and save it.8. Go to project ->add files to project and select the program written.9. Go to project and add files to project10. Go to c drive-> ti-> c6000->cgtools->lib(file type should be object and library

files)->rst6700.lib.11. Go to c drive-> ti-> tutorial-> dsk6711->hello1->(file of type should be linker

command file)12. Go to command files->hello.cmd.13. Go to project and compile file.14. Go to project and then build.15. Go to file->load program-> open the file. In the window displayed the 1st

column we have address of memory and in 2nd column opcodes.16. Go to debug and run the program.17. View->graph->time/frequency.

In graph property dialog set the properties as per the requirement.

PRACTICE PROGRAM :

AIM: To write a program to generate a sinusoidal wave in C and execute it using code composer studio.

REQUIREMENTS: Code composer studio software.

Sample Programme

#include<stdio.h>#include<math.h>float y[360];main () { int i; for (i=0;i<360;i++) { y[i]=sin(2*3.14*2*i/360); if (i= = 360) i = 0; } }

Graph Settings And Waveform Output:

26


Extension: Students are expected to try for other standard signals like cosine, ramp and square wave.

27


iii. GENERATION OF VARIOUS SIGNALS AND SEQUENCES .

Pre requisite:-

1. Study all the Basic Signals and Sequences2. Study all the Functional Representations of Basic Signals and Sequences

objective:- : Generate various signals and sequences (Periodic and Aperiodic), such as Unit Impulse, Unit Step, Square, Saw Tooth, Triangular, Sinusoidal, Ramp, Sinc.

Equipment Required:-

1. MATLAB 7.02. Windows XP SP2

Procedure:- 1: give the amplitude of the signal 2: specify the time period of the signal 3: give the sequences 4: specify the size of the samples.

Program:-

1. Generate Sinusoidal signal

clear all;

close all;

clc;

N = input('Enter the number of cycles ...:: ');

t = 0:0.05:N;

x = sin(2*pi*t);

subplot(1,2,1);

plot(t,x);

xlabel('---------> Time');

ylabel('---------> Amplitude');

title('Sinusoidal');

subplot(1,2,2);

stem(t,x);

xlabel('---------> Time');


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title('Sinusoidal');

OUTPUT:-:-

Enter the number of cycles ...:: 2

2. Generate Unit Impulse function

clear all;

close all;

clc;

x = ones(1,1);

y = zeros(1,2);

z = [y, x, y];

stem(z);

xlabel('---------> Time');


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title('Unit Impulse');

OUTPUT:-

3. Generate Unit Step function

clear all;

close all;

clc;

x = ones(100);

subplot(2,1,1);

plot(x);

xlabel('---------> Time');


title('Step signal');

subplot(2,1,2);

stem(x);

xlabel('---------> Time');


title('Step signal');

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OUTPUT:-

4. Generate Ramp function

clear all;

close all;

clc;

t = 0:25;

y = t;

subplot(1,2,1);

plot(t,y);

xlabel('---------> Time');


title('Ramp function');

subplot(1,2,2);

stem(t,y);

xlabel('---------> Time');

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title('Ramp function');

OUTPUT:-

5. Generate Sawtooth Waveform

clear all;

close all;

clc;

N = input('Enter the number of cycles ...:: ');

t1 = 0:25;

t = [];

for i = 1:N,

t = [t,t1];

end;

subplot(2,1,1);

plot(t);

xlabel('---------> Time');


title('Sawtooth waveform');

subplot(2,1,2);

stem(t);

xlabel('---------> Time');

32



title('Sawtooth waveform');

OUTPUT:-

Enter the number of cycles ...:: 3

6. Generate Triangular Waveform

clear all;

close all;

clc;

N = input('Enter the number of cycles .....:: ');

M = input('Enter the period ....:: ');

t1 = 0:0.1:M/2;

t2 = M/2:-0.1:0;

t = [];

for i = 1:N,

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t = [t,t1,t2];

end;

subplot(1,2,1);

plot(t);

xlabel('---------> Time');


title('Triangular waveform');

subplot(1,2,2);

stem(t);

xlabel('---------> Time');


title('Triangular waveform');

OUTPUT:-

Enter the number of cycles .....:: 3Enter the period ....:: 4>>

7. Generate Square waveform

clear all;

close all;

clc;

N = input('Enter the number of cycles in a square wave....:: ');

M = input('Enter the period of the square wave ....:: ');

34


y=0:0.001:2;

for j=0:M/2:M*N;

x=y;

plot(j,x,'r');

hold on;

end

for k=0:M:M*N;

x=k+y;

m=2;

plot(x,m,'r')

hold on

end

for k=2:M:M*N;

x=k+y;

m=0;

plot(x,m,'r');

hold on;

end

hold off

axis([0 12 -0.5 2.5])

xlabel('time---->');

ylabel('Amplitude--->');

title('Square wave');

OUTPUT:-Enter the number of cycles in a square wave....:: 3Enter the period of the square wave ....:: 4

35


8. Generate Sinc function

clear all;

close all;

clc;

t = -3:0.1:3;

x = sin(pi*t)./(pi*t);

subplot(1,2,1); plot(x);

xlabel('---------> Time');


title('Sinc function');

axis([0,100,-0.5,1.0]);

subplot(1,2,2); stem(x);

xlabel('---------> Time');


title('Sinc function');

axis([0,100,-0.5,1.0]);

OUTPUT:-

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Result:-

Applications:- Basic signals are required for Signal & Image Processing

Viva Questions:-

1. What is subplot(), stem(), plot()?

2. What is xlabel(), ylabel(), title()?

3. What do you mean by time scale?

SUGGESTED BOOKS:-1. Signals and Systems : Principles, algorithm and applications – Prokias J Gard and D.G. Manolakis, 3rd Edition, PHI, 1996.2. Signals and Systems by Sanjith KMithra3. Signals and Systems by Oppenheim and Schafer

WEBSITES:-1. www.mathworks.com2. www.texasinstruments.com3. www.analogdevices.com4. www.wiley.com

37

http://www.analogdevices.com/

http://www.texasinstruments.com/

http://www.mathworks.com/


EXPERIMENT NO.1TO FIND DFT/IDFT OF A GIVEN DT SIGNAL

PREREQUISITE : Knowledge MATLAB and the understanding of Fast Fourier Transform (FFT) for analyzing the different plots.

I. Objective:

To compute the DFT/IDFT of a given sequence.

II. APPRATUS REQUIRED:

PC with XP Operating System, Code Composer Studio, DSK (TMS320C6713), USB port, 5 volts power supply.

MATLAB SOFTWARE 7.0

III ALGORITHM

1. Get the input sequence

2. Get the length of the sequence

3. Get the DFT of the sequence by using the formula

IV MATLAB PROGRAM:

clc

clear all

close all

x=input(‘enter the input sequence’);

n=20;

xk=fft(x,n);

k=0:1:n-1;

subplot(4,1,1);

stem(k,x);

xlabel('k');

ylabel('input sequence x');

subplot(4,1,2);

stem(k,abs(xk));

xlabel('k');

38


ylabel('mag of xk');

subplot(4,1,3);

stem(k,angle(xk));

xlabel('k');

ylabel('arg(x(k)');

x=ifft(xk);

subplot(4,1,4);

stem(x);

INPUT:

enter the input sequence: [1 1 1]

OUTPUT:

39


VIVA-VOCE QUESTIONS:

1. Define the term ‘linearity’2. Explain what is meant by the linearity of a system. Illustrate your answer with suitable

example3. What are problems associated with a nonlinear system?4. Discuss on whether linearity is an advantage or disadvantage to a system5. Has nonlinearity any advantage over linearily with regards to the operation of a system?

Illustrate your answer with suitable examples6. Define the terms

(a) Causality and time-variance(b) Illustrate the properties of causality and time-variance with suitable examples.

7. Explain the term convolution as applied to a system. Illustrate your answer with suitable examples.

X SUGGESTED BOOKS :

1. Digital signal Processing : Principles, algorithm and applications – Prokias J Gard and D.G. Manolakis, 3rd Edition, PHI, 1996.2. Digital Signal Processing by Sanjith KMithra3. Digital Signal Processing by Oppenheim and Schafer4. Digiatal Signal Proessing Lab Manual by Sanjith KMithra

XI WEBSITES

1. www.mathworks.com2. www.texasinstruments.com3. www.analogdevices.com4. www.wiley.com

40





EXPERIMENT NO.2TO FIND THE FREQUENCY RESPONSE OF A GIVEN SYSTEM.

I PREREQUISITE : Knowledge on MATLAB and the understanding of Frequency domain representations of Signals and Systems.

II OBJECTIVE: To write a program to plot the frequency response of a filter described by the difference equation y(n)=x(n)+0.9x(n-2)-0.4y(n-2), and change the range of PI using MATLAB

III APPARATUS REQUIRED: 1 Matlab Software.

2 Windows XP professional

IV ALGORITHM:

1. Get the numerator coefficients2. Get the denominator coefficients3. 6. Draw the frequency response

Mat lab program:

clcclear allclose allb=[1];a=[1,-.5];w=0:0.01:2*pi;[h]=freqz(b,a,w);subplot(2,1,1);plot(w/pi,abs(h));xlabel('normalized frequency');ylabel('magnitude');title('frequency response of first order systemh(n)=0.5.^nu(n)');subplot(2,1,2);plot(w/pi,angle(h));xlabel('normalized frequency');ylabel('phase in radians');

41


output:

Viva voce:

1. A casual system is one that can be convolved. Prove your statement.2. Define and explain what is meant by stability of a system3. Explain how the stability of a system can be determined4. What do you mean by periodic or circular convolution?5. What are the differences between regular and periodic convolutions?6. What do you mean by circular shift in a periodic sequence?

SUGGESTED BOOKS :

1. Digital signal Processing : Principles, algorithm and applications – Prokias J Gard and D.G. Manolakis, 3rd Edition, PHI, 1996.2. Digital Signal Processing by Sanjith KMithra3. Digital Signal Processing by Oppenheim and Schafer4. Digiatal Signal Proessing Lab Manual by Sanjith KMithra

WEBSITES1. www.mathworks.com2. www.texasinstruments.com3. www.analogdevices.com4. www.wiley.com

42





EXPERIMENT NO.3i.TO VERIFY THE LINEAR CONVOLUTION

I PREREQUISITE: Knowledge of C language and the understanding of mathematical equation for linear convolution are required for developing the program.

II OBJECTIVE: To write a program to find the linear convolution of two given sequences in matlab/ C and execute them using code composer studio discrete time sequences

III APPARATUS REQUIRED:Code composer studio software.Matlab software 7.0

IV ALGORITHM:

4. Get the first sequence intervals

5. Get the first sequence

6. Get the second sequence intervals

7. Get the second sequence

8. Get the convolution of the two sequence by using the formula

N-1 X (n) = Σ X (k) h (n-k)

K=0

Get the linear convolution output of the two sequences.

V MATLAB PROGRAM:

clc;

close all;

clear all;

x=input ('enter the first sequence');

h= input ('enter the second sequence');

y=conv(x,h);

figure;

subplot(3, 1, 1);

stem(x);

43


ylabel('amplitude');

xlabel('--->n');

title('input sequence 1');

subplot (3,1,2);

stem(h);


xlabel('--->n');

title('input sequence 2');

subplot(3,1,3);

stem(y);


xlabel('--->n');

title('output sequence');

disp('the resultant signal is');y

Input

enter the first sequence[1 1 1 1]

enter the second sequence[1 1 2 4]

OUTPUT

44


EQUIVALENT ‘C’ PROGRAM TO IMPLEMENT LINEAR CONVOLUTION

#include<stdio.h>

main(){ int m=4; /*Lenght of i/p samples sequence*/

int n=4; /*Lenght of impulse response Co-efficients */int i=0,j;int x[10]={1,2,3,4,0,0,0,0}; /*Input Signal Samples*/int h[10]={1,2,3,4,0,0,0,0}; /*Impulse Response Co-efficients*/

/*At the end of input sequences pad ‘M’ and ‘N’ no. of zero’s*/int y[10];

for(i=0;i<m+n-1;i++){y[i]=0;

for(j=0;j<=i;j++)y[i]+=x[j]*h[i-j];

}for(i=0;i<m+n-1;i++)printf("%d\n",y[i]);

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}

VI PROCEDURE:

Open Code Composer Studio, make sure the DSP kit is turned on.

Start a new project using ‘Project-new ‘ pull down menu, save it in a separate directory(c:\ti\myprojects) with name lconv.pjt.

Add the source files conv.asm to the project using ‘Projectadd files to project’ pull down menu.

Add the linker command file hello.cmd .(Path: c:\ti\tutorial\dsk6713\hello1\hello.cmd)

Add the run time support library file rts6700.lib(Path: c:\ti\c6000\cgtools\lib\rts6700.lib)

Compile the program using the ‘Project-compile’ pull down menu or by clicking the shortcut icon on the left side of program window.

Build the program using the ‘Project-Build’ pull down menu or by clicking the shortcut icon on the left side of program window.

Load the program(lconv.out) in program memory of DSP chip using the ‘File-load program’ pull down menu.

To View output graphically Select view graph time and frequency.

VII RESULT:

Thus the convolution of two sequences has been computed using C –language and MATLAB.

VIII APPLICATION:

To find the frequency response of LPF/HPF

IX VIVA-VOCE QUESTIONS:

1. Difine convolution?

46


2. Compare linear & circular convolution?3. How is circular convolution faster when compared to linear convolution?4. What are the drawbacks of linear convolution?5. How do linear and circular convolution vary regarding the no. of computations

requirements.6. How is multiplication of the DFTS of 2 Sequence is equivalent to the circular

convolution of the two sequences in the time domain?7. Compare the output response of both circular and linear convolution?8. What is zero padding? Give its importance?9. What are advance and disadvantages of linear and CC? performing convolution.10. Give the importance of circular shift in performing convolution.

SAMPLE PROGRAM : #include<stdio.h>#include<math.h>

int x[50],h[50],y[99]; main() { int m=6; int n=6; int i=0,j; int x[15]={1,2,3,4,5,6,0,0,0,0,0,0}; int h[15]={1,2,3,4,5,6,0,0,0,0,0,0}; for(i=0;i<m+n-1;i++) { y[i]=0; for(j=0;j<=I;j++) y[i]+=x[j]*h[i-j]; } for(i=0;i<m+n-1;i++) printf(“%d\n”,y[i]); }

Input : Input sequence is x= {1,2,3,4,5,6} Impulse response h={1,2,3,4,5,6}

Output: y[11]={1,4,10,20,35,56,70,76,73,60,36}Graph settings:

47


X SUGGESTED BOOKS : 1. Digital signal Processing : Principles, algorithm and applications – Prokias J Gard and D.G. Manolakis, 3rd Edition, PHI, 1996.2. Digital Signal Processing by Sanjith KMithra3. Digital Signal Processing by Oppenheim and Schafer4. Digiatal Signal Proessing Lab Manual by Sanjith KMithra

XI WEBSITES1. www.mathworks.com2. www.texasinstruments.com3. www.analogdevices.com4. www.wiley.com

48





EXPERIMENT NO.3ii.TO VERIFY THE CIRCULAR CONVOLUTION

I PREREQUISITE : Knowledge of C language and the understanding of mathematical equation for circular convolution is required for developing the program.

II OBJECTIVE : To write a program to find the circular convolution of two given sequences .

III APPARATUS REQUIRED:


MATLAB SOFTWARE 7.0

IV ALGORITHM:

1. Get the first sequence intervals 2. Get the first sequence 3. Get the second sequence intervals 4. Get the second sequence 5. Get the convolution of two sequences 6. Get the circular convolution output of given two sequences

V MATLAB PROGRAM:

clc;

clear all;

close all;

disp('circular convolution program');

x=input('enter i/p sequence of x.....');

m=length(x);

h=input('enter i/p sequence of h.....');

n=length(h);

49


disp('circular convolution of x & h is');

if(m-n~=0)

if(m>n)

h=[h,zeros(1,m-n)];

n=m;

end

x=[x,zeros(1,n-m)];

m=n;

end

y=zeros(1,n);

y(1)=0;

a(1)=h(1);

for j=2:n

a(j)=h(n-j+2);

end

%ciruclar conv

for i=1:n

y(1)=y(1)+x(i)*a(i);

end

for k=2:n

y(k)=0;

% circular shift

for j=2:n

x2(j)=a(j-1);

end

50


x2(1)=a(n);

for i=1:n

if(i<n+1)

a(i)=x2(i);

y(k)=y(k)+x(i)*a(i);

end

end

end

y

subplot(3,1,1);

stem(x);

title('i/p sequence x');

xlabel('--->n');

ylabel('--->amplitude');

subplot(3,1,2);

stem(h);

title('i/p sequence h');

xlabel('--->n');


subplot(3,1,3);

stem(y);

title('y=circular convolution of x & h');

xlabel('--->n');


51


INPUT:

circular convolution program

enter i/p sequence of x.....[1 1 1 2 1 1]

enter i/p sequence of h.....[1 1 2 1]

OUTPUT:

circular convolution of x & h is

y =

6 5 5 6 6 7

Program to Implement Circular Convolution

#include<stdio.h> int m,n,x[30],h[30],y[30],i,j,temp[30],k,x2[30],a[30];void main(){ printf(" enter the length of the first sequence\n"); scanf("%d",&m); printf(" enter the length of the second sequence\n"); scanf("%d",&n); printf(" enter the first sequence\n"); for(i=0;i<m;i++)

52


scanf("%d",&x[i]); printf(" enter the second sequence\n"); for(j=0;j<n;j++) scanf("%d",&h[j]); if(m-n!=0) /*If length of both sequences are not equal*/ {

if(m>n) /* Pad the smaller sequence with zero*/{for(i=n;i<m;i++)h[i]=0;n=m;}for(i=m;i<n;i++)x[i]=0;m=n;

} y[0]=0; a[0]=h[0]; for(j=1;j<n;j++) /*folding h(n) to h(-n)*/ a[j]=h[n-j]; /*Circular convolution*/ for(i=0;i<n;i++) y[0]+=x[i]*a[i]; for(k=1;k<n;k++) { y[k]=0; /*circular shift*/ for(j=1;j<n;j++)

x2[j]=a[j-1]; x2[0]=a[n-1]; for(i=0;i<n;i++) {

a[i]=x2[i];y[k]+=x[i]*x2[i];

} } /*displaying the result*/ printf(" the circular convolution is\n"); for(i=0;i<n;i++) printf("%d \t",y[i]); }

INPUT: Eg: x[4]={3, 2, 1,0}

h[4]={1, 1, 0,0}

OUT PUT y[4]={3, 5, 3,0}

53


PROCEDURE:

Open Code Composer Studio, make sure the DSP kit is turned on.

Start a new project using ‘Project-new ‘ pull down menu, save it in a separate directory(c:\ti\myprojects) with name lconv.pjt.

Add the source files conv.asm to the project using ‘Projectadd files to project’ pull down menu.

Add the linker command file hello.cmd .(Path: c:\ti\tutorial\dsk6713\hello1\hello.cmd)

Add the run time support library file rts6700.lib(Path: c:\ti\c6000\cgtools\lib\rts6700.lib)

Compile the program using the ‘Project-compile’ pull down menu or by clicking the shortcut icon on the left side of program window.

Build the program using the ‘Project-Build’ pull down menu or by clicking the shortcut icon on the left side of program window.

Load the program(lconv.out) in program memory of DSP chip using the ‘File-load program’ pull down menu.

To View output graphically Select view graph time and frequency.

MODEL CALCULATIONS:

n = 0.7000

x = 0.7343h = 1 2 3 4N2 = 1N3 = 4N = 8x = Columns 1 through 6

0.7343 0 0 0 0 0

Columns 7 through 8

0 0

h = 1 2 3 4 0 0 0 0

54


m = 0 1 2 3 4 5 6 7

M = 0 7 6 5 4 3 2 1

h = 1 0 0 0 0 4 3 2p = 0 1 2 3 4 5 6 7

q =

Columns 1 through 6

0.3000 1.3000 2.3000 3.3000 4.3000 5.3000

Columns 7 through 8

6.3000 7.3000

VII .RESULT:

Thus the Circular convolution of two sequences has been computed using C -language, ASM and MATLAB.

VIII. APPLICATION:

To find the frequency response of LPF/HPF


1. Difine convolution?2. Compare linear & circular convolution?3. How is circular convolution faster when compared to linear convolution?4. What are the drawbacks of linear convolution?5. How do linear and circular convolution vary regarding the no. of computations

requirements.6. How is multiplication of the DFTS of 2 Sequence is equivalent to the circular

convolution of the two sequences in the time domain?7. Compare the output response of both circular and linear convolution?8. What is zero padding? Give its importance?9. What are advance and disadvantages of linear and CC? performing convolution.10. Give the importance of circular shift in performing convolution.


55



56





EXPERIMENT NO.4IMPLEMENTATION OF FFT OF A GIVEN SEQUENCE .

I PREREQUISITE : Knowledge on MATLAB and the understanding of Frequency domain representations of signals.

II OBJECTIVE : To write a program to implement FFT algorithm in C and execute them using code composer studio.

III APPRATUS REQUIRED:


MATLAB SOFTWARE 7.0

IV ALGORITHM:

1. Get the input sequence 2. Get the length of FFT3 draw the plot

V PROGRAM:

clc;

clear all;

close all;

N=input('enter samples 2^m>=128)');

n=0:N-1;

ang1=2*pi*n/3;

ang2=8*pi*n/9;

x=3*cos(ang1+0.25*pi)-2*sin(ang2-0.3*pi);

X=fft(x,N);

Xm=abs(X);

M=max(Xm)+1;

subplot(1,1,1);grid;

axis([-1,N,0,M]);

plot(n,Xm);

ylabel('magnitude');

57


xlabel('index k');

title('frequency content');

VI MODEL CALCULATIONS

0 5 10 15 20 25 30 35 40 45 500

10

20

30

40

50

60

70

mag

nitu

de

index k

frequency content

VII. RESULT: The output results are matching with the Program steps

VIII. APPLICATION: This can be used to find frequency response of any DSP system

IX QUESTIONS:

1. How is discrete Fourier transform different from discrete time Fourier Transformation?

2. What do you mean by N-point DFT?

3. What are twiddle factors?

4. Explain the following

a. Decimation-in-time FFT algorithm

b. Decimation-in-frequency FFT algorithm

5. What do you mean by radix-R FFT algorithm, where R is an integer?

58


6. Obtain the number of computations involved in the case of N-point radix-2 DIT FFT

algorithm.

7. How many stages of decimations are required in the case of a 64-point radix-2 DIT FFT

algorithm?

8. What are butterfly diagrams?

9. How butterfly diagrams are useful in the computation of FFT algorithms?

10. What is meant by in- place computation in FFT



PROGRAMMain.c (fft 256.c):

#include <math.h> #define PTS 64 //# of points for FFT #define PI 3.14159265358979

typedef struct {float real,imag;} COMPLEX;

void FFT(COMPLEX *Y, int n); //FFT prototypefloat iobuffer[PTS]; //as input and output bufferfloat x1[PTS]; //intermediate buffer short i; //general purpose index variable short buffercount = 0; //number of new samples in iobuffer short flag = 0; //set to 1 by ISR when iobuffer full COMPLEX w[PTS]; //twiddle constants stored in w COMPLEX samples[PTS]; //primary working buffer

main(){ for (i = 0 ; i<PTS ; i++) // set up twiddle constants in w

59





{ w[i].real = cos(2*PI*i/(PTS*2.0)); //Re component of twiddle constants w[i].imag =-sin(2*PI*i/(PTS*2.0)); //Im component of twiddle constants } for (i = 0 ; i < PTS ; i++) //swap buffers { iobuffer[i] = sin(2*PI*10*i/64.0); /*10- > freq, 64 -> sampling freq*/ samples[i].real=0.0; samples[i].imag=0.0; } for (i = 0 ; i < PTS ; i++) //swap buffers { samples[i].real=iobuffer[i]; //buffer with new data } for (i = 0 ; i < PTS ; i++) samples[i].imag = 0.0; //imag components = 0

FFT(samples,PTS); //call function FFT.c

for (i = 0 ; i < PTS ; i++) //compute magnitude { x1[i] = sqrt(samples[i].real*samples[i].real

+ samples[i].imag*samples[i].imag); } }

fft.c:

#define PTS 64 //# of points for FFTtypedef struct {float real,imag;} COMPLEX;extern COMPLEX w[PTS]; //twiddle constants stored in w

void FFT(COMPLEX *Y, int N) //input sample array, # of points { COMPLEX temp1,temp2; //temporary storage variables int i,j,k; //loop counter variables int upper_leg, lower_leg; //index of upper/lower butterfly leg int leg_diff; //difference between upper/lower leg int num_stages = 0; //number of FFT stages (iterations) int index, step; //index/step through twiddle constant i = 1; //log(base2) of N points= # of stages

60


do { num_stages +=1; i = i*2; }while (i!=N); leg_diff = N/2; //difference between upper&lower legs step = (PTS*2)/N; //step between values in twiddle.h for (i = 0;i < num_stages; i++) //for N-point FFT { index = 0; for (j = 0; j < leg_diff; j++) { for (upper_leg = j; upper_leg < N; upper_leg += (2*leg_diff)) { lower_leg = upper_leg+leg_diff;

temp1.real = (Y[upper_leg]).real + (Y[lower_leg]).real; temp1.imag = (Y[upper_leg]).imag + (Y[lower_leg]).imag; temp2.real = (Y[upper_leg]).real - (Y[lower_leg]).real; temp2.imag = (Y[upper_leg]).imag - (Y[lower_leg]).imag; (Y[lower_leg]).real = temp2.real*(w[index]).real

-temp2.imag*(w[index]).imag; (Y[lower_leg]).imag = temp2.real*(w[index]).imag

+temp2.imag*(w[index]).real; (Y[upper_leg]).real = temp1.real; (Y[upper_leg]).imag = temp1.imag; } index += step; } leg_diff = leg_diff/2; step *= 2; } j = 0; for (i = 1; i < (N-1); i++) //bit reversal for resequencing data { k = N/2; while (k <= j) { j = j - k; k = k/2; } j = j + k; if (i<j) { temp1.real = (Y[j]).real; temp1.imag = (Y[j]).imag; (Y[j]).real = (Y[i]).real;

61


(Y[j]).imag = (Y[i]).imag; (Y[i]).real = temp1.real; (Y[i]).imag = temp1.imag; } } return;}

LAB WORK : The logic of the code will be explain in the lab. Students are expected to write the program and execute it for different inputsThey are also expected to check the output with the help of MATLAB.Input waveform

Waveform output:



62





EXPERIMENT NO.5DETERMINATION OF POWER SPECTRUM OF A GIVEN SIGNAL

I PREREQUISITE : Knowledge on MATLAB and the understanding of Frequency domain representations of Signals and Systems.

II. OBJECTIVE : To compute Power Density Spectrum of a sequence.

III. APPRATUS REQUIRED:

PC with XP Operating System, MATLAB

IV ALGORITHM:

1. Get the frequencies of the two sinusoidal waves2. Get the sampling frequency3. Get the length of the sequence to be considered4. Get the two FFT lengths for comparing the corresponding power spectral densities

IV MATLAB PROGRAM:

clc

clear all

close all

f1=input('enter the frequency of the first sinosoid');

f2=input('enter the frequency of the second sinosoid');

fs=input('enter the sampling frequency ');

N=input('enter the length of the input sequence');

N1=input('enter the FFT length1');

N2=input('enter the FFT length2');

t=0:1/fs:1;

x=2*sin(2*pi*f1*1)+3*sin(2*pi*f2*t)-randn(size(t));

pxx1=abs(fft(x,N1)).^2/(N+1);

pxx2=abs(fft(x,N2)).^2/(N+1);

subplot(2,1,1);

plot((0:(N2-1))/N2*fs,10*log10(pxx2));

xlabel('frequency');

ylabel('power spectrum in db');

title('psd with fft length');

63


input:Enter the frequency of the first sinosoid500enter the frequency of the second sinosoid400enter the sampling frequency 600enter the length of the input sequence4enter the FFT length14enter the FFT length22

output:

VIVA-VOCE

1. What is the need for spectral estimation?2. How can the energy density spectrum be determined?3. What is autocorrelation function?4. What is the relationship between autocorrelation and spectral density?5. Give the estimate of autocorrelation function and power density for random signals.6. Obtain the expression for mean and variance for the autocorrelation function of random

signals 7. Calculate the man and variance for the autocorrelation function of random signals.8. Give the time and frequency domain representation for Bartlett window.9. Explain how DFT and FFT are useful in power spectral estimation.10. Explain power spectrum estimation using the Bartlett method.11. What are the limitations of non-parametric method sin spectral estimation?



64





EXPERIMENT NO 6 and 7IMPLEMENTATION OF LP/HP FIR FILTERS

I PREREQUISITE : Knowledge MATLAB and the understanding of different windowing techniques is required for developing the program.

II OBJECTIVE: To design FIR filter (LP/HP/BP/BS) using windowing techniques .

III APPRATUS REQUIRED : MATLAB Software with help library

IV ALGORITHM

1. Get the stop band and pass band ripples. 2. Get the stop band and pass band edge frequencies.

3.Get the sampling frequency.4.calculate the order of the filter.5.Find the filter coefficients.6.Draw the O/P response.

V PROGRAMS:

%fir filt design using window techniques

clc;

clear all;

close all;

rp=input('enter passband ripple');

rs=input('enter the stopband ripple');

fp=input('enter passband freq');

fs=input('enter stopband freq');

f=input('enter sampling freq ');

wp=2*fp/f;

ws=2*fs/f;

num=-20*log10(sqrt(rp*rs))-13;

65


dem=14.6*(fs-fp)/f;

n=ceil(num/dem);

n1=n+1;

if(rem(n,2)~=0)

n1=n;

n=n-1;

end

c=input('enter your choice of window function 1. rectangular 2. triangular 3.kaiser 4.bartlett

5.blackman 6.hamming 7.hanning : \n ');

if(c==1)

y=rectwin(n1);

disp('Rectangular window filter response');

end

if (c==2)

y=triang(n1);

disp('Triangular window filter response');

end

if(c==3)

y=kaiser(n1);

disp('kaiser window filter response');

end

if(c==4)

y=bartlett(n1);

disp('bartlett window filter response');

end

66


if(c==5)

y=blackman(n1);

disp('blackman window filter response');

end

if(c==6)

y=hamming(n1);

disp('hamming window filter response');

end

if(c==7)

y=hanning(n1);

disp('hanning window filter response');

end

%LPF

b=fir1(n,wp,y);

[h,o]=freqz(b,1,256);

m=20*log10(abs(h));

subplot(2,2,1);plot(o/pi,m);

title('LPF');

ylabel('Gain in dB-->');

xlabel('(a) Normalized frequency-->');

%HPF

b=fir1(n,wp,'high',y);

[h,o]=freqz(b,1,256);

m=20*log10(abs(h));


67


title('HPF');


xlabel('(b) Normalized frequency-->');

%BPF

wn=[wp ws];

b=fir1(n,wn,y);

[h,o]=freqz(b,1,256);

m=20*log10(abs(h));


title('BPF');


xlabel('(c) Normalized frequency-->');

%BSF

b=fir1(n,wn,'stop',y);

[h,o]=freqz(b,1,256);

m=20*log10(abs(h));


title('BSF');


xlabel('(d) Normalized frequency-->');

68


Input: 1. Rectangular window

enter passband ripple0.05

enter the stopband ripple0.04

enter passband freq1500

enter stopband freq2000

enter sampling freq 9000

enter your choice of window function 1. rectangular 2. triangular 3.kaiser 4.bartlett

5.blackman 6.hamming 7.hanning :

1

Rectangular window filter response

OUTPUT:

69


Input: 2. Triangular window








2

Triangular window filter response

Output:

70


Input: 3. Kaiser window








3

kaiser window filter response

Output:

71


Input: 4.Barlett window








4

bartlett window filter response

Output:

72


Input: Blackman window








5

blackman window filter response

Output:

73


input: Hamming window








6

hamming window filter response

Output:

74


input: Hanning window








7

hanning window filter response

Output:

75


VII. RESULT:

Results are obtained as per the design program VIII. APPLICATION:

Isolation of noise signal and Processing of speech and voice signals.


1. With reference to digital filters, what do you mean by finite-impulse response2. Discuss the basic principles involved in the design of FIR filters.3. Why FIR filters are called constant-phase filters?4. Discuss the principles behind the Design of FIR filters using

Fourier series method5. Discuss the principles behind the Design of FIR filters using

Using Windowing technique 6. Discuss the principles behind the Design of FIR filters using

Frequency sampling method7. What is Gibb’s phenomenon?8. What are commonly used windows?9. Compare the advantages and disadvantages of various window functions10. Discuss the features of FIR filter using the Kaiser’s approach.



76





EXPERIMENT NO.8IMPLEMENTATION OF LP IIR FILTERS


I. Objective: MATLAB Program to find frequency response of Analog LP/HP filters (a) Butterworth filter.(b) Chebyshev Filter

II. APPRATUS REQUIRED: PC with XP Operating System, MATLAB

SPECIFICATION: MATLAB7.5

III ALGORITHM: 1. Get the stop band and pass band ripples. 2. Get the stop band and pass band edge frequencies.

3. Get the sampling frequency 4. Get the order of the filter. 5. Find the filter coefficients. 6. Draw the frequency response.

Butterworth lp

Program:

clc;

close all;

clear all;

format long

rs=input('enter the stopband ripple....');

rp=input('enter the passband ripple....');

ws=input('enter the stopband freq....');

wp=input('enter the passband freq....');

fs=input('enter the sampling freq....');

77


w1=2*wp/fs;

w2=2*ws/fs;

[n,wn]=buttord(w1,w2,rp,rs,'s');

[z,p,k]=butter(n,wn);

[b,a]=zp2tf(z,p,k);

[b,a]=butter(n,wn,'s');

w=0:0.01:pi;

[h,om]=freqs(b,a,w);

m=20*log10(abs(h));

an=angle(h);

subplot(2,1,1);

plot(om/pi,m);

ylabel('--->gain in db');

xlabel('--->normalized frequency');

subplot(2,1,2);

plot(om/pi,an);

ylabel('--->phase in radians');


INPUT:

enter the stopband ripple....60

enter the passband ripple....0.15

enter the stopband freq....3000

enter the passband freq....1500

enter the sampling freq....7000

78


output:

CHEBY1 LP

clc;

close all;

clear all;

format long






w1=2*wp/fs;

79


w2=2*ws/fs;

[n,wn]=cheb1ord(w1,w2,rp,rs);

[b,a]=cheby1(n,rp,wn);

w=0:0.01:pi;

[h,om]=freqz(b,a,w);

m=20*log10(abs(h));

an=angle(h);

subplot(2,1,1);

plot(om/pi,m);



subplot(2,1,2);

plot(om/pi,an);



INPUT:





80



Output:

CHEBY2 LP

clc;

close all;

clear all;

format long






w1=2*wp/fs;

81


w2=2*ws/fs;


[b,a]=cheby2(n,rs,wn);

w=0:0.01:pi;


m=20*log10(abs(h));

an=angle(h);

subplot(2,1,1);

plot(om/pi,m);



subplot(2,1,2);

plot(om/pi,an);



input:






82


Output:

Viva-voce:

Define IIR Filters?2. Compare types of IIR files3. Give the importance of IIR filters over other types of filters?4. Give the advantages of IIR filters considering the co-efficient calculations5. Compare IIR filters regarding stability for higher order?6. What is an IIR filter? Compare its characteristics with an FIR filter.7. What are the requirements for converting a stable analog filter into a stable digital

filter?8. Obtain the mapping formula for the approximation of derivatives method using

backward difference>9. Comment on the stability of backward difference approximation for the derivative

method of transformation.10. Why is the forward difference formula for the approximation of derivatives not use?

SUGGESTED BOOKS : 1. Digital signal Processing : Principles, algorithm and applications – Prokias J Gard and D.G. Manolakis, 3rd Edition, PHI, 1996.2. Digital Signal Processing by Sanjith KMithra3. Digital Signal Processing by Oppenheim and Schafer

83


4. Digiatal Signal Proessing Lab Manual by Sanjith KMithra


84





EXPERIMENT NO.9IMPLEMENTATION OF HP IIR FILTERS


I. Objective : MATLAB Program to find frequency response of Analog HP filters (a) Butterworth filter.(b) Chebyshev Filter



III ALGORITHM: 1. Get the stop band and pass band ripples. 2. Get the stop band and pass band edge frequencies.

3. Get the sampling frequency 4. Get the order of the filter. 5. Find the filter coefficients. 6. Draw the frequency response.

BUTTERWORTH HP

Program:

clc;

close all;

clear all;

format long






85


w1=2*wp/fs;

w2=2*ws/fs;

[n,wn]=buttord(w1,w2,rp,rs,'s');

[b,a]=butter(n,wn,'high','s');

w=0:0.01:pi;


m=20*log10(abs(h));

an=angle(h);

subplot(2,1,1);

plot(om/pi,m);



subplot(2,1,2);

plot(om/pi,an);



input:






86


output:

CHEBY1 HP

clc;

close all;

clear all;

format long






w1=2*wp/fs;

w2=2*ws/fs;

[n,wn]=cheb1ord(w1,w2,rp,rs,'s');

87


[b,a]=cheby1(n,rp,wn,'high','s');

w=0:0.01:pi;


m=20*log10(abs(h));

an=angle(h);

subplot(2,1,1);

plot(om/pi,m);



subplot(2,1,2);

plot(om/pi,an);



input:






88


Output:

CHEBY2 HP

clc;

close all;

clear all;

format long






w1=2*wp/fs;

w2=2*ws/fs;

89



[b,a]=cheby2(n,rs,wn,'high');

w=0:0.01:pi;


m=20*log10(abs(h));

an=angle(h);

subplot(2,1,1);

plot(om/pi,m);



subplot(2,1,2);

plot(om/pi,an);



input:






90


Output:

VII. APPLICATION:

Isolation of noise signal and Processing of speech and voice signals.

VIII VIVA-VOCE QUESTIONS:

Define IIR Filters?2. Compare types of IIR files3. Give the importance of IIR filters over other types of filters?4. Give the advantages of IIR filters considering the co-efficient calculations5. Compare IIR filters regarding stability for higher order?6. What is an IIR filter? Compare its characteristics with an FIR filter.7. What are the requirements for converting a stable analog filter into a stable digital

filter?8. Obtain the mapping formula for the approximation of derivatives method using

backward difference>9. Comment on the stability of backward difference approximation for the derivative

method of transformation.10. Why is the forward difference formula for the approximation of derivatives not use?

91


SUGGESTED BOOKS : 1. Digital signal Processing : Principles, algorithm and applications – Prokias J Gard and D.G. Manolakis, 3rd Edition, PHI, 1996.2. Digital Signal Processing by Sanjith KMithra3. Digital Signal Processing by Oppenheim and Schafer4. Digiatal Signal Proessing Lab Manual by Sanjith KMithra


92





EXPERIMENT NO.10 IMPLEMENTATION OF INTERPOLATION PROCESS.

PREREQUISITE : Knowledge MATLAB and the understanding of different windowing techniques is required for developing the program.

I.Objective: To implement up sampling or interpolation.

II. APPRATUS REQUIRED: PC with XP Operating System, Code Composer Studio, DSK (TMS320C6713), USB port, 5 volts power supply.

MATLAB SOFTWARE 7.0

III ALGORITHM

1. Get the length of the sequence

2. Get the up sampling factor

3. Get the input signal frequency

4. Get the interpolated sequence.

Matlab program:

clc

clear all

close all


L=input('enter the up sampling factor:');

fi=input('input signal frequency');

n=0:N-1;

x=sin(2*pi*fi*n);

y=zeros(1,L*length(x));

y([1:L:length(y)])=x;

subplot(2,1,1);

stem(n,x);

title('input sequence');

93


xlabel('time');


subplot(2,1,2);

stem(n,y(1:length(x)));

title([' output sequence,upsampling factor=',num2str(L)]);

xlabel('time');


INPUT:

enter the length of the input sequence12enter the up sampling factor:3input signal frequency800

Output:

94




95





EXPERIMENT NO 11 IMPLEMENTATION OF DECIMATION PROCESS.


I. Objective: To implement down sampling or decimation

II. APPRATUS REQUIRED: PC with XP Operating System, Code Composer Studio, DSK (TMS320C6713), USB port, 5 volts power supply.

MATLAB SOFTWARE 7.0

III ALGORITHM

1. Get the length of the input sequence.

2. Get the Down sampling factor

3. Get the decimated sequence.

Matlab program:

clc

clear all

close all


n=0:1:N-1;

x=sin(2*pi*n/20)+sin(2*pi*n/15);

M=2;

x1=x(1:M:N);

n1=1:1:N/M

subplot(2,1,1);

stem(n,x);

title('input sequence');

xlabel('time');


subplot(2,1,2);

stem(n1-1,x1);

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title(' output sequence');

xlabel('time');


Input:

enter the length of the input sequence 20enter the down sampling factor:2input signal frequency 1000

Output:

VIVA VOCE:

1. What are the requirements for converting a stable analog filter into a stable digital filter?

2. Obtain the mapping formula for the approximation of derivatives method using backward difference>

3. Comment on the stability of backward difference approximation for the derivative method of transformation.

4. Why is the forward difference formula for the approximation of derivatives not use?

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EXPERIMENT NO 12IMPULSE RESPONSE OF FIRST ORDER AND SECOND ORDER SYSTEM.


I. Objective : MATLAB Program to find impulse response the given system



III ALGORITHM: 1. Get the numerator coefficients. 2. Get the denominator coefficients.

3. Draw the impulse response.Program

clc;

close all;

clear all;

a=input('enter the numerator coefficients');

b=input('enter the denominator coefficients');

x=[zeros(1,10),1,zeros(1,10)];

n=-10:1:10;

h=filter(a,b,x);

subplot(2,1,1);

stem(n,x);

title('input');

xlabel('--->n');

ylabel('--->x(n)');

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subplot(2,1,2);

stem(n,h);

title('impulse response');

xlabel('--->n');

ylabel('--->h(n)');

input

enter the numerator coefficients[1]

enter the denominator coefficients[1 -0.6 0.08]

OUTPUT

Viva voce:

1. What is the need for spectral estimation?2. How can the energy density spectrum be deterimined?3. What is autocorrelation function?4. What is the relationship between autocorrelation and spectral density?

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5. Give the estimate of autocorrelation function and power density for random signals.6. Obtain the expression for mean and variance for the autocorrelation function of random

signals 7. Calculate the man and variance for the autocorrelation function of random singals.8. Give the time and frequency domain representation for Bartlett window.9. Explain how DFT and FFT are useful in power spectral estimation.10. Explain power spectrum estimation using the Bartlett method.11. What are the limitations of non-parametric method sin spectral estimation



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EXPERIMENT NO.13IMPLEMENTATION OF I/D SAMPLING RATE CONVERSION


I. Objective : MATLAB Program to I/D sampling rate conversion

II. APPRATUS REQUIRED:

PC with XP Operating System, MATLAB

MATLAB7.0

III ALGORITHM: 1. Get the numerator coefficients. 2. Get the denominator coefficients.

3. Draw the impulse response.

MAT LAB PROGRAM:

clc;

close all;

clear all;

x = input('enter the input sequence....');

L = input('Up-sampling factor = ');

M = input('Down-sampling factor = ');

n=length(x);

k=0:n-1;

y = resample(x,L,M);

subplot(2,1,1);

stem(k,x);

title('Input Sequence');

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xlabel('Time index n');

ylabel('Amplitude');

subplot(2,1,2);

m = 0:(n*L/M)-1;

stem(m,y(1:n*L/M));

title('Output Sequence');

xlabel('Time index n');

ylabel('Amplitude');

INPUT:

enter the input sequence....[1 2 3 4 5 6]Up-sampling factor = 2Down-sampling factor = 3

OUTPUT:

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Dsp Manual Final

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