DSP-C Compiler Development
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Transcript of DSP-C Compiler Development
DSP-C Compiler DevelopmentDSP-C Compiler Development
Objective of presentationObjective of presentation
• To demonstrateTo demonstrate• DSP C Compiler development at acmeDSP C Compiler development at acmett
• Process followed for DSP C Compiler developmentProcess followed for DSP C Compiler development
Sequence of presentationSequence of presentation
• Customer Requirement StudyCustomer Requirement Study• Time Estimation On RequirementTime Estimation On Requirement• Development Model ChosenDevelopment Model Chosen• DSP C Compiler Team FormationDSP C Compiler Team Formation• Development ProcessDevelopment Process• DSP-C Compiler ConstructionDSP-C Compiler Construction• DSP-C Compiler MaintenanceDSP-C Compiler Maintenance• ConclusionConclusion
Duration of presentationDuration of presentation
• Estimated TimeEstimated Time :: ~ 60 Minutes ~ 60 Minutes
Customer Requirement StudyCustomer Requirement Study
Customer Requirement DefinitionCustomer Requirement Definition
• DSP C Cross Compiler for target DSP processorDSP C Cross Compiler for target DSP processor• Windows platformWindows platform• Compile DSP C programCompile DSP C program• Generate assembly code for target DSP processorGenerate assembly code for target DSP processor• Generate ‘C’ source level debugging informationGenerate ‘C’ source level debugging information
DSP C Compiler
Windows
DSP C Program
Target DSP Assembly
With Debug Information
Studied Customer RequirementStudied Customer Requirement
Architecture size
16-bit fixed point DSP
Instruction Set 16bit / 32bit variable-length instruction set
Register 8 general-purpose data registers (40 bits) 8 base address registers (16 bits) 4 index address registers (16 bits) A stack pointer register (16 bits) Program Counter (16 bit) Control / Status register
Memory Program Memory (64 K Word * 4 Page) 2 memory banks (64 K Word each)(1 Word = 16 Bits)
Addressing modes
Direct addressing Register indirect Register indirect with post increment Register indirect with post index modify Register indirect with post displacement modify Modulo addressing Bit-reversed addressing Program memory addressing Absolute addressing PC Relative
Hardware Loop Yes
Components 2 Address Generation Units 1 Multiplier
16bit * 16bit MAC unit 40bit ALU 40bit Barrel Shifter Bit manipulation computing unit (bit extraction and bit
insertion)
• Target DSP processor Target DSP processor architecture to be architecture to be supportedsupported
• ISO DSP C ISO DSP C SpecificationSpecification
• ISO C SpecificationISO C Specification
Proposed Solution For Customer Proposed Solution For Customer RequirementRequirement
• Development platformDevelopment platform• Windows 2K,XP
• Development languageDevelopment language• C
• Development toolsDevelopment tools• Microsoft VC, Numega, QAC
• Documentation toolsDocumentation tools• Microsoft Office, DOXYGEN
• Version controlVersion control• CVS
• Defect trackingDefect tracking• acmet Defect Tracking
System
• Time trackingTime tracking• acmet Time Tracking System
Preprocessed
file(s)
Error listing
file(s)
Assembly
file(s)
Prototype
file(s)
Call tree
file
Error Handler
Symbol-table
handler
Preprocessed C statements
Stream of C statements
Input processing
Preprocessing
Lexical Analysis
Syntax Analysis
Semantic Analysis
Loop Optimization &
intermediate code generation
Global Optimization
Loop Optimization
Code generation & register allocation
ILP and Memory Organization
Option list file
C source file
Stream of tokens
Parse tree
Parse tree
Intermediate code
Modified intermediate code
Modified intermediate code
Assembly code
Approval/Approval/FeedbackFeedback
Understanding,Understanding,ProposalProposal
Customer ApprovalCustomer Approval
• Confirmed understanding on requirementConfirmed understanding on requirement• Got approval for proposal from customerGot approval for proposal from customer
acmet Customer
Time Estimation On RequirementTime Estimation On Requirement
Time Estimation – OverviewTime Estimation – Overview
Send to Customer for Send to Customer for ApprovalApproval
Identify tasks/Identify tasks/ sub-taskssub-tasks
Peer reviewPeer review
Estimate time requiredEstimate time required
Peer reviewPeer review
CorrectioCorrectionsns
CorrectioCorrectionsns
Past data not
available
Past data Available
Customer RequirementCustomer Requirement
NoNo
NoNo
YesYes
YesYes
GuesstimationGuesstimation
Time EstimationTime Estimation
• Created Work Break-down Structure (WBS)Created Work Break-down Structure (WBS)• Estimated time for each activity in the WBSEstimated time for each activity in the WBS
• GuesstimationGuesstimation• Past experiencePast experience
• Calculated overall time estimation ‘T’ = t1 + t2 + … + t12Calculated overall time estimation ‘T’ = t1 + t2 + … + t12
DSP C CompilerDSP C Compiler
Front-endFront-end Back-endBack-end
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
t11 t12
TT
Development Model ChosenDevelopment Model Chosen
Development Model ChosenDevelopment Model Chosen
• Incremental Development ModelIncremental Development Model• Construction of a software in a series of mini life Construction of a software in a series of mini life
cycles (increments)cycles (increments)
• Output of each increment is a usable product to Output of each increment is a usable product to the customerthe customer• Functional specificationFunctional specification• Design documentDesign document• User’s manualUser’s manual• ExecutableExecutable• Source codeSource code• Quality assurance informationQuality assurance information
• Evaluation reportsEvaluation reports• QAC reportQAC report• True coverage reportTrue coverage report
Incremental Development modelIncremental Development model
Stage n: Detailed design, code, debug, test, and Stage n: Detailed design, code, debug, test, and deliverydelivery
Stage 2: Detailed design, code, debug, test, and Stage 2: Detailed design, code, debug, test, and deliverydelivery
ArchitecturArchitectural Designal Design
RequiremeRequirement Analysisnt Analysis
RequiremeRequirement nt
DefinitionDefinition
Stage 1: Detailed design, code, debug, test, and Stage 1: Detailed design, code, debug, test, and deliverydelivery
Measurement Measurement of Productivityof Productivity •ImplementationImplementation
•Problems discovered during Problems discovered during development can be solved development can be solved before the rest of the system is before the rest of the system is buildbuild
•Improves quality of the Improves quality of the final productfinal product
•ScheduleSchedule•Delay in schedule can be Delay in schedule can be identified earlieridentified earlier•Feedback on estimation from Feedback on estimation from previous increments can be previous increments can be used for further incrementsused for further increments
•Development team can see the product actually working
•A great boost to morale and leads to enhanced productivity
•Productivity can be measured in terms of the actual product
•Maintenance environment starts Maintenance environment starts earlyearly
•Limited scope and test-case Limited scope and test-case thoroughness can be achieved thoroughness can be achieved easilyeasily
•Identifies side effects at every Identifies side effects at every incrementincrement
•Increases the long-term success Increases the long-term success of the productof the product
•Customer can have better idea Customer can have better idea about meeting their requirementabout meeting their requirement
•Customer can revise their Customer can revise their requirement, if requiredrequirement, if required
Incremental Development model - Incremental Development model - AdvantagesAdvantages
Improved Improved Testing and Testing and MaintenanceMaintenance
Early Early Identification of Identification of
ProblemsProblems
Better Better Validation of Validation of RequirementRequirement
Measurement Measurement of Productivityof Productivity
Measurement Measurement of Productivityof Productivity
Improved Improved Testing and Testing and MaintenanceMaintenance
Improved Improved Testing and Testing and MaintenanceMaintenance
Early Early Identification of Identification of
ProblemsProblems
Early Early Identification of Identification of
ProblemsProblems
Better Better Validation of Validation of RequirementRequirement
Better Better Validation of Validation of RequirementRequirement
DSP C Compiler Team FormationDSP C Compiler Team Formation
DSP C Compiler Team FormationDSP C Compiler Team Formation
acmeacmett Process Training Process Training
Standards and Practices to be adopted, ‘C’ fundamentals, Ideal coding practices, Compiler fundamentals,
Debugging skills, Testing techniques
acmeacmett Process Training Process Training
Standards and Practices to be adopted, ‘C’ fundamentals, Ideal coding practices, Compiler fundamentals,
Debugging skills, Testing techniques
Studied DSP Studied DSP FundamentalsFundamentals
Studied DSP C Studied DSP C SpecificationSpecification
Studied Target DSP Studied Target DSP Processor Processor
ArchitectureArchitecture
Familiarized Target Familiarized Target DSP Assembly DSP Assembly InstructionsInstructions
Explored the following:Explored the following:•What is DSP?What is DSP?•Key features of a DSP processorKey features of a DSP processor•How is the DSP architecture How is the DSP architecture different from RISC/CISC different from RISC/CISC architecture?architecture?
Referred web articles and Referred web articles and tutorials for studytutorials for study
Explored the following:Explored the following:•What is DSP?What is DSP?•Key features of a DSP processorKey features of a DSP processor•How is the DSP architecture How is the DSP architecture different from RISC/CISC different from RISC/CISC architecture?architecture?
Referred web articles and Referred web articles and tutorials for studytutorials for study
Studied and understood the Studied and understood the features supported in DSP Cfeatures supported in DSP C
Referred study material:Referred study material:•DSP-C specificationDSP-C specification ISO/IEC DTR 18037:2005(E)ISO/IEC DTR 18037:2005(E)
Studied and understood the Studied and understood the features supported in DSP Cfeatures supported in DSP C
Referred study material:Referred study material:•DSP-C specificationDSP-C specification ISO/IEC DTR 18037:2005(E)ISO/IEC DTR 18037:2005(E)IA IF ID WB
EX
MD
REG
MA
Stage1 Stage2 Stage3 Stage4 Stage5 Stage6
•Studied key features of Target DSP Studied key features of Target DSP architecturearchitecture
•Addressing modesAddressing modes•Clipping/roundingClipping/rounding•Pipeline architecturePipeline architecture
•Explored Target DSP instruction Explored Target DSP instruction setset
•Explored Target DSP tools Explored Target DSP tools (Assembler, Linker, Debugger)(Assembler, Linker, Debugger)
•Studied key features of Target DSP Studied key features of Target DSP architecturearchitecture
•Addressing modesAddressing modes•Clipping/roundingClipping/rounding•Pipeline architecturePipeline architecture
•Explored Target DSP instruction Explored Target DSP instruction setset
•Explored Target DSP tools Explored Target DSP tools (Assembler, Linker, Debugger)(Assembler, Linker, Debugger)
MOVX R0, [b]; MOVX R0, [b];
MOVX R1, [c]; MOVX R1, [c];
ADD R2, R0, R1 MOVX R3, ADD R2, R0, R1 MOVX R3, [e];[e];
MOVX R4, [f]; MOVX R4, [f];
ADD R5, R3, R4 MOVX [a], ADD R5, R3, R4 MOVX [a], R2; R2;
MOVX [d], R5;MOVX [d], R5;
MOVX R0, [b]; MOVX R0, [b];
MOVX R1, [c]; MOVX R1, [c];
ADD R2, R0, R1 MOVX R3, ADD R2, R0, R1 MOVX R3, [e];[e];
MOVX R4, [f]; MOVX R4, [f];
ADD R5, R3, R4 MOVX [a], ADD R5, R3, R4 MOVX [a], R2; R2;
MOVX [d], R5;MOVX [d], R5;
•Hand-coded assembly programs for Hand-coded assembly programs for DSP application 'FFT'DSP application 'FFT'
•Gained in-depth knowledge on DSP Gained in-depth knowledge on DSP architecture advantagesarchitecture advantages
•Derived design rules and used it in Derived design rules and used it in developmentdevelopment
•Hand-coded assembly programs for Hand-coded assembly programs for DSP application 'FFT'DSP application 'FFT'
•Gained in-depth knowledge on DSP Gained in-depth knowledge on DSP architecture advantagesarchitecture advantages
•Derived design rules and used it in Derived design rules and used it in developmentdevelopment
Communication ProcessCommunication Process
Communication between team membersCommunication between team members
• Communication between team members is by Communication between team members is by means of e-mailmeans of e-mail
• Meeting/ Discussion is made in-case solution/ Meeting/ Discussion is made in-case solution/ conclusion could not be derived for a problem by conclusion could not be derived for a problem by means of e-mail communicationmeans of e-mail communication• Points discussed are recorded
• Record of Discussion (RoD)• Minutes of Meeting (MoM)
• RoD and MoM are sent to team by means of e-mail
• Peer Reviews are done offline by means of e-mail Peer Reviews are done offline by means of e-mail
Peer Review by means of e-mailPeer Review by means of e-mail
ArtifacArtifacttfor for reviewreview
ArtifacArtifacttfor for reviewreview
ArtifacArtifactt‘‘A’ for A’ for reviewreview
• Artifact for review is Artifact for review is sent to team sent to team • With deadline for
review
• Reviewers review at Reviewers review at their own pacetheir own pace• Within the deadline for
review• Send review
comments to team
• Update artifact based Update artifact based on review commentson review comments
• Send updated artifact Send updated artifact for reviewfor review
CommenComment on At on A
CommenComment on At on A
CommenComment on At on A
ArtifacArtifactt‘‘A’ for A’ for reviewreview
CommenComment on At on A
UpdateUpdateddArtifactArtifact‘‘A’A’
UpdateUpdateddArtifactArtifact‘‘A’A’
UpdateUpdateddArtifactArtifact‘‘A’A’
UpdateUpdateddArtifactArtifact‘‘A’A’
Communication Process - AdvantagesCommunication Process - Advantages
• Enhanced information sharingEnhanced information sharing• Record for future referenceRecord for future reference• Cross-check the understanding of team Cross-check the understanding of team
membersmembers• Peer reviews are done effectively since reviewer Peer reviews are done effectively since reviewer
can review the artifacts at his own pace within can review the artifacts at his own pace within the deadline timethe deadline time
Development ProcessDevelopment Process
Development Process - OverviewDevelopment Process - Overview
Initial StudyInitial Study
Input/ output Input/ output SpecificationSpecification
Design and Design and Algorithm writingAlgorithm writing
QA TestQA Test
Final ProductFinal Product
Coding and Coding and Unit testingUnit testing
Requirement Requirement from customerfrom customer
Clarification from Clarification from customer customer (if required)(if required)
Prepare Testing Prepare Testing check-sheetcheck-sheet
Generate BlackGenerate Blackbox test-casesbox test-cases
•Peer Review Peer Review •DiscussionDiscussion•MeetingsMeetings•Lessons learnt Lessons learnt from previous from previous incrementincrement
•Peer Review Peer Review •DiscussionDiscussion•MeetingsMeetings•Lessons learnt Lessons learnt from previous from previous incrementincrement
Coding and Unit Coding and Unit TestingTesting
Algorithm Writing Algorithm Writing and Verificationand Verification
Derive Input/Output Derive Input/Output SpecificationSpecification
Development Process – Detail ViewDevelopment Process – Detail View
Derive Design Derive Design StrategyStrategy
Quality Quality Assurance Assurance
TestTest
•QA-C TestQA-C Test•Maintain QA-C metrics for functionsMaintain QA-C metrics for functions•Cyclomatic Complexity (CYC)Cyclomatic Complexity (CYC)•Deepest level of nesting (MIF)Deepest level of nesting (MIF)•Static path count (PTH)Static path count (PTH)•Eliminate QA-C errors/warningsEliminate QA-C errors/warnings
•True Coverage TestTrue Coverage Test•Achieve 100% code coverageAchieve 100% code coverage•Identify and eliminate dead/unreachable codeIdentify and eliminate dead/unreachable code
•Integration TestIntegration Test•Black box testingBlack box testing•Standard compiler test-suitesStandard compiler test-suites
CorrectionCorrectionss
YesYes
Code ReviewCode Review
AlgorithmAlgorithm
NoNo
Passed ?Passed ? NoNo
Unit testingUnit testing
Make corrections/ Make corrections/ modificationsmodifications
Write unit testsWrite unit tests
CodingCoding
YesYes
Source CodeSource Code
Possible StrategiesPossible Strategies
Strategy 2Strategy 2•AdvantagesAdvantages•DisadvantagesDisadvantages
Strategy 1Strategy 1•AdvantagesAdvantages•DisadvantagesDisadvantages
Input/output Input/output specificationspecification
Best StrategyBest Strategy
Peer ReviewPeer ReviewTeam Team DiscussionsDiscussions
Send to customer Send to customer for confirmationfor confirmation
Strategy nStrategy n•AdvantagesAdvantages•DisadvantagesDisadvantages
Send to customer Send to customer for confirmationfor confirmation
Initial StudyInitial Study
Prepare input/output Prepare input/output specificationspecification
Reference Compiler Reference Compiler BehaviorBehavior
CorrectionCorrectionss
Customer Customer RequirementRequirement
NoNo
YesYes
Peer ReviewPeer Review
Update input/output Update input/output specificationspecification
Target DSP Target DSP Processor SpecificationProcessor Specification
Clarification fromClarification fromcustomercustomerTeam discussionsTeam discussions Write AlgorithmWrite Algorithm
CommentsComments
YesYes
Peer ReviewPeer Review
Make corrections/ Make corrections/ modificationsmodifications
Design StrategyDesign Strategy
Team Team DiscussionsDiscussions
AlgorithmAlgorithm
NoNo
Development Progress MonitorDevelopment Progress Monitor
• Daily progress in development is monitored by Daily progress in development is monitored by acmeacmett• Daily plan reportDaily plan report• Daily work done reportDaily work done report
• Customer is made aware with the progress of Customer is made aware with the progress of Compiler development on weekly basisCompiler development on weekly basis• Weekly work done reportWeekly work done report• Weekly progress tracking reportWeekly progress tracking report
• Gantt chartsGantt charts
• Incremental deliveryIncremental delivery
DSP C Compiler ConstructionDSP C Compiler Construction
for RISC Processorfor RISC ProcessorC CompilerC Compiler
Front-endFront-end
ISO C specific supportISO C specific support
Back-endBack-end
RISC processor specific RISC processor specific supportsupport
DSP C Compiler ConstructionDSP C Compiler Construction
DSP C CompilerDSP C Compiler
Front-endFront-end
ISO C specific supportISO C specific support
ISO DSP C specific ISO DSP C specific supportsupport
Back-endBack-end
DSP processor specific DSP processor specific supportsupport
for DSP Processorfor DSP Processor
• Used RISC compiler front-endUsed RISC compiler front-end• Modified RISC compiler front-end (legacy code) Modified RISC compiler front-end (legacy code)
to support DSP specific featuresto support DSP specific features• Constructed DSP C compiler back-end with DSP Constructed DSP C compiler back-end with DSP
specific featuresspecific features
• Code GenerationCode Generation
• MAC (MAC (MMultiply and ultiply and AcAccumulate) cumulate) Instructions SupportInstructions Support
• LRA (LRA (LLocal ocal RRegister egister AAllocation) llocation) SupportSupport
• Memory OrganizationMemory Organization• Instruction Level ParallelismInstruction Level Parallelism• Pipeline Hazards OptimizationsPipeline Hazards Optimizations• Conditional Instructions Conditional Instructions
SupportSupport• Bit Field Instructions SupportBit Field Instructions Support• Delay Slot Optimization Delay Slot Optimization
SupportSupport• PC Relative addressing SupportPC Relative addressing Support• Peephole OptimizationsPeephole Optimizations• Interrupt HandlingInterrupt Handling• Bit Reversal AddressingBit Reversal Addressing
• _X, _Y address space _X, _Y address space qualifiersqualifiers
• _Sat specifier_Sat specifier• FX_FRACT_OVERFLOW FX_FRACT_OVERFLOW
pragmapragma• FX_FULL_PRECISION FX_FULL_PRECISION
pragmapragma• Zero Overhead Loop Zero Overhead Loop
(ZOL)(ZOL)• Paged Program Memory Paged Program Memory
SupportSupport• Debug Information Debug Information
SupportSupport• Customer requirementsCustomer requirements
• _Circ qualifier_Circ qualifier• __REG qualifier__REG qualifier• ABS/NORM operatorsABS/NORM operators• BIT_REVERSAL pragmaBIT_REVERSAL pragma
DSP-C Compiler Front-end & Back-end DSP-C Compiler Front-end & Back-end SupportSupport
Back-endBack-end
DSP processor specific DSP processor specific supportsupport
Front-endFront-end
ISO C specific supportISO C specific support
ISO DSP C specific ISO DSP C specific supportsupport
DSP C Compiler in 6 incrementsDSP C Compiler in 6 increments
Increment 1
Increment 2
Increment 3
Increment 4
Increment 5
Increment 6
Duration: Staff months : 50 Calendar months : 5Task:•Enhancement in Instruction level Enhancement in Instruction level parallelismparallelism•Paged program memory supportPaged program memory support•Enhancement in MAC, ZOLEnhancement in MAC, ZOL•Peephole optimizationPeephole optimization
Duration:
Staff monthsStaff months : 25: 25
Calendar monthsCalendar months : 5: 5Task:•Hand code DSP application programs Hand code DSP application programs •DSP application study, G.729DSP application study, G.729•Understand requirement for the DSP Understand requirement for the DSP application application •Understand target DSP architecture Understand target DSP architecture featuresfeatures
Duration: Staff monthsStaff months : 8: 8
Calendar monthsCalendar months : 4: 4
Task:•Various DSP architecture studyVarious DSP architecture study•Suggestion for target DSP architecture Suggestion for target DSP architecture design from compiler point of viewdesign from compiler point of view•Overall functional specification Overall functional specification preparationpreparation
Duration: Staff months : 25 Calendar months : 2.5
Task:•Enhancement in Instruction level Enhancement in Instruction level parallelismparallelism•Pragma and interrupt supportPragma and interrupt support•Modulo addressing mode supportModulo addressing mode support•Perennial and PlumHall testingPerennial and PlumHall testing
Duration: Staff monthsStaff months : 66: 66
Calendar monthsCalendar months : 6: 6
Task:•Enhancement in Key DSP featuresEnhancement in Key DSP features•Support all the integral and the Support all the integral and the fraction data typesfraction data types•Debug information supportDebug information support•Conditional instruction supportConditional instruction support•Bit-field instruction supportBit-field instruction support
Duration: Staff monthsStaff months : 56: 56
Calendar monthsCalendar months : 8: 8
Task:•Support of following key DSP Support of following key DSP featuresfeatures
•Instruction Level ParallelismInstruction Level Parallelism•Memory managementMemory management•Post increment/ decrement Post increment/ decrement addressing modesaddressing modes•Zero overhead loopZero overhead loop•MACMAC
•Support of basic data types - Signed Support of basic data types - Signed integer, Signed _Fractinteger, Signed _Fract
Challenges FacedChallenges Faced
• Understand the complexity in DSP architecture Understand the complexity in DSP architecture • Front-end designFront-end design
• Used RISC compiler front-end• Work on legacy code
• Back-end designBack-end design• Location of modules• Interface between modules
• Interface between front-end and back-endInterface between front-end and back-end• Effective use of architectural advantagesEffective use of architectural advantages
• For example, • Instruction Level Parallelism (ILP)• Delay Slot Optimization (DSO)• Hardware Looping
DSP C Compiler MaintenanceDSP C Compiler Maintenance
DSP C Compiler MaintenanceDSP C Compiler Maintenance
• Fix defects Fix defects • Identified through acmeIdentified through acmett testing testing• Reported by customerReported by customer
• Defects to be fixed are chosen as per the Defects to be fixed are chosen as per the requirement of customerrequirement of customer
• Strictly follow acmeStrictly follow acmett defect fix process to avoid defect fix process to avoid degradationdegradation
Defect Fix Process - OverviewDefect Fix Process - Overview
Proposed CodeProposed CodeCorrectionCorrection
Write Unit TestsWrite Unit Tests
Unit TestingUnit Testing
QA TestQA Test
Code CorrectionCode Correction
Preliminary Preliminary AnalysisAnalysis
Defect Analysis Defect Analysis ReportReport
Prepare Testing Prepare Testing check-sheetcheck-sheet
Generate BlackGenerate Blackbox test-casesbox test-cases
•Peer Review Peer Review •DiscussionDiscussion•MeetingsMeetings•Lessons learnt Lessons learnt from previous from previous defect fixesdefect fixes
•Peer Review Peer Review •DiscussionDiscussion•MeetingsMeetings•Lessons learnt Lessons learnt from previous from previous defect fixesdefect fixes
Root Cause Root Cause AnalysisAnalysis
Final ProductFinal Product
ConclusionConclusion
ConclusionConclusion
• Current StatusCurrent Status• DSP C Compiler is delivered to customerDSP C Compiler is delivered to customer• Customer is satisfied with our serviceCustomer is satisfied with our service• Currently maintenance support is being provided Currently maintenance support is being provided
for the DSP C Compilerfor the DSP C Compiler
• Future PlanFuture Plan• Study and explore more optimization techniques Study and explore more optimization techniques
used for DSP applicationsused for DSP applications• Enhance the current optimization techniques we Enhance the current optimization techniques we
supportsupport