dsp blocks interfacing

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INTERFACING WITH

DSP BLOCKS

)


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A digital signal processor (DSP) is a specialized

microprocessor , with its architecture optimized for the

operational needs of digital signal processing.For

performing computations DSP processor needs to be

interfaced with various components such as AD, DA,

etc.

!hese modules need to be interfaced with the DSP bloc" to

wor" as a single entit#.

INTRODUCTION


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A general DSP bloc" consist of $

A multiplier

An adder%Subtractor%Accumulator bloc".

A F&AS' memor#.A SDA

D*P Switches


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+&- D*AA F !S/01234/ DS-


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A !e5as *nstruments !S/01234/ DSP operates at

006 'z .

*t has 42 b#tes of s#nchronous DA and 640-b#tes of non7volatile Flash memor# .

8 user accessible &9Ds and D*P switches

Software board configuration through registers

implemented in P&D

KEY FEATURES OF TMS320C!"3 DSP

PROCESSOR


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Standard e5pansion connectors for daughter card use

:!A emulation through on7board :!A emulator

with ;S+ host interface or e5ternal emulator

Single voltage power suppl# (


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!he DSP on the 234/ DS- interfaces to on7board

peripherals through a /07bit wide 9*F (95ternal

emor# *nterface).

!he SDA, Flash and P&D are all connected to the

bus.

9*F signals are also connected daughter card

e5pansion connectors

F#nctional O$er$ie% o& t'e

TMS320C!"3 DSK


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P&D(Programmable &ogic)$

*t is used to implement functionalit# specific to DS-.

*t acts as a >glue> logic that ties the board components

together. !he P&D implements simple random logic functions

that eliminate the need for additional discrete devices.

*t acts as a main controller which controls all thecomponent of DSP and provides necessar# signalling to

them.

DSP TMS320C!"3 DSK

COMPO(E(TS


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odec samples analog signal on the microphone or lineinput and converts them into digital data so it can be

processed b# DSP.

!he codec communicates using two serial channels,

one to control the codec?s internal configurationregisters and one to send and receive digital audio

samples.

!he codec has a 40'z s#stem cloc".

A)C23 codec


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F&AS' 9@

Flash memor# is an electronic (solid7state) non7volatile

computer storage medium that can be electricall#

erased and reprogrammed

Flash can be erased in large bloc"s commonl# referred

to as sectors or pages. nce a bloc" has been erased

each word can be programmed once through a special

command seuence.


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Memory Map, C67!DSK


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D*P SB*!'9S !he DS- includes 8 software accessible &9Ds (D37

D41) and D*P switches (SB4).

*t provide the user a simple form of input%output. +oth

are accessed through the P&D ;S9C9 register.


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!here are certain *% devices which handle transfer of

one bit at a time. Such devices are referred to as serial

*% devices or peripherals.

ommunication with serial peripherals can be

s#nchronous, with processor cloc" as reference or it

can be as#nchronous.

CODEC INTERFACING WITHDSP


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D9, a coder7decoder is an e5ample for s#nchronous

serial *%. *t has Analog input7output, AD and DA.

A coded is a device or computer program for encoding or

decoding a digital data stream or signal.

!he signals in SS* generated b# the DSP are$

D$ Data !ransmit to D9.

D$ Data eceive from D9.

&-$ !ransmit data with this cloc" reference.


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&-$ eceive data with this cloc" reference.

FS$ Frame s#nc signal for transmit.

FS$ Frame s#nc signal for receive, First bit, during

transmission or reception, is in s#nc with these signals.D@$ indicator for receiving all bits of data.

D@$ indicator for transmitting all bits of data.


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n the D9 side, signals are$

FSE$ Frame s#nc signal.

D*$ Data eceive from DSP.

D;!$ Data !ransmit to DSP.

S&-$ !5 % 5 data with this cloc" reference.


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SS* between DSP and D9


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!he receiving or transmit activit# is initiated at the

rising edge of cloc", &-% &-. eception %!ransfer starts after FS % FS remains high for one

cloc" c#cle.

D@ % D@ is initiall# high, goes &B to '*'

after the completion of data transfer.

9ach transfer of bit reuires one cloc" c#cle.


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Receive Timing for SSI


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Transmit Timing for SSI


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CODEC PCM3002

Block diagram for CODECPCM3!


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Analog front end samples signal at 28 over sampling

rate.

AD is based on Delta7sigma modulator to convert

analog signal to digital form.

Decimation filter reduces the sampling rate and thus

processing does not need high speed devices.

DA is Delta7sigma modulator, converts digital signal

to analog signal.


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&PF smoothens the analog reconstructed signal b#

removing high freuenc# components.

!he Serial *nterface monitors serial data transfer. *t

accepts built7in AD output and converts to serial data

and transmits the same on D;!. *t also accepts serial

data on D* G gives the same to DA.

!he serial interface wor"s in s#nchronization with

+&-* G &*.


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!he ode ontrol initializes the serial data transfer. *t

sets all the desired modes, the number of bits and the

mode ontrol Signals, D, and &. D carries

ode Bord. is the mode loc" Signal, D to be loaded is sent

with reference to this cloc", & is the mode &oadSignal. *t defines start and end of latching bits into

D9 device.


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P/110 D9 handles data size of 42 % 01 bits. *t has 285 over7sampling, delta sigma AD G DA.

*t has two channels, called left and right. !he D9

is programmable for digital de7emphasis, digital

attenuation, soft mute, digital loop bac", power7down

mode.

S#stem cloc", S@S&- of D9 can be 062fs,

/H8fs or 640fs. *nternal cloc" is alwa#s 062fs for

converters, digital filters.

Speci&ication o& CODEC PCM 3002


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D*, D;! are the single line data lines to carr# the

data into the D9 and from D9.

&* is frame s#nc signal for &eft and ight

hannels.


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THANK "OU

dsp blocks interfacing

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