DSP-based PLL-controlled 50–100 kHz 20 kW high-frequency induction heating system for surfacehardening and welding applications

N.S. Bayındır, O. K .ukrer and M. Yakup

Abstract: A digital signal processor (DSP)-based phaselocked loop (PLL)-controlled high-frequency induction heating system is described. The rectifier and insulated gate bipolar transistor(IGBT) inverter are controlled by a TMS320F240 DSP system, which has the hardware feature ofproviding a dead-band delay independent of the frequency of operation. This feature, together withthe high speed of the DSP, allows the use of zero current resonant switching at a high power factorfor frequencies up to 100kHz. Resonant operation of the inverter is maintained by a simple digitalPLL scheme implemented on the DSP. The frequency converter enables safe operation at all loadconditions with digital overcurrent, overvoltage and overtemperature protection features. The cost-effective system described is operated successfully at outputs up to 19.8kW at 72 kHz and 500V.

1 Introduction

High-frequency induction heating furnaces are widelyused in applications such as surface hardening, welding,metal to plastic or metal to glass bonding and curing.The higher efficiency, very short heating times and localheating capabilities of induction heaters have made themsuperior to other heating devices. With the latest advancesin power semiconductor switching devices and micropro-cessors, high-frequency induction heating power suppliesare now more reliable and cost-effective and have higherperformances [1–4]. In [4] a pulse amplitude modulatedvoltage source, series load resonant inverter hasbeen developed using high-power static induction transis-tors (SITs), which operates at a load-adaptive tunedoperating frequency that is slightly higher than the seriesresonant frequency in order to achieve zero-voltagesoft-switching commutation. A phaselocked loop integratedcircuit (PLL-IC) is used to provide load resonant operationbased on the phaselocked loop principle. Due to thedifference between the switching frequency and theload resonant frequency, the power factor has beendegraded by 5% and oscillations are observed at theswitching instants. Moreover with this method the delaybetween the inverter output voltage and current waveformscannot be maintained at the same level at all frequenciesdue to the change in component characteristics withfrequency. In [1], a half-bridge inverter circuit with series–parallel resonance is described which does not use animpedance matching transformer. Series and parallelcompensating capacitors are used to reduce the reactive

loading of the workpiece and also to increase the loadcurrent with respect to the inverter current. However, themethod is valid for coil inductance values less than twice thetotal series stray inductance in the circuit. Anotherdisadvantage is the use of an extra capacitor, which isexpensive at the frequencies in question. A comparison ofseries and parallel inverter systems [5] has revealed that thevoltage source series resonant inverter offers better overallperformance than the parallel resonant counterpart withrespect to converter utilisation. Considering the results ofthis comparison, the series resonant inverter topology hasbeen adopted in this project.In this paper digital signal processor (DSP)-based PLL

control scheme is presented in which the phase differencebetween the inverter voltage and current is minimised andmade independent of the operating frequency. The hard-ware dead-band feature of the DSP is used, in conjunctionwith software-based PLL control, to achieve precise zero-current switching operation so that the di/dt stresses on theinsulated gate bipolar transistors (IGBTs) are minimisedand switching occurs with negligible oscillations. The DSP-based digital control approach enables easy implementationof various monitoring and protection functions, in additionto the built-in dead-band feature. Furthermore, a digitalimplementation of the PLL scheme is more reliable than ananalogue implementation, where changing componentcharacteristics may degrade performance in time.Moreover,in analogue implementations of PLL control the dead-bandtime may vary with operating frequency, which thendegrades the power factor.The design and constructional features of the whole

system are presented in this paper. Experimental work hasbeen carried out on the induction heating system to measurethe operational performance under various loading condi-tions. Experimental results indicate that the system operatessuccessfully with a power factor very close to unity. Asimulation model has been developed using Simulink, whichhas been used to analyse and design the PLL controlsystem. A mathematical model of the system has also beendeveloped in discrete time, with which the stability of thesystem can be assessed.

N.S. Bayındır and O. K.ukrer are with the Department of Electrical andElectronic Engineering, Eastern Mediterranean University, G. Magosa, Mersin10, Turkey

M. Yakup is with the Technology Development Centre, Eastern MediterraneanUniversity, G. Magosa, Mersin 10, Turkey

r IEE, 2003

IEE Proceedings online no. 20030096

doi:10.1049/ip-epa:20030096

Paper first received 29th April 2002 and in revised form 25th September 2002

IEE Proc.-Electr. Power Appl. 1

2 System description

The general layout of the frequency converter is shown inFig. 1, where it may be seen that the output power iscontrolled by a three-phase controlled rectifier and that theinverter is of the voltage-fed load resonant type. High-speedIGBTs with fast anti-parallel diodes are used in the inverter.RC snubbers are used to reduce the dv/dt stresses on theIGBTs. A high-frequency impedance matching transformerwith a turns ratio of 5/1 has been designed and constructedwith an amorphous core on which the primary andsecondary coils are wound using Litz wire, and this is usedto isolate and match the impedances of the converter andthe induction heating coil. The induction heating coil andthe impedance matching transformer are water cooled. Ahigh-frequency compensating capacitor of value Cs¼ 1mF(500kHz, 600V) is connected in series with the coil (Ls).The inverter output voltage and the capacitor voltage aremeasured by means of high-frequency voltage transducersto provide the necessary inputs to the DSP for PLL control.The inverter and coil currents are also measured to trackthe load resonant operation and also to measure theefficiency of the converter and of the impedance matchingtransformer.

3 DSP-based PLL control system

3.1 Control system descriptionA simple DSP-based PLL control algorithm has beendeveloped in which the dead-band delay is provided by thespecial hardware feature of the TMS320F240 DSP system.The digital implementation of PLL maintains resonantoperation over a wide range of frequencies from 50 to100kHz. A block diagram of the PLL system is shown inFig. 2. The capacitor voltage vc and the inverter outputvoltage vi are measured with high-frequency voltagetransducers with negligible delay and the zero crossings ofthese voltages are detected and compared in an XOR gate,as shown in Fig 3. The output of the XOR gate is filtered toyield a DC voltage (xf) proportional to the phase differencebetween the inverter and capacitor voltages. This voltage isisolated optically and applied to the analogue input of theDSP, where digital implementation of the PLL scheme isthen realised. The flowchart of the PLL control algorithmis shown in Fig. 4. The voltage input to the DSP, which isproportional to the phase difference between the inverteroutput and the capacitor voltages, is compared with a valuecorresponding to 90 degrees and the switching frequency isadjusted so that this difference is made zero. When thiscondition is achieved, the capacitor and the inverter voltages

are in quadrature, which ensures that the inverter voltageand current are in phase.The pulse width modulated (PWM) outputs of the DSP

are used to generate switching pulses for the inverterIGBTs. The PWM periods determined by the PLLalgorithm are loaded into the timer control registerT1CON, which then starts generation of the PWM

3-phsupply

3-ph controlledrectifier

+

T1

T4 T2

T3

LF

Cs

Ls(Rl)CFVdc

-

DSP based PLLcontrol system

voltagetransducer

voltagetransducer

Fig. 1 General layout of high frequency induction heating system

DSPTMS320F240

impedancematching

transformerinverteropto-

isolator

opto-isolator

phasedetection

circuit

zero-crossingcircuits

resonant load(capacitor+inductor)

Xf

vc

vi

Fig. 2 Block diagram of PLL-based control system

XOR

Rf

Xf

Cf

Fig. 3 Phase detection circuit

initiate dead-bandroutine

start A/Dconverter

wait for end ofconversion

acquire phase error[eD(k )]

calculate new inverter periodTc(k+1) = Tc(k)+KcD.eD(k+1)

Tc(k+1) < Tmin

Tc(k+1) > Tmax Tc(k+1) = Tmax

Tc(k+1) = Tmin

update counterperiod in dead-band

yes

yes

no

no

Fig. 4 PLL control algorithm

2 IEE Proc.-Electr. Power Appl.

switching pulses. The dead-band delay between the switch-ing instants of the IGBTs on the same leg of the inverter isprovided by the dead-band control register DBTCON,which is set at 0.8ms. This delay is adjusted by the specialhardware feature of the DSP, and is independent of theprocessing delays. This feature of the DSP maintains aconstant delay at all frequencies, which is not possible inanalogue circuit implementations of PLL control due to thevariation of component characteristics with frequency(particularly in the high-frequency range). The DSPoperates at a speed of 20 MIPS, which makes it possibleto control the system up to 100 kHz.During experimentation, a lower frequency limit

of 50kHz and an upper frequency limit of 100kHzwere set on the control system so that the operatingfrequency could never exceed these limits accidentally. Theswitching signals are isolated and amplified before they areapplied to the gates of the IGBTs using a signalconditioning circuit.

3.2 Mathematical modelAn approximate discrete-time model of the system wasfound to be useful in designing the control system. Referringto Fig. 4, the PLL control is implemented in discrete-timeby the following equation:

T ðk þ 1Þ ¼ T ðkÞ þ Kceðk þ 1Þ ð1Þwhich corresponds to integral action.In (1) T is the inverter voltage period (represented by Tc

in digital form in Fig. 4), Kc is the integral gain (representedby KcD) and e is the error in phase difference (representedby eD) defined as

eðkÞ ¼ xf ðkÞ � 12

ð2Þwhere xf is the average value of the normalised LP filteroutput (Fig. 5).

Normalisation here refers to a scaling such that themaximum is unity (corresponding to 100% duty ratio of theXOR output). Note that the period of the VCO output (T)is updated instead of its frequency. This is found to be moreconvenient since the inverter control program (dead band)requires period information directly.Now, it is clear that xf can be expressed in the steady state

in terms of the phase difference f as

xf ;ss ¼fp¼ uf ð3Þ

where uf is the average value of the LP filter input.

However, in transient operation xf should be related to uf

by the differential equation

dxfdt

¼ � 1

tfxf þ 1

tfuf uf ¼ f

pð4Þ

where tf¼RfCf is the time constant of the filter.Note that in (4) uf is a function of the frequency of the

inverter voltage (or its period) through the phase differencef. Considering the steady state operation of the resonantload of the inverter, the following relationship can beobtained between f and T:

fðT Þ ¼ tan�12pT RlCs

1� ð 2po0T

Þ2

( )ð5Þ

where o0 ¼ 1=ffiffiffiffiffiffiffiffiffiLsCs

p; Ls is the inductance of the heating

coil and Rl is its equivalent resistance.It is assumed that the relationship (5) is approximately

valid during transient operation in which the period Tchanges slowly. Furthermore, (5) is obtained by assumingthat the inverter output voltage is purely sinusoidal.Equation (4) can be discretised as follows:

xf ðk þ 1Þ ¼ axf ðkÞ þ bf½T ðkÞ�

pð6Þ

where a ¼ e�Ts=tf , b¼ (1–a), and Ts is the control samplingtime. Using (1), (2) and (6) the closed-loop system equationis obtained as

T ðk þ 1Þ ¼ T ðkÞ þ Kc axf ðkÞ þ bf½T ðkÞ�

p� 1

2

� �ð7Þ

Equations (6) and (7) are non-linear, since f is a non-linearfunction of T(k). These equations can be linearised easily bylinearising (5) around the operating point, where theinverter frequency is equal to the resonant frequency ofthe load, to give (see Appendix, Section 7)

fðT Þ ’ p2� 1

pRlCsðT � T0Þ ð8Þ

where T0 is the inverter period at the operating point.With the following definitions of perturbation variables:

Dxf ¼xf � 12

DT ¼T � T0ð9Þ

the linearised closed-loop equations of the system become(see Appendix, Section 7)

yðk þ 1Þ ¼ AcyðkÞ ð10Þ

In (10) y is the column vector y¼ [Dxf DT]T and

Ac ¼a � 1�a

p2tr

� �aKc 1� ð1�aÞKc

p2tr

24

35

where tr¼RlCs.Applying Jury’s stability test [6] to (10), the following

range of gain for stability is obtained:

0oKco1þ a1� a

� 2p2RlCs ð11Þ

4 System modelling and simulation

At the design stage of the induction heating system, asimulation model of the converter and the load wasdeveloped using the SIMULINK package to estimate theturns ratio of the impedance matching transformer, the

vi vc

1

0

XOR output uf = xfss

�

Fig. 5 Waveforms for PLL operation

IEE Proc.-Electr. Power Appl. 3

compensating capacitor value and the IGBT ratings, aswell as the controller gain. The simulation model is shownin Fig. 6. The system parameters are Lsp¼ 122mH, Csp¼0.04mF, Rlp¼ 11.1O (referred to the primary sideof the impedance matching transformer), Ts¼ 200ms,and tf¼ 68ms. Note that this model does not simulatethe PLL control algorithm as in the actual practical imple-mentation, with the period T as the output of theVCO (software version). Instead, the frequency of theVCO output in this model is controlled by the VCOinput. However, the behaviours resulting from the twoapproaches are expected to be similar for sufficiently smalldeviations around the operating point. An equivalent gainof Kc¼ 5.0ms has been used in the simulations, which is thevalue that corresponds to the gain used in the experimentalsystem. Note that the theoretical limit for the gain from (11)is Kco9.8ms.

Referring to Fig. 6 the capacitor and inverter voltagesare passed through relays, which represent zero-crossingdetectors (ZCD), the outputs of which are applied tothe inputs of the XOR. The lowpass filter (LPF) outputis compared with the reference value of 0.5 and the erroris sampled by a first-order sample-and-hold, whichrepresents the analogue-to-digital conversion operation.The discrete-time integrator implements the integral con-troller. The VCO output in this simulation is the squarewave inverter output voltage, which is applied to theresonant load model. The rate limiter adjusts the rate ofchange of the inverter voltage during switches to practicalvalues.Fig. 7 shows sample simulation results for steady-state

and transient operation of the system. In the transient testcase, it is assumed that there are ramp changes in theinductance and the resistance of the coil from 90mH to

72mH, and from 10O to 8O, respectively (Section 4). Thisemulates a transient test on the actual system in which theworkpiece is pulled out by almost 20%. In Fig. 7c it can beobserved that the PLL control strategy keeps the coilcurrent in phase with the inverter voltage under alloperating conditions.

5 Experimental results

An experimental prototype of the proposed system has beenset up using a Fuji IPM inverter module (7MBP 100RA-120), with short-circuit, overcurrent, overtemperature andundervoltage protection logic. The system has beenoperated at an output power of 19.8kW, an operatingfrequency of 72kHz and an input voltage of 500V. Theinverter output voltage and current, and the capacitorvoltage are presented in Figs 8 and 9. In Fig. 8c IGBTcollector–emitter voltages have been measured at 400V,which is the maximum range of the oscilloscope. The outputvoltages of the PLL circuit (XOR and LP filter outputs)were also measured and are presented in Fig. 10. Atransient test has been performed at a lower power of

clock time

t v_inv

inv.voltage

Vi Vc

load

relay1(ZCD)

relay2(ZCD)XOR

XOR15000s+15000

0.5constant

norm. filter volt.

transf. ratio

1/5v_cap

cap. voltage

rate limiter

xf

hold0

+-

e =xf -1/2 LPF

int. gain

0.0

discrete-timeintegrator VCO+INV

in1 out1Tz-1

t

1Vi

+-- ×

×

1s

1s-K-

i_inv

inv. current 1Vc

Rint2int1

rate lim21/Cs

sum prod1prod2

rate lim1Ls

a

b

Fig. 6 SIMULINK model for PLL-controlled induction heatingsystema Complete systemb Resonant load model

-600

-400

-200

0

200

-400

-600

-800

-200

0

200

400

600

800

400

600

0.03495 0.03496 0.03497 0.03498 0.03499 0.03500

vi

ii

0.03496 0.03497 0.03498 0.03499 0.03500

vi

vc

0.450.400.350.300.250.200.150.100.050.000.300

0.350

0.400

0.450

0.500

0.550

0.600

0.650

0.700

0.50

start of transient

time, s

x fv i

, V; v

c, V

v i, V

; ic, A

c

b

a

Fig. 7 Simulation results for induction heating systema Inverter voltage (vi) and current (ii)b Inverter voltage (vi) and capacitor voltage (vc) (referred to inverterside)c Transient response of filter output (xf) for a 20% sudden reductionin the load L and R

4 IEE Proc.-Electr. Power Appl.

3.3kW with a different coil, where the workpiece wassuddenly partially pulled out of the coil (by about 20%).The transient change in the filtered output shows that thePLL control system brings the system back to unity powerfactor operation in about 50ms. It is difficult to make acomparison with the simulation result under similar

conditions, since the exact conditions in the test cannot bemodelled in the simulation. However, the response time inthe simulation is around 30ms, which roughly agrees withthe practical result. Note that in the simulation result thetransient starts at t¼ 250ms and comes to an end att¼ 280ms. Comparison of steady-state experimental and

0

0

vi ii

vi

ii

voltage: 200 V/div, current: 20 A/div, time: 2.5 µs/div

voltage: 200 V/div, current: 20 A/div, time: 1 µs/div

voltage: 200 V/div, time: 2.5 µs/div voltage: 50 V/div; time: 500 ns/div

a

b c

(i)

(ii)

0

0

vi

ii

vi

vc

0

Fig. 8 Experimental results for 19.8 kW outputa (i) Inverter voltage (vi) and current (ii). (ii) Inverter voltage and current, reduced timescale (1ms/div)b Inverter voltage (vi) and capacitor voltage (vc)c Collector–emitter voltages of IGBTs on the same inverter leg

IEE Proc.-Electr. Power Appl. 5

simulation results reveals that the system design based onthe simulation model closely follows the predicted beha-viour.Referring to Fig. 8a, (i), it can be observed that

the inverter switches at exactly zero current which ensuresunity power factor. This also means that switching lossesare minimised as a result of zero current switching. Hence,in efficiency calculations the switching losses can beneglected and an estimate of the overall efficiency of theinverter based on conduction losses only can be obtained,using

Z ¼ 1� 2VCE;satVdc

� 100% ð12Þ

as 98.9%. In (12) VCE,sat represents the saturation voltage ofthe IGBTs.Fig. 8a, (ii) displays the inverter current and voltage on

a much smaller time scale and shows that the currentand voltage waveforms are exactly in phase. It may alsobe noted that the inverter switches in 1.2ms. Furthermore,the inverter voltage exhibits no oscillations during switchingintervals. This is the result of zero-current switching andthe very small leakage inductance of the impedancematching transformer. The IGBT collector–emitter voltages(for IGBTs on the same inverter leg) on a narrow timescale are shown in Fig. 8c, where it is also clear that theIGBTs switch in about 0.8ms, which is consistent withFig. 8b. Note that the IGBTs on the same leg switchalmost simultaneously without giving rise to shoot-through,which is again a result of zero-current switching. Fig. 8bshows that the inverter and capacitor voltages arephaseshifted by 901, which demonstrates that thePLL scheme operates successfully. The effect of increasingthe dead-band duration on the inverter output voltageis illustrated in Fig. 9, where the dead-band is adjustedto 1.2ms. The oscillations in the voltage during the switchingintervals are the result of the feedback diodes trying to turnon as the load current reverses direction when the outgoingtransistors are turned off. During this transition period,the incoming transistors remain off due to the increaseddead-band. It is evident that such oscillations give rise toextra losses. Therefore, it can be concluded that the dead-band duration is very critical in zero-current switchingapplications.

6 Conclusions

A DSP-based PLL-controlled induction heating system hasbeen described in which zero-current switching of theIGBTs and operation at unity power factor with negligibleoscillations on the inverter voltage are achieved through asoftware-based PLL control scheme using a DSP which hasa hardware dead-band feature. The proposed DSP-based

vi

ii

voltage: 200 V/div, current: 20 A/div, time: 2.5 µs/div

Fig. 9 Inverter voltage and current for a dead-band time of 1.2ms

voltage: 2 V/div, time: 2.5 µs/diva

ZCDoutput

0

0

XORoutput

voltage: 100 mV/div, time: 2.5 µs/divb

voltage: 100 mV/div, time: 50 ms/divc

start of transient

Fig. 10a XOR output (lower trace)b Lowpass filter output in steady-statec Lowpass filter output for transient case

6 IEE Proc.-Electr. Power Appl.

PLL controller is more flexible and precise than conven-tional analogue PLL controllers, allowing easy modificationof control parameters (such as dead-band time andcontroller gain) via software, whereas in analogue imple-mentations, which require hardware changes, these mod-ifications would be far more difficult. The dead-band delaycan be kept constant at any predefined value, independentof the operating frequency, using the built-in dead-bandcircuitry. Experimental results reveal that the PLL controlscheme operates precisely as designed and no phase delaywas observed between the inverter output voltageand current. Transient tests on the system have shown thatafter a disturbance the PLL control system brings thesystem back to unity power factor operation within a timeof 50ms.System parameters such as the turns ratio of the

impedance matching transformer, compensating capacitorvalue and IGBT ratings, as well as controller gain wereobtained from a simulation model. Agreement betweenpredicted simulation results and experimental results havevalidated the design.The use of a DSP-based control system has the

added advantage that different control schemes requiringdifferent heating periods and different adaptations of theinduction heating system can be implemented withmodifications to the software alone and no changes to thehardware.

7 Acknowledgments

The authors wish to thank the Eastern MediterraneanUniversity Technology Development Centre (DAU-TEK-MER) for their financial support.

8 References

1 KAMLI, M., YAMAMOTO, S., and ABE, M.: ‘A 50-150kHz half-bridge inverter for induction heating applications’, IEEE Trans. Ind.Electron., 1996, 43, (1), pp. 163–172

2 WANG, S., IZAKI, K., HIROTA, I., YAMASHITA, H., OMORI,H., and NAKAOKA, M.: ‘Induction-heated cooking appliance usingnew quasi-resonant ZVS-PWM inverter with power factor correction’,IEEE Trans. Ind. Appl., 1998, 34, (4), pp. 705–712

3 CALLEJA, H., and ORDONEZ, R.: ‘Improved induction-heatinginverter with power factor correction’. 30th Annual IEEE Powerelectronics specialists Conference, PESC 99

4 OKUNO, A., KAWANO, H., SUN, J., KUROKAWA, M.,KOJINA, A., and NAKAOKA., M.: ‘Feasible development of soft-switched SIT inverter with load-adaptive frequency-tracking controlscheme for induction heating’, IEEE Trans. Ind. Appl., 1998, 34, (4), pp.713–718

5 DAWSON, F.P., and JAIN, P.: ‘A comparison of load commutatedinverter systems for induction heating and melting applications’, IEEETrans. Power Electron., 1991, 6, (3), pp. 430–441

6 KUO, B.C.: ‘Digital Control Systems’, 1st Edn. (Holt-SaundersInternational Editions, Tokyo, 1981)

9 Appendix

The phase difference f can be linearised by means of thefollowing truncated Taylor series:

fðT Þ ’ fðT0Þ þdfdT

� T¼T0

ðT � T0Þ ð13Þ

where T0¼ 2p/o0. The derivative can be evaluated from (5)as

dfdT

¼ � aðT 2 þ T 20 Þ

ðT 2 � T 20 Þ þ a2T 2

ð14Þ

where a¼ 2pRlCs. When evaluated at T¼T0, this derivativegives

dfdT

� T¼T0

¼ � 2

a¼ � 1

pRlCsð15Þ

By also noting that f(T0)¼ p/2, (8) is obtained.Substituting (8) and (9) into (6) gives:

Dxf ðk þ 1Þ þ 1

2¼a Dxf ðkÞ þ

1

2

� �

þ bp

p2� 1

pRlCsDT ðkÞ

� �

Simplification using the fact that b¼ 1�a then yields

Dxf ðk þ 1Þ ¼ aDxf ðkÞ �ð1� aÞp2RlCs

DT ðkÞ ð16Þ

Similarly, substituting (8) and (9) into (7) gives

DT ðk þ 1Þ ¼DT ðkÞ þ Kc a Dxf ðkÞ þ1

2

� ��

þð1� aÞp

p2� 1

pRlCsDT ðkÞ

� �� 1

2

�

which simplifies to

DT ðk þ 1Þ ¼ðaKcÞDxf ðkÞ

þ 1� ð1� aÞKc

p2RlCs

� �DT ðkÞ

ð17Þ

Equations (16) and (17) can then be written in matrixform as in (10).

IEE Proc.-Electr. Power Appl. 7