2166 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 3, MARCH 2016

A Single-Phase PV Quasi-Z-Source Inverter WithReduced Capacitance Using Modified Modulationand Double-Frequency Ripple Suppression Control

Yan Zhou, Member, IEEE, Hongbo Li, and Hui Li, Senior Member, IEEE

Abstract—In single-phase photovoltaic (PV) system, there isdouble-frequency power mismatch existed between the dc inputand ac output. The double-frequency ripple (DFR) energy needs tobe buffered by passive network. Otherwise, the ripple energy willflow into the input side and adversely affect the PV energy harvest.In a conventional PV system, electrolytic capacitors are usuallyused for this purpose due to their high capacitance. However, elec-trolytic capacitors are considered to be one of the most failureprone components in a PV inverter. In this paper, a capacitancereduction control strategy is proposed to buffer the DFR energy insingle-phase Z-source/quasi-Z-source inverter applications. With-out using any extra hardware components, the proposed controlstrategy can significantly reduce the capacitance requirement andachieve low input voltage DFR. Consequently, highly reliable filmcapacitors can be used. The increased switching device voltagestress and power loss due to the proposed control strategy will alsobe discussed. A 1-kW quasi-Z-source PV inverter using galliumnitride (GaN) devices is built in the lab. Experimental results areprovided to verify the effectiveness of the proposed method.

Index Terms—Capacitance reduction, double-frequency ripple(DFR), Z-source (ZS)/quasi-Z-source (qZS).

I. INTRODUCTION

THE voltage-fed z-source inverter (ZSI) and quasi-Z-sourceinverter (qZSI) have been considered for photovoltaic (PV)

application in recent years [1]–[13]. These inverters featuresingle-stage buck–boost and improved reliability due to theshoot-through capability. The ZSI and qZSI are both utilized inthree-phase and single-phase applications [1]–[5]. The single-phase ZSI/qZSI can also be connected in cascaded structurefor higher voltage application and higher performance [6]–[12].In three-phase applications, the Z-source (ZS)/quasi-Z-source(qZS) network only needs to be designed to handle the high-frequency ripples. However, in single-phase application, theZS/qZS network needs to handle not only the high-frequencyripples but also the low-frequency ripple. The qZSI will be usedin this paper to study the low-frequency ripple issue and presentthe proposed control strategy. A single-phase qZSI system is

Manuscript received February 1, 2015; revised March 25, 2015; acceptedApril 28, 2015. Date of publication May 12, 2015; date of current versionNovember 16, 2015. This work was supported by the National Science Foun-dation under Award No. ECCS-1125658. Recommended for publication byAssociate Editor D. Xu (GE Green PS)

Y. Zhou is with the Ford Motor Company, Dearborn, MI 48124 USA (e-mail:yzhou77@ford.com).

H. Li and H. Li are with the Center for Advanced Power Systems, FloridaState University, Tallahassee, FL 32310 USA (e-mail: hli12@caps.fsu.edu;hli@caps.fsu.edu).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2015.2432070

Fig. 1. Diagram of a single-phase qzsi-based PV system.

shown in Fig. 1. Ideally, the dc-side output power is pure dc andthe ac-side power contains a dc component plus ac ripple com-ponent whose frequency is two times the grid voltage frequency.The mismatched ac ripple is termed as double-frequency ripple(DFR) in this paper. In order to balance the power mismatchbetween the dc side and ac side, the DFR power needs to bebuffered by the passive components, mainly the qZS capacitorC1 which has higher voltage rating than C2 . The DFR peakpower is the same as the dc input power, so large capacitanceis needed to buffer this ripple energy. To achieve high inverterpower density with reasonable cost, electrolytic capacitors areusually selected. Electrolytic capacitors contain a complex liq-uid chemical called electrolyte to achieve high capacitance andlow series resistance. As the electrolytic capacitors age, the vol-ume of liquid present decreases due to evaporation and diffusion.This process is accelerated with higher temperature, eventuallyleading to performance degradation over time [14]. Therefore,electrolytic capacitors are considered to be the weak compo-nent regarding to lifetime, especially under outdoor operationconditions.

Accurate analytical models to calculate the DFR for qZSIhave been developed in [8], [15], and [16] and the design guide-lines for selecting the capacitance to limit the DFR are alsoprovided. Nevertheless, the required capacitance is still large.In [17], two additional smoothing-power circuits are employedto reduce the DFR of dc-link voltage in ZSI. However, the addedcircuits increase the system cost and complexity. In [18], a low-frequency harmonic elimination PWM technique is presented tominimize the DFR on Z-source capacitors. However, the method

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ZHOU et al.: SINGLE-PHASE PV QUASI-Z-SOURCE INVERTER WITH REDUCED CAPACITANCE USING MODIFIED MODULATION 2167

is used for application with constant voltage input source andDFR current is induced in the inductor and the input side. Thisis not suitable for the PV application, because the ripple currentwill decrease the energy harvest from the PV panels.

In some reported single-phase two-stage system which iscomposed of a dc–dc converter and H-bridge inverter, the dc-link capacitance can be significantly reduced by using dedicatedcontrol [14], [19]. However, the qZSI does not have the dc–dcstage, so the reported capacitance reduction methods cannot beapplied in the qZSI.

In this paper, a new control strategy is proposed for ZSI/qZSI to mitigate the input DFR without using large capacitance,which enables us to use the highly reliable film capacitors. Thereis no extra hardware needed to implement the capacitance re-duction. The proposed control system incorporates a modifiedmodulation strategy and a DFR suppression controller. In or-der to apply the capacitance reduction method, it is necessary tostudy the impact of decreasing the capacitance on system designand performance. This will be covered in Section III. A 1-kWqZSI inverter prototype with the proposed control strategy isbuilt in the laboratory. The gallium nitride (GaN) devices areapplied in the inverter to increase the system efficiency at highswitching frequency. Finally, experimental results are providedto verify the effectiveness of the proposed control system.

II. PROPOSED CONTROL SYSTEM FOR

CAPACITANCE REDUCATION

The basic principle of the proposed capacitance reductionmethod can be explained by

ΔE =12C

(v2

C max − v2C min

)(1)

where C is the capacitance, ΔE is the ripple energy that is storedin the capacitor, and vC max and vC min are the maximum andminimum voltages across the capacitor. According to (1), thereare two ways to increase ΔE. One is to increase the capacitanceC, and the other way is to increase the voltage fluctuation acrossthe capacitor. Instead of increasing the capacitance, the proposedcontrol system will increase the voltage fluctuation across theqZS capacitors to buffer more double-frequency power. A ded-icated strategy is needed to impose the DFR on qZS capacitorswhile preventing the ripple energy from flowing into the input.In order to achieve this, a modified modulation strategy and aninput DFR suppression controller are presented.

In conventional single-phase qZSI, the modulation strategyis shown in Fig. 2(a). The two phase legs of the full bridgeare modulated with 180◦ opposed reference waveforms, m andm, , to generate three-level voltage output. Two straight lines v∗

p

and v∗n are used to generate the shoot through duty ratio. When

the triangular carrier is greater than v∗p or the carrier is smaller

than v∗n , all four switches S1 − S4 turn on simultaneously for

shoot-through.In the proposed control system, the shoot-through control

lines v∗p and v∗

n are modified to a line with double-frequencycomponent as shown in Fig. 2(b). By doing so, the dc sideand the qZS capacitor DFR can be decoupled. An input DFR

Fig. 2. Modulation strategy of (a) traditional method and (b) proposed method.

suppression controller is added in the control system to generatethe double-frequency component in v∗

p and v∗n .

Fig. 3 shows the detailed control system diagram of theproposed single-phase qZSI. The proposed control containsthe maximum power point tracking (MPPT) controller, grid-connected current controller, qZS capacitor voltage controller,and input DFR suppression controller. The MPPT controllerprovides the input voltage reference v∗

IN . The error betweenv∗

IN and vIN is regulated by a PI controller and its output isthe magnitude of the grid current reference. The grid currentig is regulated by controlling the inverter modulation index mthrough a proportional resonant (PR) controller. The PR con-troller has a resonance frequency equal to the grid frequency.The qZS capacitor voltage is regulated by controlling dSH . Theshoot through lines can be generated as v∗

p = 1 − dSH and v∗n =

−1 + dSH . It is noted that vC 2 is used for the capacitor voltagecontrol. This is because vC 2 signal will be used for the qZS net-work oscillation damping. As will be explained in Section III-A,the oscillation is mainly caused by the resonance among the C2and inductors. If the inverter loss is not enough to damp the oscil-lation, dedicated active damping is needed to deal with the oscil-lation and vC 2 information is required for the implementation.

2168 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 3, MARCH 2016

Fig. 3. Diagram of the proposed control system.

Due to the limited space, the detail of the active damping is notpresented in this paper and will be covered in future paper. ThevC 2 voltage controller only regulates the average value of vC 2 ,which is Vc2 ave , due to the low-pass filter in the signal feed-back with a cutoff frequency of 25 Hz. Therefore, the capacitorvoltage controller has limited influence on double-frequencycomponent and most DFR energy can be kept in qZS capaci-tors. The reference V ∗

c2 ave is synthesized using the referencevalue of the average dc-link voltage, V ∗

dc ave , and the input volt-age average value Vin . V ∗

dc ave should be selected carefully sothat the value of dSH does not become negative because of thedouble-frequency swing, and the summation of dSH and m is al-ways smaller than 1. For different input voltages, V ∗

dc ave couldbe optimized to achieve lowest switching device voltage stress.Selection of V ∗

dc ave will be explained in more detail in Sec-tion III-B when we discuss the increased voltage stress acrossthe switching devices. A feed-forward component V ∗

c2/V ∗dc ave

is added to the output of the capacitor voltage controller toincrease the dynamic performance. The DFR suppression con-troller is composed by one resonant controller whose frequencyis designed at two times the grid frequency. The input of thecontroller is the DFR existed in vIN . It equals to the differencebetween vIN and Vin . The input DFR suppression controllerensures that the DFR in C1 and C2 does not flow into theinput.

III. IMPACT OF CAPACTICANCE REDUCTION

A. System Stability

In order to apply the proposed control system, it is necessaryto study impact of decreasing C1 on system stability. The pos-sible operation states of voltage fed qZSI have been presented

in [13], and it is summarized in the appendix with equivalentcircuits, and the averaged model of qZSI can be obtained as

⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩

L1diL1

dt=

(1 +

TAB + T0B

TS − TAB − T0B

)(vC 1 + vC 2) dSH

+TSBU

TS − TAB − T0B(vC 1 + vC 2) − vC 1 + vIN

L2diL2

dt=

(1 +

TAB + T0B

TS − TAB − T0B

)(vC 1 + vC 2) dSH

+TSBU

TS − TAB − T0B(vC 1 + vC 2) − vC 2

C1dvC 1

dt= iL1 − (iL1 + iL2) dSH − TSBU

TS(iL1 + iL2)

−(

TAC

TS+

TAB

TS

)iDC

C2dvC 2

dt= iL2 − (iL1 + iL2) dSH

− TSBU

TS(iL1 + iL2) −

(TAC

TS+

TAB

TS

)iDC

(2)where Ts is the switching period, TAB , T0B , TSBU , TAC , andTSBI are time intervals of different operation states, as listed inthe appendix, m is the modulation signal and dSH = TSBI /Ts .The small signal model can be derived accordingly as

⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨

⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩

L1diL1

dt=

(1 +

TAB + T0B

TS − TAB − T0B

)(Vc1 + Vc2) dSH

+TSBU + TAB + T0B

TS − TAB − T0B(vC 1 + vC 2)

− (1 − Dsh)vC 1 + Dsh vC 2 + vIN

L2diL2

dt=

(1 +

TAB + T0B

TS − TAB − T0B

)(Vc1 + Vc2) dSH

+TSBU + TAB + T0B

TS − TAB − T0B(vC 1 + vC 2)

−(1 − Dsh)vC 2 + Dsh vC 1

C1dvC 1

dt=

(1 − Dsh − TSBU

TS

)iL1 −

(Dsh +

TSBU

TS

)iL2

+ (Il1 + Il2) dSH −(

TAB

TS+

TAC

TS

)iDC

C2dvC 2

dt =(1 − Dsh − TS B U

TS

)iL2 −

(Dsh +

TSBU

TS

)iL1

+ (Il1 + Il2) dSH −(

TAB

TS+

TAC

TS

)iDC .

(3)The variables with “�” in (3) denote the small signal per-

turbations. Vc1 , Vc2 , Il1 , Il2 , and Dsh are the steady-state ca-pacitor voltage, inductor current, and shoot-through duty cycle,respectively.

The transfer function from shoot-through duty cycle of dSHto capacitor voltage vC 2 , denoted as GvC 2

dS H, can be derived as

GvC 2dS H

=b3s

3 + b2s2 + b1s + b0

a4s4 + a3s3 + a2s2 + a1s + a0(4)

ZHOU et al.: SINGLE-PHASE PV QUASI-Z-SOURCE INVERTER WITH REDUCED CAPACITANCE USING MODIFIED MODULATION 2169

Fig. 4. Root loci of the system with C1 parameter sweeping.

where

a0 = (1 − 2Dsh)2 − 2 (λ1 + λ3) (1 − 2Dsh) + 4λ1λ3 ,

a1 = 0,a2 =(L1 + L2) (C1 + C2) (λ1 + Dsh) (λ3 + Dsh) ,

+ (L1C1 + L2C2) (1 − 2Dsh − λ1 − λ3) ,

a3 = 0, a4 = L1L2C1C2 ,

b0 = (Vc1 + Vc2) (1 + λ2) (1 − 2Dsh − 2λ3) ,

b1 = (IL1 + IL2) [L2 (Dsh + λ1 − 1) − L1 (Dsh + λ1)] ,

b2 = C1 (Vc1 + Vc2)[

L1 (1 + λ2)

− (L1 + L2) (Dsh + Dshλ2 + λ3 + λ2λ3)

]

,

b3 = −L1L2C1 (Il1 + Il2) ,

λ1 =TSBU + Dsh (TAB + T0B )

TS − TAB − T0B,

λ2 =TAB + T0B

TS − TAB − T0B, λ3 =

TSBU

TS

The root loci of transfer function GvC 2dS H

are drawn in Fig. 4 bysweeping the value of C1 capacitance to analyze the dynamiccharacteristics of the qZSI. When drawing the root loci, otherparameters are fixed as C2 = 20 μF, L1 = 330 μH, L2 = 215μH, Lg = 600 μH, vin = 140 V, and Dsh = 0.08. The right-half-hand plane (RHP) zero indicates the qZS network is anonminimum phase system. This RHP zero will limit the sys-tem dynamic response. However, the decrease of C1 will notsignificantly change the position of the RHP zero. There aretwo pairs of conjugated poles located on the imaginary axis,which indicate possible resonances at two different frequen-cies. The lower frequency resonance is more related to C1 andthe higher frequency resonance is mainly determined by C2 .Therefore, it is seen that the higher resonant frequency doesnot change much with the C1 change. The lower resonant fre-quency increases when C1 decreases. Because there is alwaysa zero close to the lower frequency pole, the lower frequency

resonance is largely damped. Decreasing C1 does not affect thesystem stability much.

B. Increased Device Voltage Stress and Power Loss

When the proposed method is applied, the double-frequencyvoltage ripple across vC 1 and vC 2 will be increased intentionally.The dc-link voltage across the H-bridge vDC will also includeDFR which could increase the voltage stress of switching de-vices. Because vC 1 is much higher than vC 2 , most double-frequency energy is stored in C1 . The value of vC 1 can becalculated using the following equation:

12C1v

2C 1 =

12C1V

2c1 ave +

∫ t

0(Pin − pAC)dt (5)

where Vc1 ave is the average value of vC 1 , Pin is the inputpower, and pAC is the instantaneous ac output power. pAC canbe calculated as

pAC = Vg p sin (ωt) × Ig p sin (ωt)

=12Vg pIg p [1 − cos (2ωt)] = Pin [1 − cos (2ωt)] (6)

where Vg p and Ig p are the peak value of vg and ig . Therefore,we can get

vC 1 = Vc1 ave + Δvc1 dfr =√

V 2c1 ave +

Pin

ωC1sin (2ωt)

=

√(Vdc ave + Vin

2

)2

+Pin

ωC1sin (2ωt) (7)

where Δvc1 dfr is the DFR component of vC 1 . In (7), the valueof Vin and Pin are determined by the PV array operating point.Vdc ave is indirectly controlled by regulating Vc2 ave as shownin Fig. 3. Therefore, when V ∗

dc ave is selected and the PV arrayoperating point is determined, vC1 can be calculated. It is seenthat larger Δvc1 dfr can reduce the size of C1 . vDC duringnonshoot period can be obtained as

vDC = 2vC 1 − Vin

= 2

√(Vdc ave + Vin

2

)2

+Pin

ωC1sin (2ωt) − Vin . (8)

It is seen from (8), when C1 and Pin are fixed, the switchingdevice voltage stress is mainly determined by Vdc ave and Vin .There is an optimized value of V ∗

dc ave for different input voltageconditions to minimize the switching device voltage stress. Inorder to get the optimized value of V ∗

dc ave , dSH and m need tobe first calculated as

dSH = Dsh ave + Δdsh dfr =vC 1 − Vin

2vC 1 − Vin

=

√(Vd c av e +V in

2

)2+ P in

ωC1sin (2ωt) − Vin

2√(

Vd c av e +V in2

)2+ P in

ωC1sin (2ωt) − Vin

(9)

2170 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 3, MARCH 2016

TABLE IPARAMETERS OF THE QZSI UNDER STUDY

qZSI Component Parameters

Input voltage v IN 140–180 VGrid voltage vg 120 VrmsC1 2 mF for conventional system 200 μF for proposed systemC2 20 μFL1 330 μHL2 215 μHLg 600 μHSwitching frequency 100 kHz

where Dsh ave and Δdsh dfr are the average value and double-frequency component of dSH , respectively

m =Vg p sin(ωt)

vDC. (10)

In order to take advantage of the buck–boost feature of theqZSI, the input voltage range is usually selected that Vg p isamong the input voltage range. For the proposed method, themaximum switching device voltage stress could happen at max-imum or minimum Vin . When Vin is larger than Vg p , no shoot-through is needed in conventional design and dSH equal to zero.However, for the proposed method, certain value of Dsh ave isneeded to make sure dSH does not become negative values be-cause of the double-frequency swing. Higher Vin leads to higherpeak value of vDC . Therefore, one of the worst cases for the in-creased device voltage stress could happen at maximum Vin . Inthis case, according to (9), V ∗

dc ave can be optimized that Dsh aveis equal to the peak value of Δdsh dfr , so the increased voltagestress can be minimized. On the other hand, when Vin is smallerthan Vg p and it is at lowest value, large Dsh ave is needed toguarantee that vDC is always larger than vg . Therefore, it couldbe another worst case for the increased device voltage stress. Inthis case, V ∗

dc ave can be properly selected that the peak valueof dSH+m is equal to 1, so the increased voltage stress can beminimized. For input voltages between the minimum and max-imum, V ∗

dc ave can be selected either when Dsh ave is equal tothe peak value of Δdsh dfr or the peak value of dSH+m is equalto 1. Numeric example will be provided in the prototype designin next section.

For the proposed method, there is a design tradeoff betweenthe demand of decreasing C1 and the increased voltage stressacross the switching devices. This should be considered in thesystem design. Due to the increased voltage stress and DFRflowing in the qZS network, it is also expected that there is extrapower loss compared with the conventional design. This will bedemonstrated in the experimental study.

IV. PROTOTYPE DESIGN AND EXPERIMENTAL RESULTS

A 1-kW qZSI prototype was built in the lab. The parameters ofthe qZSI are provided in Table I. In the qZSI, the voltage acrossC1 is higher than the voltage across C2 , so C1 is designed tohandle the DFR. The quasi-Z-source network design can refer tothe model developed in [8]. For the conventional design, in orderto achieve 5% voltage ripple at the input side, 2 mF capacitor isneeded for C1 . By utilizing the proposed control strategy, C1 can

Fig. 5. V ∗dc ave and switching device voltage stress at different input voltages.

Fig. 6. Prototype of the 1-kW qZSI with minimized capacitance.

be reduced to 200 μF considering the design tradeoff discussedin Section III-B. C2 is designed to limit the high-frequencyvoltage ripple to 1% of the maximum voltage across C2 . The L1and L2 are designed to limit the high-frequency ripple to 20%of the maximum current through L1 and L2 , respectively.

In conventional design, the maximum switching device volt-age stress equals to 200 V when Vin = 140 V. For the proposedmethod, V ∗

dc and the switching device voltage stress at differentinput voltages can be calculated based on the analysis in SectionIII-B. They are provided in Fig. 5. It is seen that the maximumvoltage stress across the switching devices happens at Vin = 180V in this design. V ∗

dc ave is selected at 248 V, so that Dsh aveis equal to the peak value of Δdsh dfr . The peak value of vDC ,also the switching device voltage stress, is increased to 306 V.Therefore, the switching device voltage stress is increased by53% compared with the conventional design. If the grid voltageis increased to 240 Vrms, the inverter power rating is kept thesame and the input voltage is 260–340 V, and C1 is decreasedfrom 800 μF required in conventional design to 100 μF withthe proposed control, the switching device voltage stress is in-creased by only 15%. Therefore, there is more benefit to applythe proposed method in qZSI with higher output voltage.

The picture of the 1-kW qZSI prototype with minimized ca-pacitance is shown in Fig. 6. TPH3006PS GaN devices fromTransphorm are selected as the inverter switches and the switch-ing frequency is selected at 100 kHz. In the experimental study,the Magna Power Electronics XRii 250–16 was used as the

ZHOU et al.: SINGLE-PHASE PV QUASI-Z-SOURCE INVERTER WITH REDUCED CAPACITANCE USING MODIFIED MODULATION 2171

Fig. 7. vDC , vIN , and vC 2 waveforms of the qZSI with the conventionalcontrol, C1 = 2 mF.

Fig. 8. vDC , vIN , and vC 2 waveforms of the qZSI with the conventionalcontrol, C1 = 200 μF.

PV emulator. The waveforms of vDC , vC 2 , and vIN for theqZSI system with 2 mF capacitor are shown in Fig. 7. The in-put voltage was 150 V and the output voltage was 120 Vrms.The inverter was operated at 300 W output power condition.The double-frequency components in vDC , vC 2 , and vIN were0.72, 0.336, and 0.774 V. The 120-Hz ripple in vIN was limitedbecause of the large capacitance. The waveforms for the qZSIwith 200 μF capacitor, but without the proposed control, areprovided in Fig. 8. Because the C1 was significantly reduced,the 120-Hz ripples in vDC , vC 2 , and vIN increased to 7.18, 2.39,and 5.302 V, respectively. The distribution of the 120-Hz ripplelargely depends on the impedance network. The conventionalcontrol has minor influence on the ripple distribution. The large120-Hz ripple in vIN could influence the PV energy harvesting.The waveforms of the system with the proposed control strategyare shown in Fig. 9. The 120-Hz ripples in vDC , vC 2 and vINwere increased to 9.186, 8.75 and 0.45 V, respectively. As ex-pected, most 120-Hz ripple energy was imposed on C1 and C2 .The corresponding output current waveform is shown in Fig. 10and its total harmonic distortion value is 4.4%.

The efficiency comparison of the conventional qZSI and theqZSI with proposed control at different power outputs is pro-vided in Table II. As expected in the discussion in Section III-B,

Fig. 9. vDC , vIN , and vC 2 waveforms of the qZSI with the proposed control,C1 = 200 μF.

Fig. 10. Output current waveform of the qZSI with the proposed control,C1 = 200 μF.

TABLE IIEFFICIENCY COMPARISON OF THE CONVENTIONAL QZSI AND QZSI WITH THE

PROPOSED CONTROL

300 W 400 W 500 W 600 W

C1 = 2 mF with conventional control 93.05% 93.18% 93.66% 93.76%C1 = 200 μF with proposed control 92.36% 93.06% 93.48% 93.55%

because of the increased voltage stress and 120-Hz ripple flow-ing in the qZS network, the efficiencies of the proposed systemwere around 0.12%–0.69% lower than the conventional system.The C1 capacitance was reduced by ten times, but with theexpense of efficiency decrease. Although the efficiency dropwas not significant, it should be considered in the design stageif higher efficiency is desired.

V. CONCLUSION

In this paper, a new control strategy is proposed to minimizethe capacitance requirement in single-phase qZSI PV system.

2172 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 3, MARCH 2016

Instead of using large capacitance, the qZS capacitors are im-posed with higher double-frequency voltages to store the DFRenergy. In order to prevent the ripple energy flowing into the in-put PV side, a modified modulation and an input DFR suppres-sion controller are used to decouple the input voltage ripple fromthe qZS capacitor DFR. The small signal model is developedand shows that the capacitance reduction does not impact thesystem stability much. For the developed 1-kW quasi-Z-sourcePV system, 2 mF capacitor can be replaced with a 200 μF

capacitor by using the proposed method. However, the volt-age stress across the switching devices was increased by 53%compared with the conventional design. The efficiency was de-creased by 0.12%-0.69% at several selected operation points. Itis also shown that there is more benefit if the method is appliedfor 240 Vrms output qZSI. The increase of the switching devicevoltage stress is only 15% compared with conventional design.This control strategy can also be applied in single-phase ZSIapplications.

APPENDIX

OPERATION STATES, EQUIVALENT CIRCUITS, AND DYNAMIC STATE EQUATIONS OF QZSI

ZHOU et al.: SINGLE-PHASE PV QUASI-Z-SOURCE INVERTER WITH REDUCED CAPACITANCE USING MODIFIED MODULATION 2173

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Yan Zhou (S’10–M’14) received the B.S. and M.S.degrees in electrical engineering from the HuazhongUniversity of Science and Technology, Wuhan,China, in 2007 and 2009, respectively. He receivedthe Ph.D. degree in electrical engineering from theFlorida State University, Tallahassee, FL, USA, in2013.

He is currently working as an inverter design En-gineer at Ford Motor Company, Dearborn, MI, USA.His research interests include grid-connected PV sys-tem control, PV micro-inverter, GaN FETs applica-

tion, high PV penetration integration issues, and hybrid/electric vehicle tractioninverter.

Hongbo Li was born in Henan Province, China.He received the M.E. and Ph.D. degrees from theHuazhong University of Science and Technology,Wuhan, China, in 2008, and 2012, respectively.

He worked in Nanjing Electronic Institute from2012 to 2013. In 2014, he was a Postdoctoral Fellowin the Center for Advanced Power Systems, FloridaState University, Tallahassee, FL, USA. His researchinterests include railway traction drives, active powerfilters, and power electronics for applications in re-newable energy.

Hui Li (S’97–M’00–SM’01) received the B.S. andM.S. degrees in electrical engineering from theHuazhong University of Science and Technology,Wuhan, China, in 1992 and 1995, respectively, andreceived the Ph.D. degree in electrical engineeringfrom the University of Tennessee, Knoxville, TN,USA, in 2000.

She is currently a Professor in the Electrical andComputer Engineering Department, Florida A&MUniversity—Florida State University College of En-gineering, Tallahassee, FL, USA. Her research inter-

ests include PV converters applying WBG device, bidirectional dc–dc convert-ers, cascaded multilevel inverters, and modular multilevel converters.