DRM151, 3-phase Sensorless BLDC Motor Control...

3-phase Sensorless BLDC Motor Control Reference Design

Using Kinetis KEA128

Document Number: DRM151Rev. 0

06/2014

3-phase Sensorless BLDC Motor Control Reference Design Using Kinetis KEA128, Rev. 0

2 Freescale Semiconductor

Chapter 1 Introduction

1.1 System concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Chapter 2 Sensorless BLDC Control

2.1 Overview of the brushless DC motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72.1.1 Electronic commutation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82.1.2 Speed/torque control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

2.2 Complementary unipolar PWM modulation technique . . . . . . . . . . . . . . . . . . . . . . . . . .102.3 Position estimation based on BEMF zero-crossing detection . . . . . . . . . . . . . . . . . . . . .11

2.3.1 BEMF zero-crossing principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122.3.2 BEMF zero-crossing event detection and phase current measurement . . . . . . .132.3.3 BEMF voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152.3.4 DC bus current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.4 States of the sensorless BLDC control based on BEMF zero-crossing detection . . . . . .182.4.1 Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182.4.2 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182.4.3 Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Chapter 3 Software implementation

3.1 Application specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213.1.1 Module interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213.1.2 Module involvement in the sensorless BLDC software control loop . . . . . . . . . .223.1.3 FlexTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233.1.4 Periodic Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253.1.5 System Integration Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253.1.6 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263.1.7 Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

3.2 Software architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273.2.1 Application flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293.2.2 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303.2.3 Application timing and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323.2.4 Zero-crossing detection processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323.2.5 Speed evaluation and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353.2.6 Motor current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363.2.7 Automotive Math and Motor Control Library . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

3-phase Sensorless BLDC Motor Control Reference Design Using Kinetis KEA128, Rev. 0 Draft A

Freescale Semiconductor 3

Chapter 4 Application Control

4.1 FreeMASTER tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394.2 FreeMASTER graphical user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.2.1 Project tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404.2.2 Variable watch grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

4.3 Motor Control Application Tuning Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404.3.1 Introduction tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424.3.2 Parameters tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424.3.3 Control loop tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444.3.4 Sensorless tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .464.3.5 Output file tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474.3.6 Application control tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Chapter 5 Hardware Specification

5.1 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .515.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

5.2.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525.2.2 System basis chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525.2.3 Local Interconnect Network (LIN) and Controller Area Network (CAN) . . . . . . .535.2.4 OpenSDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535.2.5 3-phase power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545.2.6 Analog signal conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555.2.7 Brake chopper circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Chapter 6 Acronyms and Definitions

Chapter 7 References

Appendix A Reference Design Board Schematics

Appendix B Bill of Materials

3-phase Sensorless BLDC Motor Control Reference Design Using Kinetis KEA128, Rev. 0 Draft A


Chapter 1 IntroductionThis reference manual describes the design of a 3-phase brushless DC (BLDC) motor control drive using a sensorless algorithm. The design is targeted at automotive applications, such as:

• Heating, ventilation, and air conditioning (HVAC)• Electric pumps, motor control, and auxiliaries• Transmission and gearbox• Doors, window lift, and seat control

The design exhibits the suitability and advantages of the Kinetis KEA128 microcontroller for BLDC motor control. It serves as an example of a BLDC motor control design using the general-purpose Kinetis EA series of microcontrollers.

The overall solution is based on the Kinetis KEA128 ARM® Cortex®-M0+ automotive-grade microcontroller, MC33937A FET pre-driver, and MC33903D system basis chip. This Freescale integrated circuit eco-system represents a BLDC motor control solution for the 12 V automotive systems.

1.1 System conceptThe system is designed to drive a 3-phase BLDC motor. The application meets the following system concept:

• Targets the Kinetis KEA128 ARM® Cortex®-M0+ automotive microcontroller• Utilizes the MC33937A FET pre-driver• Utilizes the MC33903D system basis chip as an MCU voltage regulator and CAN and LIN

communication physical interface• Incorporates a control technique with:

— Six-step commutation control of a 3-phase BLDC motor— Position sensing by means of the BEMF (Back Electromotive Force) voltage zero-crossing

detection technique— Closed-loop speed control— Motor current limitation— Alignment and start-up

• Automotive Math and Motor Control Library Set for ARM® Cortex®-M0+ as a set of building blocks for a control algorithm implementation

• FreeMASTER run-time debugging tool as a graphical control interface (motor start/stop, speed set-up)

• Motor Control Application Tuning (MCAT) tool for application parameter tuning in run-time



Introduction



Sensorless BLDC Control

Chapter 2 Sensorless BLDC Control

2.1 Overview of the brushless DC motorThe BLDC motor is a rotating electric machine with a classic 3-phase stator similar to an induction motor. The phases mounted on the stator are connected to form a star or delta connection. The rotor has surface-mounted permanent magnets. The motor can have more than one pole pair per phase. The number of pole pairs per phase defines the ratio between the electrical revolution and the mechanical revolution.

Figure 2-1. BLDC motor – cross-section

The BLDC motor is equivalent to an inverted DC brushed motor, where the magnet rotates while the conductors remain stationary. In the DC brushed motor, the commutator and brushes reverse the current polarity in such a way that stator and rotor magnetic fields are perpendicular. However, in the brushless DC motor, a power transistor (which must be switched in synchronization with the rotor position) performs the polarity reversal. This process is also known as electronic commutation.

The arrangement of the magnets on the rotor creates a trapezoidal back electromotive force (BEMF) shape when the rotor is spinning. Neglecting the higher-order harmonic terms, the BEMF in the motor phase (ea,eb,ec) is as indicated in Figure 2-2. Each BEMF has a constant amplitude for 120 electrical degrees, followed by a 60 electrical degree transition in each half-cycle.

The ideal current waveforms in each phase (ia,ib,ic) need to be quasi-square waveforms of 120 electrical degrees of conduction angle in each half-cycle. The conduction of current in each phase must coincide with the flat part of the BEMF waveforms; this guarantees that the developed torque is constant or ripple-free at all times. In order to align current conduction in each phase with the flat part of the BEMF, the rotor position must be known.

C A B

Permanent Magnets

Stator

Stator Winding

Shaft

Rotor

Air Gap

Center point




Figure 2-2. 3-phase BEMF voltages and phase currents of a BLDC motor

The position of the rotor can be obtained by a position sensor or a sensorless algorithm. Various kinds of position sensors are used. However, since the rotor is a permanent magnet, it is a very simple matter to determine where the physical pole edges are using a simple, reliable, and inexpensive Hall effect sensor.

The following techniques are commonly used to estimate rotor position in applications that rely on sensorless control of a BLDC motor:

• BEMF zero-crossing detection method• Flux level detection method• Various kinds of system state observers• Signal injection methods

From a control perspective, two logical mechanisms must be employed:• Commutation control, where the phases are energized according to rotor position with the

quasi-square current waveforms.• Speed/torque control, where the amplitude of the quasi-square current waveform applied to the

phases is controlled to achieve the desired speed/torque performance.

The following sections discuss the concept of the BEMF zero-crossing detection method, as well as the methods and conditions for its correct evaluation.

2.1.1 Electronic commutation control

The commutation process provides a mechanism to energize phases according to the rotor position with the quasi-square current waveforms. Since only six discreet outputs per electrical cycle are required (as shown in Figure 2-2), six semiconductor power switches are sufficient to create quasi-square current waveforms for the phases. Six semiconductor power switches form a 3-phase power inverter, designed using IGBT or MOSFET switches. The power for the system is provided by the DC bus voltage UDCB. The semiconductor switches and diodes are modeled as ideal devices in Figure 2-3.

ea

Phase A

Phase B

Phase C

30° 60° 90° 120° 150° 180° 210° 240° 270° 300° 330° ϕ360°

eb

ec

ia

ic

ib

SAT SAT SAT SAT

SBT SBT SBT SBT

SCB SCB SCB SCB

SCT SCT SCT SCT

SAB SAB SAB SAB

SBB SBB SBB SBB

0°




Figure 2-3. power stage and motor topology

Six-step commutation is a very common method for driving a 3-phase star-connected BLDC motor. In six-step commutation control, the BLDC motor is operated in a two-phase model. Two phases are energized while the third phase is disconnected as the space between the magnet poles passes over it and produces a zero BEMF voltage. Selection of the two energized phases is carried out by a position sensor or a position observer. Table 2-1 shows the output current waveforms for a 3-phase inverter and the switching devices that conduct during the six switching intervals per cycle.

Table 2-1. Six-step switching sequence

Rotor position

Sector number

Switch closed

Phase current

Phase A Phase B Phase C

0°-60° 0 SAT SBB + – Off

60°-120° 1 SAT SCB + Off –

120°-180° 2 SBT SCB Off + –

180°-240° 3 SBT SAB – + Off

240°-300° 4 SCT SAB – Off +

300°-360° 5 SCT SBB Off – +

DCB

shunt

AT BT CT

AB BB CB

DCB

R

L

B

C

L

L

RR

iB

iC

iA

I

A




2.1.2 Speed/torque control

Commutation ensures the proper direction of the phase current according to the rotor position of the BLDC motor, while the motor torque/speed only depends on the amplitude of the quasi-square current waveform. Continued control of the amplitude of the quasi-square current waveform for each phase of the motor is ensured by hysteresis or PWM control.

PWM control is commonly used in applications where microcontrollers are employed. The duty cycle for the PWM modulator is obtained by the speed PI controller. The speed PI controller amplifies the error between the required and actual speeds, and its output, appropriately scaled, is assigned to the PWM modulator.

The actual mechanical speed can be calculated as a time derivative of the shaft position ϕmech.

Eqn. 2-1

Since the shaft travels exactly 1/6 of one electrical revolution (2π in radians) between two commutations, the above equation can be rewritten to the following form:

Eqn. 2-2

Where:• p is the number of pole pairs• TCM is the time between two consecutive commutations• TCM

n is the time between commutations in sector n = 0, 1, 2, 3, 4, 5• ϕel is the electrical position

2.2 Complementary unipolar PWM modulation techniqueThere are different methodologies for powering and switching the phases. The unipolar PWM control technique combines commutation control and torque control. While the state of the switches is determined by commutation control, the torque is controlled by the applied duty cycle. An application with BLDC control where the unipolar PWM control technique is employed, benefits from a reduction in the MOSFET switching losses and an improvement in the system’s EMC robustness.

The unipolar PWM control means that the motor phase sees only the positive polarity of the voltage. To achieve the unipolar PWM pattern, one phase is in complementary PWM mode while the second phase is grounded and the third phase stays unpowered, as shown in Figure 2-4. This PWM pattern can be seen every 60 electrical degrees, and they differ only in phase order. The phase order is determined according to the shaft position by commutation control.

ωmechdϕmech

dt------------------ 1

p---

dϕeldt

---------- 1p---

ϕelΔTΔ

-----------≈= =

ωmech1p---

dϕeldt

---------- 1p---

360°6

-----------

TCM------------= =

1p--- 360°

T 0° 60°→( ) T 60° 120°→( ) T 120° 180°→( ) T 180° 240°→( ) T 240° 300°→( ) T 300° 360°→( )+ + + + +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 360°

p TCMn

n 0=

5

∑---------------------------==




Figure 2-4. Complementary unipolar PWM switching

For example, in the first cycle, Phase A is powered by the complementary PWM signal while the bottom transistor of Phase B is grounded and Phase C is unpowered. After the commutation event at 90° electrical degrees, Phase A is still powered by the complementary PWM signal, Phase B is unpowered, and Phase C becomes grounded instead.

The control described in this document is based on the complementary/independent unipolar PWM modulation technique.

The following section explains sensorless position estimation by means of BEMF zero-crossing detection for commutation control purposes.

2.3 Position estimation based on BEMF zero-crossing detectionFigure 2-2 shows ideal BEMF waveforms (ea, eb, ec) and depicts a commutation event occurring at a position of 30 electrical degrees after the point where a BEMF zero-crossing arises. The BEMF zero-crossing happens at a position of 30 electrical degrees after the point of the last commutation event. Let us assume that the motor is spinning at a constant velocity; in this case, the motor needs the same amount of time to travel from the position of the last commutation event to a BEMF zero-crossing and from the BEMF zero-crossing to the following commutation event. In the time domain, a BEMF zero-crossing is right in the middle of two commutation events. Therefore, the BEMF zero-crossing event, with help of a timer, can simply be used to estimate the right commutation point as well as the velocity of the rotor.

C-off

C-off

B-off

B-off

A-off

A-off

B-off

B-off

C-off

C-off

A-off

A-off

0° 60° 120° 180° 240° 300° 360°

SAB

SBT

SBB

SCT

SCB

Commutation

ϕ

Events

SAT




2.3.1 BEMF zero-crossing principle

To explain and simulate the idea of BEMF sensing techniques, this document provides a simplified mathematical model based on the basic circuit topology (see Figure 2-5). The goal of the mathematical model is to identify dependencies between the measurable motor waveforms and a BEMF zero-crossing. The BEMF zero-crossing, in turn, helps to identify the commutation event.

Figure 2-5. Basic BLDC motor circuit topology

The mathematical model is based on the fact that only two phases of a motor are energized and the third is disconnected. The natural voltage level of the whole model is referenced to half of the DC bus voltage, which simplifies the mathematical expressions. The mathematical model assumes that the motor phases are symmetrical (see Figure 2-5).

Eqn. 2-3

For a symmetrical 3-phase motor, the sum of all BEMF voltages is zero, therefore:

Eqn. 2-4

The unpowered phase has the following voltage equation, since there is no current flowing:

Eqn. 2-5

By substituting Equation 2-3 with Equation 2-4 and Equation 2-5, the phase voltage on the unpowered phase can be derived as:

Eqn. 2-6

DCB

R

L

B

iB

iC

C

L

L

RR

iA

A

uN UDCB Rib– Ldibdt-------– eb–=

un Ria= Ldiadt------- ea–+

⎭⎪⎪⎬⎪⎪⎫

ia, ib uN⇒UN2

-------eb ea+

2----------------–= =

ec eb ea+ + 0 ec→ eb ea–( )–= =

uN uC ec–=

ucuDCB

2------------- 3

2---ec+=




At the time of the BEMF zero-crossing, the BEMF voltage (ec in this case) is zero as the name implies. Therefore, by measuring voltage at the unpowered phase (ec) and comparing it to half of the DC bus voltage, the BEMF zero-crossing can be accurately identified.

2.3.2 BEMF zero-crossing event detection and phase current measurement

Figure 2-6. BEMF zero-crossing and commutation events, and their relationship to complementary unipolar PWM switching

The exact position of the rotor can be sensed by measuring the BEMF voltage induced by the rotating permanent magnet in the unpowered phase.

In Figure 2-6, the blue windows mark the time periods in which the respective phase is unpowered. The voltage measured in this time window is the BEMF voltage. At the BEMF zero-crossing event, the permanent magnet is right in front of a coil and the rotor field is positioned 90° versus the stator field. This event happens in the middle of a commutation period and is marked as the black circles in the blue BEMF window. At this time, the phase voltage is equal to half of the DC bus voltage, as described in Section 2.3.1, "BEMF zero-crossing principle". In the case of a constant shaft velocity, the period between two following zero-crossing events is equal to the commutation period.

Figure 2-7 zooms in closer to one of the PWM cycles. At the top of the figure is the PWM pattern, where Phase A is controlled by PWM and Phase C is grounded for the entire PWM period. During the PWM On cycle, the top switch of Phase A is turned on and the bottom switch of Phase C is grounded. Current flows from the DC bus into Phase A, and back through Phase C and the DC bus shunt resistor. In this cycle, the center point of the motor shows a voltage level of UDCB/2. The BEMF voltage in the unpowered phase

Commutations

Commutationperiod

Zero-crossingperiod

Zero-crossingevents

Pha

se

voltage

time

BEMF evaluationwindow




changes relatively to UDCB/2 in the positive and negative directions, which means that the zero-crossing is detectable when the phase voltage on the unpowered phase is equal to UDCB/2. Also, the phase current is measurable on the DC bus shunt.

During the Off cycle of the PWM period, both the Phase A and Phase C bottom switches are on. Therefore, phase current circulates through Phase A, Phase C, and the two bottom switches back. During this cycle, the phase current is unable to reach the DC bus shunt resistor and the phase current cannot be measured. The center point of the motor as well is connected to ground, and the zero-crossing cannot precisely be measured in that cycle.

Figure 2-7. BEMF zero-crossing detection with complementary unipolar PWM switching

Following on from the discussion above, phase current and BEMF voltage measurements must be performed in the active phase of the PWM cycle.

SAB

SBT

SBB

SCT

SCB

SAT

Phase A

Phase B

Phase C

C-off

C-off

B-off

B-off

SAB

SCT

SCB

SAT

Phase A

Phase C

On

Off

Off

On

Off

On

SAB

SBT

SBB

SCT

SCB

SAT

SAB

SBT

SBB

SCT

SCB

VDCB

VDCB GND

GND

VDCB

GND GND

GND

VB

EM

F

GND

VB

EM

FB

C

A

B

C

A

SAT




2.3.3 BEMF voltage measurement

As we learned earlier, the BEMF voltage can only be measured during the active phase of the PWM. Importantly, this is measured towards the end of the active cycle due to switching noises. In Figure 2-8, the green marked area shows the window in which the BEMF should be measured.

Figure 2-8. BEMF voltage measurement

It should be noted that, depending on the motor and power stage parameters, the amplitude, period, and damping of the voltage ringing vary. As a result, it is recommended that the BEMF voltage is measured close to the end of the window. The time of this sample point also needs to be stored, as it is used to enhance zero-crossing detection.

Figure 2-9. Precise BEMF zero-crossing identification

SAB

SCT

SCB

Phase A

Phase C

On

Off

Off

On

Off

On

SAT

Motor

Switching

BEMFMeasurement

Window

Noise

PhaseResonance

UDCB

eT-1

TADC

TPWM

TZC

eT

/ 2




If we zoom out again and look at the BEMF voltage cycles (see Figure 2-9), it can be seen that the crossing of the BEMF voltage and level can take place wherever between two following BEMF voltage measurements. For accurate position estimation, an exact zero-crossing point has to be identified. This exact zero-crossing point identification is done by an approximation based on the interpolation of two following BEMF measurements.

Assuming that the shaft is not accelerating, actual BEMF voltage was measured at time TADC with the voltage level of eT, and the previous measurement was taken at the time of TADC – TPWM with the voltage level of eT–1, then the equation to calculate the exact time of the zero-crossing event could be derived as follows:

Eqn. 2-7

This formula is calculated in the commutation period when two following comparisons of the BEMF voltage to half of the DC bus have the opposite signs.

In order to enhance the accuracy of the zero-crossing event even further, the DC bus voltage and BEMF voltage need to be measured simultaneously.

2.3.3.1 BEMF voltage measurement limitations

The accuracy of the sensorless BLDC motor control algorithm based on the BEMF voltage measurement is mostly limited by the precision of the BEMF voltage measured on a non-fed motor’s phase. For example, the ADC accuracy, precision of the phase voltage sensing circuitry, signal noise, and distortion caused by the power switching modules, all these factors need to be taken into account. Noise generated by power switching modules can be eliminated by correctly setting the measurement event to be far away from the switching edges (PWM to ADC synchronization). There still exists some limitation that cannot be eliminated, namely the decay or freewheeling period. As soon as the phase is disconnected from the power by the commutation event, there is still a current flowing through the freewheeling diode. The conducting freewheeling diode connects the released phase to either a positive or a negative DC bus voltage. The conduction time depends on the momentary load of the motor. In some circumstances, the conduction time is so long that it doesn’t allow the detection of BEMF voltage, as represented in Figure 2-10.

It is important to differentiate between the BEMF voltage generated by the motor and the phase voltage tied to a positive or negative DC bus voltage during the decay period. For this purpose, a blanking time period after the commutation event has to be employed. During this period, the BEMF voltage is not sensed or used for sensorless control. The blanking period duration should reflect the motor, load, and dynamic application parameters.

eT eT 1––TPWM

-----------------------eT

UDCB2

--------------–

TADC TZC–----------------------------- TZC⇒ TADC

eTUDCB

2--------------–

eT eT 1––--------------------------TPWM–= =




Figure 2-10. BEMF decay period

2.3.4 DC bus current measurement

Figure 2-11. DC bus current measurement

As mentioned in Section 2.3.2, "BEMF zero-crossing event detection and phase current measurement", the DC bus current has to be measured in the active cycle of the PWM period due to the fact that the DC bus current equals the phase current only in the active cycle, as illustrated in Figure 2-11.

During the active cycle of the PWM period, the phase current is rising. The slope of the rising current is defined by the motor phase coil inductance; the lower the phase inductance, the steeper the slope of the rising current.

To obtain the average value of the DC bus current directly, the voltage on the DC bus shunt resistor has to be measured in the middle of the active PWM cycle.

Phas

e Vo

ltage

decay period

PWM Switching

t

BEMF Zero crosing

TOFF period

PWM Switching Commutation Commutation

SAB

SCT

SCB

Phase A

Phase C

On

Off

Off

On

Off

On

SAT

Phase current

DC bus current = phase current(measurable by DC bus shunt)

DC bus current ≠ phase current(not measurable by DC bus shunt)

ADCSamplePoint

ΔIAverage value

of DC buscurrent




2.4 States of the sensorless BLDC control based on BEMF zero-crossing detection

In order to start and run the BLDC motor, the control algorithm has to go through the following states:• Alignment (initial position setting)• Start-up (forced commutation or open-loop mode)• Run (sensorless running with BEMF acquisition and zero-crossing detection)

2.4.1 Alignment

As mentioned previously, the main task for sensorless control of a BLDC motor is position estimation. Before starting the motor, however, the rotor position is not known. The aim of the alignment state is to align the rotor to a known position. This known position enables starting the rotation of the shaft in the desired direction and generating the maximal torque during start-up. During the alignment state, all three phases are powered in order to get the best performance behavior in either direction of shaft rotation. Phase C is connected to the positive DC bus voltage and phases A and B are grounded. The alignment time depends on the mechanical constant of the motor, including load, and also on the applied motor current.

2.4.2 Start-up

In the start-up state, motor commutation is controlled in an open-loop mode without any rotor position feedback. The commutation period is controlled by an open-loop starting curve. The open-loop start is required only until the shaft speed is high enough (approximately 5% of nominal motor speed) to produce an identifiable BEMF voltage.

2.4.3 Run

The block diagram of the run state is represented by Figure 2-12 and includes the BEMF acquisition with zero-crossing detection in order to control the commutations. The motor speed is estimated based on zero-crossing time periods. The difference between the demanded and estimated speeds is fed into the speed PI controller. The output of the speed PI controller is proportional to the voltage to be applied to the BLDC motor. The motor current is measured and filtered during the BEMF zero-crossing event and used as feedback into the current controller. The output of the current PI controller limits the output of the speed PI controller. The limitation of the speed PI controller output protects the motor current from exceeding the maximal allowed motor current.




Figure 2-12. Speed control with current limitation

3-phase

BLDC

Motor

Measurement

Required

Speed

Required

DC Bus

Current Limit

PI

Zero-crossing

Period &

Position

Recognition

1/T

PI

Commutation

Control

Actual DC Bus Current

Actual

Speed

3-phase

Inverter

Limitation

Voltage



Software implementation

Chapter 3 Software implementation

3.1 Application specificationThe sensorless BLDC application is designed to meet the following technical specification:

• Targeted at the “3-phase Sensorless BLDC Motor Control Reference Design using KEA128” printed circuit board (refer to freescale.com/KEA128BLDCRD)

• 20 kHz PWM output frequency• 1 ms speed loop sampling period• 1 ms current loop sampling period• External voltage dividers used for scaling the DC bus and phase voltages• Linear interpolation of the ADC samples used for accurate BEMF zero-crossing detection• MC33937A internal operational amplifier used for DC bus current measurement• KEA128 voltage comparators with internal DAC used for overcurrent and undervoltage detection

The Kinetis KEA128 microcontroller includes modules such as the FlexTimer (FTM), Analog-to-Digital Converter (ADC), Analog Comparator (ACMP), and System Integration Module (SIM), suitable for BLDC motor control applications. These modules are directly interconnected and can be configured to meet BLDC motor control application requirements. Figure 3-1 shows the KEA128 module interconnection for a sensorless BLDC motor control application including connection to the MC33937A pre-driver and 3-phase power stage.

3.1.1 Module interconnection

The modules involved in output actuation, data acquisition, and the synchronization of actuation and acquisition, form the so-called control loop. This control loop consists of the FTM2, FTM0, ADC and SIM modules. The control loop is very flexible in operation and can support static, dynamic, or asynchronous timing. The sensorless BLDC motor control loop is illustrated in Figure 3-1.

Each control loop cycle is started by the FTM2 PWM initialization trigger. The FTM2 generates the PWM initialization trigger event at the required PWM frequency. The PWM initialization event starts the 8-bit delay counter in the SIM module. The SIM delay counter serves as a delay block that can schedule a state variable acquisition sequence relative to the start of the PWM period and within one PWM period.



http://www.freescale.com/KEA128BLDCRD


Figure 3-1. Module interconnection configuration

3.1.2 Module involvement in the sensorless BLDC software control loop

This section describes the KEA128 internal hardware features that support the measurement of BEMF voltages and phase current.

Each commutation event gets triggered by the FTM0 channel 0 output signal. The rising edge of the FTM0 channel 0 output signal can be configured to drive the FTM2 trigger 1 input, causing the reset of the FTM2 counter to its initial value. It also generates the FTM2 PWM initialization trigger event starting the configurable 8-bit SIM delay counter. Once the 8-bit counter overflows to zero, it triggers an ADC conversion sequence. The sequence consists of the BEMF voltage, DC bus current, and DC bus voltage conversions. The principle of phase voltage, DC bus current, and DC bus voltage measurement are described in Section 2.3.3, "BEMF voltage measurement" and Section 2.3.4, "DC bus current measurement".

The ADC conversion complete interrupt notifies the CPU that the ADC conversion result values are available for reading and further processing to identify the zero-crossing event. The time of the next commutation event is then calculated based on the actual zero-crossing period.

FTM0

ADC

FTM2

ACMP1

SIM

hw_trg

trigger1

DAC

inittrg

ch0

MC33937A

ACMP0

DAC

ch5

M

+

�

KEA128

SPI

RSEN

ch0_output (commutation)

BEMF_A

BEMF_B

BEMF_C

DC bus

current

(scaled)

DC bus voltage

(scaled)

ch4

ch3

ch2

ch1

ch0

fault0

fault3

PA_HS_G

PA_LS_G

PB_HS_G

PA_LS_G

PC_HS_G

PC_LS_G

PWMAT

PWMAB

PWMBT

PWMBB

PWMCT

PWMCB

PWM init.

trigger

ADC HW

trigger

8-bit

DELAY

counter

DC bus

overcurrent

fault

delay_ovf

DC bus

under-

voltage

fault

DC bus voltage

DC bus

current




Figure 3-2. Module involvement in the sensorless BLDC software control loop

3.1.3 FlexTimer

To achieve the maximal PWM resolution, the FTM modules are supplied by the Internal Clock Source (ICS) module output clock (ICSOUTCLK). The ICSOUTCLK frequency can be derived from the internal RC (IRC) oscillator which is trimmable within the range of 31.25–39.0625 kHz. To obtain the maximum core clock frequency, the IRC needs to be trimmed to 37.5 kHz. The IRC clock is then processed by the frequency-locked loop (FLL) provided by the ICS module. The FLL, operating in the FLL engaged internal mode, locks the frequency to 1280 times the IRC frequency, resulting in the 48 MHz ICSOUTCLK. To select the ICSOUTCLK as the FTM clock source, the FTMx_SC[CLKS] bit field needs to be set to 0b01.

3.1.3.1 FTM2

FlexTimer module 2 (FTM2) is built upon a simple timer with a 16-bit counter. It contains an extended set of features that meet the demands of motor control, including the signed up-counter, dead time insertion hardware, fault control inputs, enhanced triggering functionality, and initialization and polarity control.

To enable enhanced FlexTimer features, the FTM2 has to be configured to operate without any restrictions (FTM2_MODE[FTMEN] = 1), and with the enhanced PWM synchronization mode enabled (FTM2_SYNCONF[SYNCMODE] = 1). The FTM2 module is configured to generate edge-aligned PWM with frequency of 20 kHz (FTM2_MOD = 2399) on each FTM2 channel output (FTM2_CnSC[ELSB] = 1, where n = 0, 1, 2, 3, 4, 5). In order to protect the MOSFET devices in the same inverter leg, dead time is set to approximately 400 ns1 (FTM2_DEADTIME = 19). The FTM2 counter is

BEMF DCBI

ADCSamplePoint

DCBV

MeasuredDC busvoltage

MeasuredBEMF

voltage

MeasuredDC buscurrent

Zero-cross detection

Asynchronouscommutation event

(ch0_output)

PWM counter

PWM top

Delay

Delay counter

Delay counter0

ADCSamplePoint

ADCSamplePoint

ADC conversionsequence

overflow

PWM initialization

FTM0

FTM2

SIM

ADC

CPU

trigger

reset




reset to the initial value of 0x0000 (FTM2_CNTIN = 0x0000) with every commutation event (FTM2_SYNCONF[HWRSTCNT] = 1).

To achieve a unipolar PWM pattern, all PWM channels are configured to operate in complementary PWM mode with dead time insertion (FTM2_COMBINE[DTENn] = 1, FTM2_COMBINE[COMBINEn] = 1, FTM2_COMBINE[COMPn] = 1, where n = 0, 1, 2). To match the PWM polarity with the MC33937A PWM input polarity specification, the even (high-side) channel outputs are set active low (FTM2_POL[POLn] = 1, where n = 0, 2, 4).

The control of the PWM signals of the grounded and unpowered phase is achieved by the software output control and output mask feature. The double-buffered registers FTM2_SWOCTRL and FTM2_OUTMASK are used to control the unipolar PWM pattern. The FTM2_SWCTRL register controls the PWM output by forcing selected channels into a defined state. The FTM2_OUTMASK register controls the PWM output by forcing selected channels into an inactive state. The double-buffered values are applied at each commutation event triggered by the FTM0 output signal rising edge (FTM2_SYNCONF[HWSOC] = 1, FTM2_SYNCONF[HWOM] = 1, FTM2_SYNCONF[HWTRIGMODE] = 1, FTM2_SYNC[SYNCHOM] = 1, FTM2_SYNC[TRIG1] = 1, FTM2_COMBINE[SYNCENn] = 1, where n = 0, 1, 2). Table 3-1 shows the SWOCTRL and OUTMASK values applied at a commutation event in a particular sector of the six-step commutation sequence.

To allow the application of the double-buffered values outside the commutation event, the software trigger based update can be configured (FTM2_SYNCONF[SWSOC] = 1, FTM2_SYNCONF[SWOM] = 1, FTM2_SYNCONF[SWOC] = 1). The software trigger can be generated by writing 1 to the FTM2_SYNC[SWSYNC] bit.

The duty cycle of the edge-aligned PWM is controlled by the FTM2_CnV (n = 0, 1, 2, 3, 4, 5) register values. The even register values are set to zero to generate the leading edge at the start of the PWM cycle. Odd registers define the occurrence of the trailing edge of the active PWM cycle. The duty cycle can be set according to Equation 3-1.

1. The dead time insertion can be also controlled by the MC33937A FET pre-driver. In the reference design application, the MC33937A configured dead time prolongs the dead time generated by the FTM2 to 700 ns.

Table 3-1. Software control and output mask definition in a six-step commutation sequence

Sector FTM2_SWOCTRL FTM2_OUTMASK

0 0x0808 0x34

1 0x2020 0x1C

2 0x2020 0x13

3 0x0202 0x31

4 0x0202 0x0D

5 0x0808 0x07

Alignment1

1 Alignment vector is set to allow a commutation sequence starting from sector 0.

0x0A0A 0x05

PWM off 0x0000 0x3F




Eqn. 3-1

To set the loading point of the double-buffered FTM2_CnV register values at the end of the PWM cycle, the maximum loading point has to be enabled by writing 1 to the FTM2_SYNC[CNTMAX] bit. To enable a coherent loading of the double-buffered FTM2_CnV register values at the next loading point, 1 needs to be written in the FTM2_PWMLOAD[LDOK] bit.

The PWM initialization trigger is generated at the start of each PWM cycle to trigger the ADC conversion (FTM2_EXTRIG[INITTRIGEN] = 1).

The FTM2 is configured to set all the PWM signals to an inactive state under a fault condition indicated by an active edge detected on fault input 0 or 3 (FTM2_MODE[FAULTM] = 0b10, FTM2_COMBINE[FAULTENn] = 1, where n = 0, 1, 2; FTM2_FLTCTRL[FAULTnEN], where n = 0, 3). The FTM2 resumes the PWM generation once the fault conditions are removed and the FTM2_FMS[FAULTF0] and FTM2_FMS[FAULTF3] flag bits are cleared.

3.1.3.2 FTM0

FlexTimer module 0 (FTM0) is a basic timer that consists of a 16-bit counter. The sensorless BLDC algorithm employs one timer channel (channel 0) operating in edge-aligned PWM mode.

FTM0 channel 0 serves to schedule and identify the commutation event. The channel output signal is internally routed to the FTM2 module trigger 1 input in order to perform commutation of the PWM pairs. The commutation event is scheduled by changing the PWM period (counter module value FTM0_MOD). When the counter overflows, a rising edge is generated on the channel output and an interrupt is invoked. The PWM generated by channel 0 has the duty cycle equal to 1 counter tick (FTM0_C0V = 1).

To be able to schedule long commutation periods at low speeds, the FTM0 counter is configured to run at 750 kHz frequency (ICSOUTCLK divided by 64: FTM0_SC[PS] = 0b110, FTM0_SC[CLKS] = 0b01).

3.1.4 Periodic Interrupt Timer

The Periodic Interrupt Timer (PIT) channel 0 is employed to control the speed and motor current in a software task. PIT channel 0 is configured to generate a periodic interrupt every 1 ms (PIT_LDVAL0 = 23999, PIT_TCTRL0[TIE] = 1, PIT_TCTRL[TEN] = 1). The PIT counter counts the bus clock (24 MHz).

3.1.5 System Integration Module

The System Integration Module (SIM) is intended to completely avoid CPU involvement in the timed acquisition of state variables during the control cycle.

The SIM module contains an 8-bit programmable delay counter. The delay counter is used to delay the PWM initialization trigger generated by the FTM2 (SIM_SOPT1[ADHWT] = 0b010). The delay counter is a one-shot counter that starts counting when the PWM initialization trigger arrives and stops counting when the counter value reaches the programmed modulo value, generating the ADC conversion hardware

FTM2_CnV duty_cycle FTM2_MOD× ,= (n = 1, 3, 5)




trigger. The delay counter counts the divided bus clock. The bus clock division factor is defined by the SIM_SOPT0[BUSREF] register settings.

The programmed delay should cover the MC33937A high-side driver turn-on delay, dead time, and motor phase resonance durations, to schedule the ADC conversion hardware trigger in the BEMF measurement window as shown in Figure 2-8.

3.1.6 Analog-to-Digital Converter

The Kinetis KEA128 features a single 12-bit Analog-to-Digital Converter (ADC) module. This is a 16-channel multiplexed input successive approximation ADC.

To achieve the shortest possible conversion time, the ADC clock is supplied by the Oscillator (OSC) module output clock. The OSC module operates in low-power high-frequency range mode using the external 16 MHz crystal. The ADC is configured to use the OSC output clock (Alternate clock, ADC_SC3[ADICLK] = 0b10) divided by two (ADC_SC3[ADIV] = 0b01) to obtain the maximal possible 8 MHz ADC internal clock.

The ADC module supports the FIFO operation that allows a flexible conversion sequence definition. The ADC contains two FIFOs to buffer the analog input channels and the analog results respectively. The FIFO function is enabled when its depth is set non-zero. In the case of sensorless BLDC motor control, the FIFO depth is set to 3 (ADC_SC[AFDEP] = 3) to cover the conversion of the BEMF voltage, DC bus current, and DC bus voltage. To define the conversion sequence, the analog channels corresponding to the BEMF voltage, DC bus current, and DC bus voltage must be written in the channel FIFO (ADC_SC1[ADCH]) in order. Once the FIFO is filled, the ADC waits for the software or hardware trigger.

The hardware trigger is enabled by writing 1 to the ADC_SC2[ADTRG] bit. Once the hardware trigger is generated by the SIM module, the ADC initiates the conversion sequence (ADC_SC4[HTRGME] = 1). Once all conversions indicated by the analog channel FIFO are complete, the ADC conversion complete flag is set (ADC_SC1[COCO]) and the ADC conversion complete interrupt is submitted to the CPU (ADC_SC1[AIEN] = 1).

The ADC conversion complete interrupt service routine is responsible for reading the conversion results from the result FIFO, by reading the ADC_R register (reading from ADC_R clears the ADC_SC1[COCO] flag). The results are read from the result FIFO in the same order as the analog channels were written into the analog channel FIFO. To ensure that the conversion results are not overwritten by a subsequent conversion, the hardware trigger is masked automatically when the result FIFO is not empty (ADC_SC5[HTRGMASKSEL] = 1).

After a commutation event, the analog channel FIFO needs to be re-filled to reflect the change in the BEMF voltage related analog channel.




NOTEAs the sampling point position of the BEMF voltage conversion is fixed relatively to the PWM initialization point (see Figure 3-2), the DC bus current conversion sampling point position, relative to the center of the active PWM cycle, varies with the duty cycle. Therefore, a compensation of the measured DC bus current value needs to be implemented in the software to obtain the average current value (considering actual DC bus voltage, motor phase coil inductance, and the sampling point distance from the center of the active PWM cycle).

At low duty cycles, the measured DC bus current value has to be ignored (considered zero), as the DC bus current value is measured outside of the active PWM cycle.

3.1.7 Analog Comparator

The Kinetis KEA128 uses two independent Analog Comparators (ACMP). These are used for the DC bus overcurrent (ACMP0) and DC bus undervoltage detection (ACMP1). The ACMP0 output drives the fault0 input of the FTM2, while the ACMP1 output drives the fault3 input of the FTM2. This provides CPU independent protection of the power stage under fault conditions, as described in Section 3.1.3.1, "FTM2".

Each analog comparator contains an internal 6-bit programmable DAC used for setting the comparator threshold (ACMPx_C1[DACEN] = 1). The DAC uses VDDA as the voltage reference (ACMPx_C1[DACREF] = 1). The value of the ACMPx_C1[DACREF] bit field can be calculated according to Equation 3-2.

Eqn. 3-2

Where:• VDAC is the desired threshold voltage value• VREF is the voltage on the VDDA pin

3.2 Software architectureThis section describes the software design of the sensorless BLDC algorithm based on the zero-crossing. Figure 3-3 shows the conceptual system block diagram.

The application is optimized for Kinetis KEA128 motor control peripherals to achieve the least possible core involvement in state variable acquisition and output action application. The motor control peripherals (FTM2, FTM0, SIM, ADC, ACMP0, ACMP1) are internally linked together to work independently from the core, and to achieve deterministic sampling of analog quantities and precise commutation of the stator field. The software part of the application consists of different blocks which are described below. The entire application behavior is controlled from a PC through the FreeMASTER run-time debugging tool.

ACMP0_C1[DACVAL] Round64 VDAC⋅

VDDA------------------------ 1–⎝ ⎠

⎛ ⎞= VDACVDDA

64-------------- VDDA,⟨ ⟩∈




For further information, see KEA128BLDCRDQSG, 3-phase Sensorless BLDC Motor Control Reference Design using Kinetis KEA128 Quick Start Guide.

Figure 3-3. System block diagram

The system block diagram is shown in Figure 3-3. The motor control algorithm blocks utilize the Automotive Math and Motor Control Library for ARM® Cortex®-M0+ (for more information, refer to www.freescale.com/AutoMcLib).

The inputs of the control loop are the measured voltages and current on the power stage, in particular the phase voltages, the DC bus current, and DC bus voltage. The DC bus current is amplified by the current sense amplifier, which is part of the MC33937A FET pre-driver, and then routed together with the DC bus voltage and phase voltages to the ADC for measurement acquisition.

From a control perspective, the block diagram can be divided into two logical parts:• Commutation control, where the phase voltages and DC bus voltage are used to calculate the actual

position of the shaft. According to the identified position, the next commutation event can be prepared.

• Speed/torque control, where the required shaft velocity is compared to the actual measured speed and regulated by the PI controller. The output of the speed PI controller is the duty cycle. The duty cycle is limited by the current PI controller and assigned to the PWM.

�mech

ADC (12-bit)6-ch FTM2UART FTM0

BLDC

IDCBUS

-DCBUS

+DCBUS

U

V

W

MC33937A

FreeMASTER

Application Control

Required

Speed (RPM)

Required

Current Limit

Speed

PI Controller

Current Limitation

PI Controller

Duty cycle

PWM

Modulation

Functions

Zero Cross

Detection

SIMinittrg hw_trig

Current, Torque

Calculation

New Commutation Event

Commutation Trigger

Sector

Actual Speed (RPM)

Actual Motor Current

Zero-Crossing Period

Motor Torque Filtered KEA128

SPI ACMP0 ACMP0

Overcurrent Fault

Under-/Overvoltage Fault

- +



http://www.freescale.com/AutoMcLib

http://www.freescale.com/AutoMcLib


3.2.1 Application flow

Figure 3-4. Application state flow

Figure 3-4 explains the different application states. The figure consists of two interconnected parts:• The speed over time characteristic• The blocks in the lower part of the picture, which show the states of the application and the

transitions between respective states

The application software has three main states: the alignment state, the open-loop start state, and the run state. In the run state, the BLDC motor is fully controlled in a closed-loop sensorless mode. After the initialization of the peripheral modules has completed, the software enters the alignment state. In alignment state, the rotor position is stabilized into a known position in order to create the same start-up torque in both directions of rotation. This is achieved by applying a PWM signal to phase C. Phases A and B are assigned with a duty cycle equal to zero; that is, they are connected to the negative pole of the DC bus. The value of the duty cycle on phase C depends on the motor inertia and load applied on the shaft. Such a technique aligns the shaft into position between phase A and B, which is perpendicular to both start-up flux vectors (vectors 0 and 3) generated by the stator winding, and therefore ensures the same start-up torque in both directions of rotation. The duration of the alignment state depends on the motor’s electrical and mechanical constants, the applied current (meaning duty cycle), and the mechanical load.

When the alignment time-out expires, the application software moves to the open-loop start state. At a very low shaft velocity, the BEMF voltage is too low to reliably detect the zero-crossing. Therefore, the motor has to be controlled in an open-loop mode for a certain time period. The very first vector generated by the stator windings needs to be set to a position 90° relative to the position of the flux vector generated

time

Speed

Desired

Speed

Start speed in

sensorless

closed-loop

RunOpen-Loop Start

Real speed

Open-Loop:

Commutation time

calculated based on the

acceleration equation

Alignment

Closed-Loop:

Commutation time calculated based

on the BEMF zero-crossing period

Required speed

AppInit()

AppStopToAlignment() AppStartToRun()AppAlignmentToStart()

AppRun()AppStart()AppAlignment() Called in main()

(state machine)

Transition functions

AppStop()

LC

+VDCB

(PWM)

LA

GND

Alignment

Vector

Start-up

Vector 0

Start-up

Vector 3




by magnets mounted on the rotor. The alignment and first start-up vector are shown in Figure 3-4. The duration of the open-loop start state is defined by the number of open-loop commutations. The number of open-loop commutations depends on the mechanical time constant of the motor, including load, and also on the applied voltage (duty cycle). The shaft velocity after an open-loop start-up is approximately 5% of nominal velocity. At a velocity approximately 5% of nominal velocity, the BEMF voltage is high enough to reliably detect the zero-crossing.

After a defined number of commutation cycles, the state changes from the open-loop start state to the run state. From here on, the commutation process based on the BEMF zero-crossing measurement takes place, and the control enters the closed-loop mode.

3.2.2 State machine

The application state machine is implemented using a one-dimensional array of pointers to state functions, called AppStateMachine[]. The index of the array specifies the pointer to the related application state function. The application state machine consists of the following seven states selected using the index variable appState value. The application states are listed in the Table 3-2. Possible state transitions are shown in Figure 3-5.

Table 3-2. Application states

AppStateApplication

stateDescription

0 INIT The INIT state provides the initial configuration of the PWM duty cycle, ADC external triggering, and DC bus current offset calibration. The state machine then transitions to the STOP state.

1 CALIB The CALIB state provides the DC bus current calibration. The state machine then transitions to ALIGNMENT state.

2 ALIGNMENT In the ALIGNMENT state, the alignment vector is applied to the stator to set the rotor to the defined position. The duration of the alignment state and the duty cycle applied during the state are defined by the ALIGN_DURATION and ALIGN_VOLTAGE macro values accessible in the BLDC_appconfig.h header file. The state machine then transitions to the START state.

3 START In the START state, the motor commutation is controlled in an open-loop without any rotor position feedback. The initial commutation period is controlled by the STARTUP_CMT_PER macro value. Motor acceleration (commutation period multiplier <1) is set by the START_CMT_ACCELER macro value. The number of commutations in the START state is defined by STARTUP_CMT_CNT macro value. All macro values are accessible in the BLDC_appconfig.h header file. The aim of the START state is to achieve an RPM where the zero-crossing event can be reliably detected (BEMF high enough). Once the defined number of commutations is performed, the state machine transitions to the RUN state.

4 RUN In the RUN state, the BLDC motor is controlled in the closed-loop by the sensorless algorithm (BEMF zero-crossing detection). Speed control and current limitation are performed as described in Section 3.2.5, "Speed evaluation and control" and Section 3.2.6, "Motor current limitation". The transition to the INIT state is done by setting the appSwitchState variable to 0.




Figure 3-5. Sensorless motor control application state diagram

5 STOP In the STOP state, the motor is stopped and prepared to start running. Transition to the ALIGNMENT state is performed once the appSwitchState variable is set to 1 and the freewheeling counter expires.

6 FAULT The fault detection function is executed in the main endless loop, detecting DC bus undervoltage, DC bus overvoltage, DC bus overcurrent, and MC33937A faults. Once any of the faults are detected, the state machine automatically transitions to the FAULT state. The PWM outputs are set to the safe state. To exit the FAULT state, all fault sources must be removed and the faultSwitchClear variable has to be set to 1 to clear the fault latch. The state machine then automatically transitions to the INIT state.

Table 3-2. Application states (continued)

Peripheral initialization

ALIGNMENT

STOP

START

RUN

FAULT

INIT

Fault(s) detected

AppSwitchState = 0

Reset

faultSwitchClear = 1

Fault(s) detected

Fault(s) detected

Fault(s) detected

CALIB

appSwitchState = 1




3.2.3 Application timing and interrupts

Figure 3-6. Application timing and interrupts

Figure 3-6 shows the application timing and the associated interrupts used for the commutation, zero-crossing and speed control. The grey boxes show the executed interrupt routines versus the phase voltage measurement.

The top row shows the interrupt that is activated when the ADC conversion sequence of BEMF voltage, DC bus current, and DC bus voltage has been completed. In this interrupt, the FTM0 timer counter value is saved as a BEMF measurement reference point. The zero-crossing detection algorithm is executed in each ADC conversion complete interrupt after a commutation event. Once the zero-crossing is found, the detection algorithm is disabled until the new commutation event occurs.

The second row shows the FTM0 timer counter overflow interrupt generated at the time of the commutation event. The time between each FTM0 timer counter overflow interrupt is dependent on the actual speed of the motor. The ADC conversion sequence (ADC analog channel FIFO) is reconfigured to reflect the change in the phase used for the BEMF voltage sensing.

The last row shows the PIT channel 0 time-out interrupt generated every 1 ms. This interrupt is used for speed loop control and motor current limitation, executing PI controller functions.

3.2.4 Zero-crossing detection processing

For state variable acquisition and zero-crossing detection processing, the ADC conversion sequence complete interrupt is used. The interrupt service routine is executed once the conversion sequence consisting of BEMF voltage, DC bus current, and DC bus current conversion is finished. The ADC conversion sequence complete interrupt service routine flowchart is shown in Figure 3-7.

PIT ch0 Time-out ISR

(Speed/Current Control Loop)

FTM0 overflow ISR

(Commutation event)

ADC Conversion Complete ISR

(Zero-crossing detection)

50 μsIS

R c

alls

Phase v

oltages

Commutation period

1 ms

ADC conversion time




Figure 3-7. Processing measurements in the ADC conversion sequence complete ISR

Before the ADC conversion sequence complete ISR is executed, the ADC stores the results in the ADC result FIFO. The ADC conversion results are then read from the FIFO (ADC_R register), scaled into Q1.15 fractional format, and saved into the result structure.

The scaled value of the current sense amplifier bias voltage offset is subtracted from the measured DC bus current value to obtain the bidirectional DC bus current. A filtering of the DC bus voltage and DC bus current is provided using the moving average filter functions. The BEMF voltage is then calculated as the difference between the phase voltage and the half of the DC bus voltage. The BEMF voltage value is a signed number.

The software checks whether the current decay period has already passed (see Section 2.3.3.1, "BEMF voltage measurement limitations") to initiate the zero-crossing detection. The current decay period is called TOFF (variable timeZCToff) in the application implementation (Figure 3-7).

ADC_ISR

Save time of the previous

Save time of the actual

Read the conversion

Scale the 12-bit results in

void ADC_ISR(void){ timeOldBackEmf = timeBackEmf; timeBackEmf = FTM0_CNT;

ADCResults.BEMFVoltage = (Frac16)(ADC_R << 3); ADCResults.DCBIVoltage = (Frac16)(ADC_R << 3) - ADCResults.DCBIOffset; ADCResults.DCBVVoltage = (Frac16)(ADC_R << 3);

u_dc_bus_filt = \ (Frac16)(GDFLIB_FilterMA_F16(ADCResults.DCBVVoltage, &Udcb_filt));

bemfVoltage = ADCResults.BEMFVoltage - (u_dc_bus_filt >> 1);

if(duty_cycle > DC_THRESHOLD) { torque_filt = (Frac16)(GDFLIB_FilterMA_F16(ADCResults.DCBIVoltage, &Idcb_filt)); } else { /* Ignore DC bus current measurement at low duty cycles */ torque_filt = (Frac16)(GDFLIB_FilterMA_F16((Frac16)0, &Idcb_filt)); }

if(driveStatus.B.AfterCMT == 1) { if(timeBackEmf > timeZCToff) { driveStatus.B.AfterCMT = 0; } }...

BEMF measurement

BEMF measurement

sequence results

into Q1.15 format

Check TOFF period

Calculate the BEMFvoltage

Filter DC bus voltage

Filter DC bus current




Figure 3-8. BEMF zero-crossing detection control

Where the commutation transient time TOFF has not yet expired (driveStatus.B.AfterCMT = 1), the zero-crossing calculation will not be performed. The calculation will also not be performed if the zero-crossing point has already been identified in the current commutation period (driveStatus.B.NewZC = 1), or if the application is running in open-loop mode (driveStatus.B.Sensorless = 0).

If the above mentioned conditions are not met, the zero-crossing detection routine will be executed. Based on the current commutation sector, the BEMF slope direction is checked. If the BEMF slope is negative, the sign of the calculated value is changed. This operation allows usage of a single BEMF zero-crossing detection function for a positive slope BEMF in all commutation sectors.

When the zero-crossing position calculation is finished, the BEMF voltage value is stored as the old value as it will be referenced again in the next PWM cycle.

The flow chart and the code listing in Figure 3-9 describe the zero-crossing detection routine that was called in the interrupt shown before.

... if((driveStatus.B.AfterCMT == 0) && (driveStatus.B.NewZC == 0) && (driveStatus.B.Sensorless == 1)) { /* If the Back-EMF voltage is falling, invert Back-EMF voltage value */ if((ActualCmtSector & 0x01) == 0) { bemfVoltage = -bemfVoltage; }

/* Rising BEMF voltage zero-crossing detection */ ...

/* Save actual Back-EMF voltage */ bemfVoltageOld = bemfVoltage;

driveStatus.B.AdcSaved = 1; }}

TOFF elapsed ANDzero-cross not found yet AND

Closed-loop mode

Falling BEMF voltage

yes

Save actual BEMF

Return from

no

Invert BEMF voltage value

Look for zero-cross

interrupt

voltage value

(rising BEMF voltage)




Figure 3-9. Zero-crossing detection algorithm

In the case of a negative BEMF voltage (VBEMF < VDCB / 2), the zero-crossing point has not been passed and the zero-crossing is not detectable. The software exits the zero-crossing detecting routine and leaves the zero-crossing status bit unchanged (driveStatus.B.NewZC = 0). In the case of a zero or a positive BEMF voltage (VBEMF ≥ VDCB / 2), the zero-crossing point was reached or passed and Equation 2-7 is calculated, meaning that the BEMF voltage is divided by the delta of the two measured points and multiplied by the measured PWM period (BEMF measurement period). After this calculation, the old zero-crossing time and the new one are saved into the appropriate variables. The zero-crossing period is then calculated based on the calculated time of zero-crossing and the time of the zero-crossing in the previous commutation cycle. The zero-crossing period is also filtered to improve reliability.

At the end of the routine, the new commutation time is calculated. Here, some motor characteristics have to be taken into account. Instead of just adding half of a zero-crossing period to the actual zero-crossing time, a so-called advance angle factor is taken into account, which actually activates the commutation a bit earlier than calculated. This is usually a constant and depends on the motor characteristics.

Finally, the zero-crossing status bit is set (driveStatus.B.NewZC = 1), so the zero-crossing detection does not take place anymore in the current commutation cycle.

3.2.5 Speed evaluation and control

The speed controller in Figure 3-10 is executed in a timer interrupt every 1 ms. First of all, the actual speed is calculated from all of the last six zero-crossing periods, and this is stored in a scaled format as the actual

/* Rising Back-EMF zero-crossing detection */if(bemfVoltage >= 0){ /* Rising interpolation */ delta = bemfVoltage - bemfVoltageOld; if((driveStatus.B.AdcSaved == 1) && (delta > bemfVoltage)) { timeBackEmf -= MLIB_Mul(MLIB_Div(bemfVoltage, delta), (timeBackEmf - timeOldBackEmf)); } else { timeBackEmf -= ((timeBackEmf - timeOldBackEmf) >> 1); }

lastTimeZC = timeZC; timeZC = timeBackEmf;

periodZC[ActualCmtSector] = (ftm_mod_old - lastTimeZC) + timeZC; actualPeriodZC = (actualPeriodZC + \ periodZC[ActualCmtSector]) >> 1;

NextCmtPeriod = MLIB_Mul(actualPeriodZC, advanceAngle); FTM0_UPDATE_MOD(timeZC + NextCmtPeriod);

driveStatus.B.NewZC = 1;}

yes

no

Save the time of current and

Look forzero-cross

BEMF voltage≥ VDCB / 2

BEMF voltage interpolation

previous zero-cross event

Calculate and save zero-crossperiod, filter value

Calculate and set time of thenext commutation event

Exit




speed. The required speed is fed into the ramp function controlling the motor speed slope. The difference between the speed ramp function output and actual speed defines the speed error.

In the closed-loop mode, the actual speed error is fed into the PI controller function. Inputs to the PI controller function include the speed error and the PI controller’s parameters such as the proportional and integral gain constants. The output of the PI controller is the duty cycle, which is scaled to the PWM resolution.

At the end of the speed control function, the duty cycle is loaded into the FTM2 module.

Figure 3-10. Speed evaluation software flow

3.2.6 Motor current limitation

The current limit controller is located in the same 1 ms timer interrupt as the speed controller because the inputs and outputs of both controllers are linked together.

When the actual speed has been calculated, the current limit PI controller can be called by feeding it with the difference between the actual current and the maximum allowed current of the motor. The output of the PI controller is scaled to the number proportional to the PWM period. After the current PI controller has calculated its duty cycle, both duty cycle output values are compared to each other.

Look forzero-cross

void PIT_CH0_ISR(void){ uint8_t i;

PIT_TFLG0 = PIT_TFLG_TIF_MASK; /* Clear TOF flag */ if(driveStatus.B.CloseLoop == 1) { period6ZC = periodZC[0]; for(i=1;i<6;i++) { period6ZC += periodZC[i]; }

actualSpeed = MLIB_Div(SPEED_SCALE_CONST,period6ZC); requiredSpeedRamp = \ MLIB_ConvertPU_F16F32(GFLIB_Ramp_F32( \ MLIB_ConvertPU_F32F16(requiredSpeed), &speedRampPrms)); speedErr = requiredSpeedRamp - actualSpeed; speedPIOut = GFLIB_ControllerPIpAW(speedErr, &speedPIPrms); duty_cycle = MLIB_Mul(speedPIOut, PWM_MODULO);

/* Update PWM duty cycle */ FTM2_C1V = duty_cycle; FTM2_C3V = duty_cycle; FTM2_C5V = duty_cycle; FTM2_PWMLOAD |= FTM_PWMLOAD_LDOK_MASK; } else { actualSpeed = 0; }}

actualSpeed = [scaled] 1 /(sum of all zero-cross periods)

In closed-loop mode:- Calculate speed ramp- Calculate speed error- Calculate speed PI controller- Calculate duty cycle (scale PI

output to 0 - FTM2_MOD)- Update FTM2_CnV values

with duty cycle (n = 1, 3, 5)

Return frominterrupt




If the speed PI controller duty cycle output is higher than the current limit PI controller output, then the speed PI Controller duty cycle output value is limited to the output value of the current limit PI controller. Otherwise, the speed PI duty cycle output will be taken as the duty cycle update value. The value of the duty cycle will be used to update the FTM2 module. At the end, the integral portion values of both the PI controllers need to be synchronized to avoid one of the controllers increasing its internal value as far as the upper limit. If the duty cycle was limited to the current PI duty cycle output, then the integral portion of the current PI controller will be copied into the integral portion of the speed controller, and vice versa. The above described procedure is also described in Figure 3-11.

Figure 3-11. Speed evaluation and phase current limitation

PIT CH 0ISR

void PIT_CH0_ISR(void){ uint8_t i;

PIT_TFLG0 = PIT_TFLG_TIF_MASK; /* Clear TOF flag */ if(driveStatus.B.CloseLoop == 1) { torqueErr = MLIB_SubSat(I_DCB_LIMIT, torque_filt); currentPIOut = GFLIB_ControllerPIpAW_F16(torqueErr, &currentPIPrms);

period6ZC = periodZC[0]; for(i=1;i<6;i++) { period6ZC += periodZC[i]; }

actualSpeed = MLIB_Div(SPEED_SCALE_CONST,period6ZC); requiredSpeedRamp = \ MLIB_ConvertPU_F16F32(GFLIB_Ramp_F32( \ MLIB_ConvertPU_F32F16(requiredSpeed), &speedRampPrms)); speedErr = requiredSpeedRamp - actualSpeed; speedPIOut = GFLIB_ControllerPIpAW(speedErr, &speedPIPrms); duty_cycle = MLIB_Mul(speedPIOut, PWM_MODULO);

if(currentPIOut >= speedPIOut) { /* If max torque not achieved, use speed PI output */ currentPIPrms.f32IntegPartK_1 = MLIB_ConvertPU_F32F16(speedPIOut); currentPIPrms.f16InK_1 = 0; /* PWM duty cycle update <- speed PI */ duty_cycle = MLIB_Mul(speedPIOut, PWM_MODULO); driveStatus.B.CurrentLimiting = 0; } else { /* Limit speed PI output by current PI if max. torque achieved */ speedPIPrms.f32IntegPartK_1 = MLIB_ConvertPU_F32F16(currentPIOut); speedPIPrms.f16InK_1 = 0; /* PWM duty cycle update <- current PI */ duty_cycle = MLIB_Mul(currentPIOut, PWM_MODULO); driveStatus.B.CurrentLimiting = 1; }

/* Update PWM duty cycle */ FTM2_C1V = duty_cycle; FTM2_C3V = duty_cycle; FTM2_C5V = duty_cycle; FTM2_PWMLOAD |= FTM_PWMLOAD_LDOK_MASK; } else { actualSpeed = 0; }}

actualSpeed = [scaled] 1 /(sum of all zero-cross periods)

- Calculate current error- Calculate current PI controller

- Calculate speed ramp- Calculate speed error- Calculate speed PI controller

- Calculate duty cycle (scale

yes noCurrent PI output≥ speed PI output

speed PI output to0 - FTM2_MOD)

- Calculate duty cycle (scalecurrent PI output to0 - FTM2_MOD)

Return frominterrupt

- Update FTM2_CnV valueswith duty cycle (n - 1, 3, 5)




3.2.7 Automotive Math and Motor Control Library

The application source code uses the Freescale Automotive Math and Motor Control Library Set for ARM® Cortex®-M0+ (for further information, refer to www.freescale.com/AutoMCLib) which consists of the following sub-libraries:

• Mathematical Library (MLIB) – includes basic mathematical functions such as addition, multiplication, etc.

• General Function Library (GFLIB) – includes basic trigonometric and general mathematical functions such as sine, cosine, ramp, PI controller, etc.

• General Digital Filters Library (GDFLIB) – includes digital FIR and IIR filters• General Motor Control Library (GMLIB) – includes standard algorithms used for motor control

such as Clarke/Park transformations, Space Vector Modulation, etc.



http://www.freescale.com/AutoMCLib

Application Control

Chapter 4 Application Control

4.1 FreeMASTER toolThe FreeMASTER run-time debugging tool is used to control the application and monitor application variables during run-time. The document 3-phase Sensorless BLDC Motor Control Reference Design using Kinetis KEA128 Quick start Guide, KEA128BLDCRD contains detailed information on how to set up the FreeMASTER application in order to control the reference design application.

4.2 FreeMASTER graphical user interfaceThe FreeMASTER window with an opened application project comprises several panes:

• Project Tree – Provides a logical project tree structure containing the main page, several oscilloscopes and BEMF voltage recorder.

• Variable Stimulus – Allows you to enable automatic motor speed stimulus for motor speed response observation.

• Variable Watch Grid – Contains the list of watched variables and provides a simple interface to start/stop the motor and to set the rotation speed of the motor.

• Detailed View Area – Displays the Motor Control Application Tuning (MCAT) tool GUI by default. Contents of the detailed view area change based on the selected item in the project tree.

Figure 4-1. FreeMASTER window with an application project opened

Project Tree

VariableStimulus

Detailed ViewArea

Variable Watch Grid



Application Control

4.2.1 Project tree

Allows selecting the content of the detailed view area, as follows:• KEA128_BLDC_Sensorless – displays the MCAT GUI• Speed Scope – displays the actual/required speeds in the oscilloscope• DC Bus Voltage Scope – displays the DC bus voltage detail in the oscilloscope• DC Bus Current Scope – displays the DC bus current detail in the oscilloscope• DC Bus / Speed Scope – displays the actual/required speeds, DC bus voltage, DC bus current and

filtered DC bus current in three separate oscilloscopes• Back-EMF Voltage Recorder – displays the variable recorder which allows recording of the

BEMF voltage based on a user trigger

4.2.2 Variable watch grid

The variable watch grid provides a simple interface to start/stop the motor and to set the rotation speed of the motor by modifying the watched variables according to Table 4-1. For an application control using the MCAT GUI, please refer to Section 4.3.6, "Application control tab".

4.3 Motor Control Application Tuning ToolThe MCAT is a graphical tool with a friendly environment and intuitive control. As shown in Figure 4-2, the tool consists of a motor selector bar, tab menu, and workspace. The MCAT tool represents a modular concept that consists of several sub-modules. Each sub-module represents one tab in the tab menu. The arrangement of the submodules is flexible according to the needs of the embedded application.

Table 4-1. FreeMASTER watched variables

Variable name Range Unit Editable Description

requiredSpeed 800 .. 8000 RPM Yes Sets the required speed of the motor.

actualSpeed 0 .. 2200 RPM No Reflects the actual rotation speed of the motor.

duty_cycle 0 .. 100 % No Reflects the actual PWM duty cycle.

appSwitchState 0 .. 1 Boolean Yes 0 Stop the motor1 Start the motor



Application Control

Figure 4-2. MCAT – project page

The MCAT tool is part of reference software for a dedicated MCU. Since the tuning tool cannot be used as a standalone, it is included in the FreeMASTER project by default.

The tool supports output header file generation with the calculated constants required for control algorithms, and also enables on-line updates of those application control variables selected for tuning, for example, the control loop, speed ramp, and so forth. The variables are updated by clicking the “Update Target” button on each control tab.

The set motor parameters can be stored in an internal MCAT file by clicking the “Store Data” button or the data can be reloaded by clicking the “Reload Data” button.

Each parameter and constant contains a short hint that can be activated on a parameter name mouse focus; see Figure 4-3 for an example of this hint information.

Figure 4-3. Parameter hint information

The MCAT tool workspace is unique for each tab and a detailed overview of each available tab is provided in the subsequent sections.



Application Control

4.3.1 Introduction tab

The introduction tab can be considered as a voluntary tab. It provides a room for describing or introducing the targeted motor control application, as shown in Figure 4-2.

4.3.2 Parameters tab

The parameters tab is dedicated for entering the input application parameters, as shown in Figure 4-4. It is a mandatory tab due to its high-level dependency with other tabs. Please take care while filling in an application parameter into a cell. These parameters are used across the MCAT calculations and incorrectly filled value in the cells can cause unexpected behavior in an application running on the target. The impact of each required input is described in Table 4-2. The number of input parameters needed to be filled in depends on the selected application tuning mode:

• Basic – highly recommended for users who are not experienced enough in motor control theory. The number of required input parameters is reduced. The mandatory cells are with a white background while the rest of the input parameters are calculated automatically by the MCAT tool engine. These parameters are read-only and shadowed.

• Expert – all input parameters are accessible and freely editable by the user. However, their settings require a certain level of expertise in motor control theory.

NOTEWhen switching from the Expert to Basic mode, some parameters are overridden by the automatically calculated parameter values. Values previously set in the Expert mode are not retained and need to be reloaded by changing any editable parameter value and clicking the “Reload Data” button after switching back to Expert mode.



Application Control

Figure 4-4. Parameters tab – Expert mode

Table 4-2 shows the list of the MCAT tool input parameters with their units, a brief description, typical range, and their accessibility status in basic mode.

Table 4-2. Parameters tab parameter list

Parameter name

Unit Description Typical rangeBasic mode accessibility

pp – Motor pole-pair number 1 .. 10 Yes

Iph nom A Motor nominal phase current 0.5 .. 8 Yes

Uph nom V Motor nominal phase voltage 10 .. U DCB max Yes

N nom RPM Motor nominal mechanical speed 1000 .. 40,000 Yes

I max A HW board current scale 2 .. 20 Yes

U DCB max V HW board DC bus voltage scale 20 .. 450 Yes

I DCB over A DC bus overcurrent fault threshold voltage 0.5 .. I max No

U DBC under V DC bus undervoltage fault threshold voltage 0 .. U DCB over No

U DCB over V DC bus overcurrent fault threshold voltage U DCB under .. U DCB max No

I DBC limit A DC bus current limit of control loop 0.5 .. I max No

U DBC trip V Resistor braking DC bus voltage threshold U DCB over .. U DCB max No

N max RPM Speed scale > 1.1 * N nom No



Application Control

The parameters of the controlled motor can be acquired from the motor data sheet provided by the motor manufacturer, or by laboratory measurement.

4.3.3 Control loop tab

The control loop tab is designed for speed and torque loop tuning. The torque and speed PI controllers run in parallel with a common output limitation. The tab contains input parameters for the torque and speed control loops that are used for the PI controller, the speed ramp, and speed filter constant calculations, as shown in Figure 4-5.

Figure 4-5. Control loop tab – Expert mode

Table 4-3 shows the list of the speed/torque loop input parameters with their physical units, a brief description, typical range, and their accessibility status in basic mode.

ke V.sec/rad Back-EMF constant 0.0005 .. 0.1 No

PWM freq Hz Frequency of PWM output signal 4,000 .. 20,000 No

Align voltage V Voltage for mechanical rotor alignment < U DCB max No

Align duration sec Duration of motor alignment 0.1 .. 5 sec No

Table 4-2. Parameters tab parameter list (continued)



Application Control

Clicking the “Update Target” button effects an update of the control loop and speed ramp dedicated variables in the target using the actual inputs from the tab.

Table 4-3. Control loop tab parameter list

Parameter name Unit Description Typical rangeBasic mode accessibility

Sample time s Control loop period 0.001 .. 0.01 No

Output limit high % Control loop output high limit Output limit low .. 100 No

Output limit low % Control loop output low limit 0 .. Output limit high No

Inc Up RPM/s Speed ramp increment up 100 .. 10,000 Yes

Inc Down RPM/s Speed ramp increment down 100 .. 10,000 Yes

Filter order 2n points Actual speed moving filter order 1 .. 5 No

Speed Loop Kp – Proportional gain of speed PI controller in time domain

0.00001 .. 0.1 No

Speed Loop Ki – Integral gain of speed PI controller in time domain

0.00001 .. 0.1 No

Torque Loop Kp – Proportional gain of torque PI controller in time domain

0.00001 .. 0.1 No

Torque Loop Ki – Integral gain of torque PI controller in time domain

0.00001 .. 0.1 No



Application Control

4.3.4 Sensorless tab

The sensorless tab enables parameter settings for the BLDC sensorless control algorithm. The tab is divided into two parts, the left-side fields represent those input parameters required for sensorless algorithm constant calculation and the right-side represents the read-only calculated constants, as shown in Figure 4-6.

Figure 4-6. Sensorless tab – Expert mode

Table 4-4 shows the list of the speed loop input parameters with their physical units, a brief description, typical range, and their accessibility status in basic mode.

Table 4-4. Sensorless tab parameter list

Parameter name Unit Description Typical rangeBasic mode accessibility

Timer freq Hz Frequency of timer used for commutation timing and period measurement

500,000 .. 1,000,000 No

Speed min RPM Minimal speed threshold for sensorless speed control

5 .. 10% of N nom No

Freewheel time s Freewheel counter value 0.2 .. 5 No

OL speed lim RPM Target open-loop speed; threshold to switch to closed-loop operation

Speed min + 5% of N nom No



Application Control

Clicking the “Update Target” button effects an update of the control loop and speed ramp dedicated variables in the target using the actual inputs from the tab.

4.3.5 Output file tab

The output file tab serves as a preview of the application constants corresponding to the tuned motor control application, as shown in Figure 4-7.

Figure 4-7. Output file tab – Expert mode

Cmt count – Commutation number for open-loop start-up

5 .. 15 No

1st cmt period s First commutation period duration

0.01 .. 0.0583 No

Time off % Current decay period in percentage of actual commutation period

20 .. 40 No

Integ thr corr.1 % Back-EMF integration correction factor

N/A Yes

1 This parameter value is ignored as the BEMF voltage integration method is not used by the application.

Table 4-4. Sensorless tab parameter list (continued)



Application Control

The constants are thematically divided into the groups according to selected control tabs as follows:• Application scales • Mechanical alignment • BLDC control loop • BLDC sensorless module • FreeMASTER scale variables

Application tuning modes are not available for this tab.

Click the “Generate Configuration File” button to generate the content of the output file tab. The header file BLDC_appconfig.h is generated and saved to the default path KEA128_BLDC_Sensorless\Sources\Config.

4.3.6 Application control tab

The last tab available from the tab menu is the application control tab. The application control page is based on the graphical components to provide a user friendly control interface.

Figure 4-8. Application control tab

In this view, the most important variables and settings are displayed using a graphical representation. The fan can be switched on or off by using the “ON/OFF” switch or by changing the appSwitchState variable value in the Variable Watch Grid. The required speed can be selected in the range from 800 to 8000 RPM



Application Control

either by clicking the speed gauge or by manually changing the requiredSpeed variable value in the Variable Watch Grid.

Where any fault is detected, it has to be cleared manually by clicking the green “Fault Clear” button or by setting the faultSwitchClear variable value to 0 in the Variable Watch Grid. Then, the application can be switched on again. Faults present in the system are signalized by the red fault indicators. Pending faults are signalized by small red circle indicators next to respective fault indicator.



Application Control



Hardware Specification

Chapter 5 Hardware Specification

5.1 Electrical specificationThe electrical characteristics in Table 5-1 apply to operations at 25°C and the application circuit shown in Appendix A, “Reference Design Board Schematics”.

Table 5-1. Electrical characteristics

Characteristic Symbol Min Typical Max Unit

POWER INPUT

Power Input DC Voltage Range VBAT 8 12 18 V

Supply Current1

VBAT = 12 VIBAT – 56 – mA

ANALOG MEASURMENT

ADC and ACMP0/1 Voltage Reference VREF 4.9 5.0 5.1 V

DC BUS AND PHASE VOLTAGE SENSING

DC Bus and Phase Voltage Divider Ratio VDCB_DIV – 5 – –

DC Bus and Phase Voltage Measurement RangeVREF = 5 V

VDCB_RANGE0 – 25 V

DC BUS CURRENT SENSE AMPLIFIER (MC33937A)

DC Bus Shunt Resistor RSH_DCB – 10 – mΩ

DC Bus Current Sense Amplifier Gain ADCB – 12 – –

DC Bus Current Amplifier Input Offset Voltage VDCB_OS -15 – 15 mV

DC Bus Current Sense Amplifier Measurement RangeR91 populated, R95 not populated, VREF = 5 V, VDCB_OS = 0R91 not populated, R95 populated, VREF = 5 V, VDCB_OS = 0

IDCB_RANGE-20.833

0––

20.83341.667

A

DC Bus Current Sense Amplifier Output Voltage SlopeVREF = 5 V

ΔVO_DCB/ΔIPH– 12 –

mV/A

DC BUS OVERCURRENT COMPARATOR (MC33937A)

DC Bus Overcurrent Comparator Threshold2

R91 populated, R95 not populated, VREF = 5 V, VDCB_OS = 0R91 not populated, R95 populated, VREF = 5 V, VDCB_OS = 0

IDCB_OC––

020.83

––

A




5.2 Functional description

5.2.1 Power supply

The reference design board is designed to be supplied by the voltage VBAT using the input FASTON terminals J11 (VBAT) and J12 (GND). The board power supply is reverse battery protected.

The power stage DC bus voltage is directly supplied from VBAT and is reverse battery protected.

The MC33903D system basis chip linear regulator provides the 5 V voltage (VDD) for on-board circuitry. Presence of the VDD voltage is monitored by LED D7. The VDD voltage is then split into:

• 5 V voltage supplying the KEA128 MCU and on-board digital circuitry• 5 V voltage providing the supply voltage and reference voltage to analog peripherals of the

KEA128 MCU and the supply voltage to the on-board analog circuitry

5.2.2 System basis chip

The MC33903D system basis chip (SBC) integrates a 5 V linear voltage regulator and LIN and CAN physical layer interfaces. As the SBC includes safety features such as the watchdog, supply voltage monitoring, VDD voltage level monitoring, VDD linear voltage regulator temperature monitoring, the behavior of the SBC in the Fail-safe mode needs to be configured. The SBC Fail-safe mode is configurable

PHASE CURRENT SENSE AMPLIFIERS (AD8648)

Phase Shunt Resistor RSH_PH – 10 – mΩ

DC Bus and Phase Current Sense Amplifier Gain APH – 12 – –

Input Offset Voltage VPH_OS – 0.6 3.2 mV

Phase Current Measurement RangeVREF = 5 V, VPH_OS = 0

IPH_RANGE-20.833 – 20.833

A

Output Voltage SlopeVREF = 5 V

ΔVO_PH/ΔIPH– 12 –

mV/A

PHASE OVERCURRENT COMPARATOR (NCV2903)

Phase Overcurrent Comparator Threshold2

VREF = 5 V, VPH_OS = 0 IPH_OC – 0 –A

BRAKE RESISTOR

Recommended Brake Resistor3 RBR – 15 – Ω

Recommended Power Rating PR_BR 3 – – W

1 Application in Stop state.2 Configurable by the R75/R80 voltage divider.3 Requires J13 (brake resistor terminal), Q9, R57, and R58 to be populated.

Table 5-1. Electrical characteristics (continued)

Characteristic Symbol Min Typical Max Unit




by the jumper array J6. The SBC Fail-safe mode A is enabled by default. In this mode, the VDD regulator remains ON under fault conditions, retaining power for the KEA128 and remaining on-board circuitry. For more information, refer to MC33903/4/5 Data Sheet, MC33903_4_5.

5.2.3 Local Interconnect Network (LIN) and Controller Area Network (CAN)

The MC33903D LIN transceiver #1 is used as the on-board LIN physical interface hardware. The LIN node is configured in slave mode by default. To configure it to master mode, D9 and R45 have to be assembled (see Appendix B, “Bill of Materials” for component part numbers).

Similarly, the MC33903D CAN transceiver is used as the CAN physical interface hardware. The default 120 Ω node termination is enabled by the assembled R42, R43 resistors.

The connector J7 includes both the LIN and CAN signals. Table 5-3 summarizes J7 header pin-out.

5.2.4 OpenSDA

OpenSDA is an open-standard serial and debug adapter. It bridges serial and debug communications between a USB host and an embedded target processor. The hardware circuit is based on a Freescale Kinetis K20 family microcontroller (MCU) with 128 KB of embedded flash memory and an integrated USB controller. OpenSDA features a mass storage device (MSD) bootloader, which provides a quick and easy mechanism for loading different OpenSDA applications such as flash programmers, run-control debug interfaces, serial-to-USB converters, among others. Two or more OpenSDA applications can run simultaneously. The run-control debug application and serial-to-USB converter run in parallel to provide a virtual COM communication interface while allowing code debugging via OpenSDA with just single USB connection. See the OpenSDA User’s Guide, OSDAUG, for more details.

Table 5-2. J6 jumper array description

Position Description Default setting

1-2 MC33903D Debug mode enable. Open

3-4 MC33903D Fail-safe mode A enable. Closed

5-6 MC33905D/KEA128 RESET signal interconnection enable. Open

Table 5-3. J7 signal description

Pin Signal name Description Direction

1 CAN_LO CAN bus H Differential bidirectional

2 GND Ground –

3 CAN_HI CAN bus L Differential bidirectional

4 LIN LIN bus Digital bidirectional

5 GND Ground –

6 VSUP Reverse battery protected VBAT line –




OpenSDA is managed by a Kinetis K20 MCU built on the ARM Cortex-M4 core. The OpenSDA circuit includes a status LED (D3) and a reset push-button (SW4). The push-button asserts the RESET signal to the KEA128 target MCU. It can also be used to place the OpenSDA circuit into Bootloader mode, by holding down the RESET push-button while plugging the USB cable into USB connector J2. Once the OpenSDA enters bootloader mode, other OpenSDA applications such as a debug application can be programmed.

SPI and GPIO signals provide an interface to the SWD debug port of the KEA128. Additionally, signal connections are available to implement a UART serial channel. The OpenSDA circuit receives power when the USB connector J6 is plugged into a USB host.

5.2.4.1 Debugging interface

Signals with SPI and GPIO capability are used to connect directly to the SWD of the KEA128. These signals are also brought out to a standard 10-pin (0.05”) Cortex Debug connector (J1) (see Appendix A, “Reference Design Board Schematics”).

5.2.4.2 Virtual serial port

A serial port connection is available between the OpenSDA MCU and UART pin PTI0 (UART2_RX) and PTI1 (UART2_TX) of the KEA128. Several of the default OpenSDA applications provided by Freescale, including the MSD Flash Programmer and the P&E Debug Application, provide a USB Communications Device Class (CDC) interface that bridges serial communications between the USB host and this serial interface on the KEA128.

5.2.5 3-phase power stage

The power stage is configured as a 3-phase power bridge with MOSFET output transistors. It is simplified considerably by an integrated gate driver that has several safety features. A Freescale MC33937A pre-driver provides a supply voltage for the low- and high-side MOSFET gates. It integrates an undervoltage hold-off, desaturation, phase comparators, and overcurrent protection circuits. The dead time insertion can be configured using SPI. The low- and high-side drivers are capable of providing a typical current of 1 A. This gate drive current may be limited by an external resistor to achieve a good trade-off between the efficiency and EMC compliance of the application.

Table 5-4. J1 signal description

Pin Signal name Description Direction

1 5V_MCU +5 V supply voltage –

2 SWD_DIO_TGTMCU Serial Wire Debug Data Input/Output Bidirectional

3 GND Ground –

4 SWD_CLK_TGTMCU Serial Wire Debug Clock Input

5 GND Ground –

6 – 9 – Not connected –

10 /RESET MCU Reset Bidirectional




The motor can be connected to the motor phase FASTON terminals J8 (phase A), J9 (phase B), and J10 (phase C).

5.2.6 Analog signal conditioning

This section describes the analog signal conditioning provided by the on-board circuitry.

5.2.6.1 DC bus and phase voltage dividers

The DC bus voltage and phase voltages are divided by the resistor dividers with the divider ratio of VDCB_DIV. This allows DC bus and phase voltage measurements in range of VDCB_RANGE (see Table 5-1 for actual values). The outputs of the resistor dividers are fed to the KEA128 analog input pins as listed in Table 5-5.

5.2.6.2 DC bus current sense amplifier

The MC33937A FET pre-driver integrated current sense amplifier is used as a DC bus current-to-voltage converter. The amplifier behaves as a differential amplifier, amplifying the voltage drop on the DC bus shunt resistor. The amplifier gain is set to ADCB providing a DC bus current measurement in the range of IDCB_RANGE (see Table 5-1 for actual values). Default hardware configuration provides measurement of the bidirectional DC bus current (a bias voltage of VREF/2 is applied to the positive input of the amplifier by default). The output of the current sense amplifier is fed to pin PTA1/ADC0_SE0/ACMP0_IN1 of the KEA128.

5.2.6.3 DC bus overcurrent comparator

The MC33927A FET pre-driver integrated overcurrent comparator can be used for DC bus overcurrent detection. The comparator compares the current sense amplifier output voltage with the voltage on the OC_TH pin. Once output voltage of the current sense amplifier is greater than the voltage on the pin OC_TH, the overcurrent condition is signalized by high voltage level on the OC_OUT output pin connected to the PTE7/KBI1_P7 input pin of the KEA128. The overcurrent threshold can be defined by the R75/R80 divider ratio according to Equation 5-1 or Equation 5-2 (positive current only).

Eqn. 5-1

Table 5-5. DC bus and phase voltages – MCU connection

Signal name MCU pin(s) Description

DCBV PTB4/ACMP1_IN2PTC3/ADC0_SE11

DC bus voltage.

BEMF_A PTB2/ADC0_SE6 Phase A voltage / phase A BEMF voltage.

BEMF_B PTB3/ADC0_SE7 Phase B voltage / phase B BEMF voltage.

BEMF_C PTF4/ADC0_SE12 Phase C voltage / phase C BEMF voltage.

R80R75 R80+-----------------------

IDCB_OC RSH_DCB ADCB⋅ ⋅

VREF-------------------------------------------------------------------- 0.5, (R91 populated, R95 not populated)+=




Eqn. 5-2

The reference application uses the internal analog comparator ACMP1 of the KEA128 to detect the DC bus overcurrent. The internal overcurrent comparator of the MC33937A pre-driver represents another potential solution for DC bus overcurrent detection.

5.2.6.4 Phase current sense amplifiers

To allow current measurement on each of the motor phases, the AD8648 quad operational amplifier can be used as a phase current-to-voltage converter. All three amplifiers used behave as differential amplifiers, amplifying the voltage drop on the phase shunt resistor. The amplifier gain is set to APH providing a DC bus current measurement in the range of IPH_RANGE (see Table 5-1 for actual values). The hardware configuration provides measurement of the bidirectional DC bus current (a bias voltage of VREF/2 is applied to the positive input of the amplifier). The output of each phase current sense amplifier is fed to the KEA128 analog input pin as listed in Table 5-6.

5.2.6.5 Phase overcurrent comparators

The MC33937A FET pre-driver integrated overcurrent comparator, along with the dedicated NCV2903 dual analog comparator, can be used for the overcurrent condition detection on each of the motor phases.

The output of the U8D amplifier is fed to the KEA128 internal analog comparator ACMP0 and compared with the threshold voltage of the internal 8-bit DAC. The ACMP0 comparator threshold can be set according to Equation 5-3. The output of the ACMP0 is then internally connected to the FTM2 fault0 input.

Eqn. 5-3

The dual analog comparator U10 compares the outputs of current sense amplifiers U8C (phase B) and U8B (phase C) with the threshold voltage defined by the R75/R80 divider ratio according to Equation 5-4.

Eqn. 5-4

Table 5-6. Phase current signals – MCU connection


PH_A_I PTA1/ACMP0_IN1 Phase A current.

PH_B_I PTB0/ADC0_SE4 Phase B current.

PH_C_I PTB1/ADC0_SE5 Phase C current.

R80R75 R80+-----------------------

IDCB_OC RSH_DCB ADCB⋅ ⋅

VREF-------------------------------------------------------------------- (R91 not populated, R5 populated),=

ACMP0_C1[DACVAL] Round64 IPH_OC RSH_PH APH⋅ ⋅ ⋅

VREF-------------------------------------------------------------------- 31+⎝ ⎠

⎛ ⎞=

R80R75 R80+-----------------------

IPH_OC RSH_PH APH⋅ ⋅

VREF--------------------------------------------------------- 0.5+=




NOTETo provide consistent overcurrent thresholds across all motor phases, the R75/R80 resistor divider should be set to obtain the same comparator threshold voltage level as can be obtained using the internal 8-bit DAC of the ACMP0.

The output of each particular U10 comparator is fed to the KEA128 analog input pin as listed in Table 5-7.

5.2.7 Brake chopper circuit

The brake chopper circuit is included to control the operation of losing energy from the motor through regenerative braking to an external brake resistor.

The reference design board features pads for an assembly of a logic level MOSFET transistor, Q9, with a freewheeling diode, D14. Once assembled, an external brake resistor can be connected through the two pin connector J13. Refer to Appendix B, “Bill of Materials” for component part numbers.

Table 5-7. Phase overcurrent signals– MCU connection


PH_B_OC PTA6/KBI0_P6 Phase B overcurrent.

PH_C_OC PTA7/KBI0_P7 Phase C overcurrent.



Acronyms and Definitions

Chapter 6 Acronyms and Definitions

Table 6-1. Acronyms and definitions

Term Definition

ACMP Analog Comparator

ADC Analog-to-Digital Converter

BEMF Back Electromotive Force

BLDC Brushless DC Motor

CAN Controller Area Network

CDC Communications Device Class

COM Communication Port

CPU Central Processing Unit

DAC Digital-to-Analog Converter

DC Direct Current

EMC Electromagnetic Compatibility

FET Field-Effect Transistor

FIFO First In, First Out

FLL Frequency-Locked Loop

FTM FlexTimer

GPIO General-Purpose Input/Output

GUI Graphical User Interface

HVAC Heating, Ventilation and Air Conditioning

ICS Internal Clock Source

IGBT Insulated Gate Bipolar Transistor

ISR Interrupt Service Routine

LED Light-Emitting Diode

LIN Local Interconnect Network

MCAT Motor Control Application Tuning

MCU Microcontroller Unit

MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor

MSD Mass Storage Device

OSC Oscillator

PC Personal Computer

PI Proportional-Integral



Acronyms and Definitions

PIT Periodic Interrupt Timer

PWM Pulse Width Modulation

SBC System Basis Chip

SIM System Integration Module

SPI Serial Peripheral Interface

SWD Single Wire Debug

UART Universal Asynchronous Receiver/Transmitter

USB Universal Serial Bus

Table 6-1. Acronyms and definitions

Term Definition



References

Chapter 7 References

Table 7-1. Reference list

Document Number Title Availability

KEA128RM KEA128 Sub-Family Reference Manual freescale.com

SKEA128P80M48SF0 KEA128 Sub-Family Data Sheet

MC33903_4_5 SBC Gen2 with CAN High Speed and LIN Interface Technical Data

MC33937 Three Phase Field Effect Transistor Pre-driver

KEA128BLDCRD 3-phase Sensorless Motor Control Reference Design using Kinetis KEA128 Quick Start Guide

freescale.com/KEA128BLDCRD

– 3-phase Sensorless Motor Control Reference Design using Kinetis KEA128

freescale.com/KEA128BLDCRD

– Automotive Math and Motor Control Library Set for ARM® Cortex®-M0+

freescale.com/AutoMCLib

– FreeMASTER Run-time Debugging Tool freescale.com/FREEMASTER

– Motor Control Application Tuning Tool freescale.com/MCAT



References



Reference Design Board Schematics

Appendix A Reference Design Board Schematics




5 5

4 4

3 3

2 2

1 1

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TITLE PAGE

SUPPLY

04

Table of Contents

DEBUG INTERFACE

02

MCU

03

POWER BRIDGE

0506

MOSFET DRIVERS / VI SENSING

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5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

INDICATORS

KEAZ

JTAG / SWD CONNECTOR

APPLICATION CONTROLS

XT

AL

EX

TA

L

EX

TA

LX

TA

L

SW

B0

SW

B1

DC

BV

/RE

SE

T

LED0_RED

LED0_GRN

SW_RUN_L

SW_RUN_R

/RE

SE

T

LE

D0_R

ED

LE

D0_G

RN

SW

B0

SW

B1

SW

_R

UN

_R

SW

_R

UN

_L

SW

D_D

IO_T

GT

MC

US

WD

_C

LK

_T

GT

MC

U

GN

D

5V

_M

CU

GN

DG

ND

GN

D

5V

_M

CU

5V

_M

CU

GN

DG

ND

GN

DG

ND

GN

D

5V

_M

CU

VD

DA

GN

DG

ND

GN

D

5V

_M

CU

5V

_M

CU

GN

DG

ND

GN

D

GN

D

SB

C_M

OS

I{p

g4,6

}S

BC

_M

ISO

{pg4,6

}

SB

C_S

CK

{pg4,6

}

SB

C_C

S{p

g4}

SB

C_IN

T{p

g4}

SB

C_C

AN

_R

X{p

g4}

SB

C_C

AN

_T

X{p

g4}

MC

33937A

_C

S{p

g6}

MC

33937A

_S

CK

{pg4,6

}

MC

33937A

_E

N{p

g6}

MC

33937A

_R

ST

{pg6}

MC

33937A

_S

I{p

g4,6

} MC

33937A

_S

O{p

g4,6

}

MC

33937A

_IN

T{p

g6}

SB

C_M

UX

{pg4} SB

C_LIN

_R

X{p

g4}

SB

C_LIN

_T

X{p

g4}

PW

MC

_H

S{p

g6}

PW

MB

_H

S{p

g6}

PW

MB

_LS

{pg6}

PW

MA

_LS

{pg6}

PW

MA

_H

S{p

g6}

SW

D_C

LK

_T

GT

MC

U{p

g3}

PH

_B

_O

C{p

g6}

DC

BV

{pg6}BE

MF

_B

{pg6}

BE

MF

_A

{pg6}

RX

_T

GT

MC

U{p

g3}

/RE

SE

T{p

g3,4

}

TX

_T

GT

MC

U{p

g3}

BE

MF

_C

{pg6}

DC

BI/P

H_A

_I

{pg6}

PH

_C

_I

{pg6}

PH

_B

_I

{pg6}PH

_C

_O

C{p

g6}

PW

MC

_LS

{pg6}

SW

D_D

IO_T

GT

MC

U{p

g3}

BR

AK

E_P

WM

{pg5} M

C33937A

_O

C{p

g6}

AN

_S

W{p

g6}

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hall

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n,

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X____

____

C4

0.1

uF

C8

0.1

uF

R1

4.7

K

SW

1

12

C9

0.1

uF

DN

P

C10

12P

F

R5

1K

AB

SW

3

1 2 3

C1

2.2

uF

C7

2.2

uF

R2

4.7

K

C2

0.1

uF

R7

1K

SK

EA

Z128M

LK

4

U1

PT

A0/A

DC

0_S

E0/K

BI0

_P

0/F

TM

0_C

H0/I2C

0_4W

SC

LO

UT

/AC

MP

0_IN

062

PT

A1/A

DC

0_S

E1/K

BI0

_P

1/F

TM

0_C

H1/I2C

0_4W

SD

AO

UT

/AC

MP

0_IN

161

PT

A2/K

BI0

_P

2/U

AR

T0_R

X/I2C

0_S

DA

60

PT

A3/K

BI0

_P

3/U

AR

T0_T

X/I2C

0_S

CL

59

PT

A4/S

WD

_D

IO/K

BI0

_P

4/A

CM

P0_O

UT

80

PT

A5/R

ES

ET

/KB

I0_P

5/IR

Q/T

CLK

079

PT

A6/A

DC

0_S

E2/K

BI0

_P

6/F

TM

2_F

LT

1/A

CM

P1_IN

046

PT

A7/A

DC

0_S

E3/K

BI0

_P

7/F

TM

2_F

LT

2/A

CM

P1_IN

145

PT

B0/A

DC

0_S

E4/K

BI0

_P

8/U

AR

T0_R

X/P

WT

_IN

142

PT

B1/A

DC

0_S

E5/K

BI0

_P

9/U

AR

T0_T

X41

PT

B2/A

DC

0_S

E6/K

BI0

_P

10/S

PI0

_S

CK

/FT

M0_C

H0

40

PT

B3/A

DC

0_S

E7/K

BI0

_P

11/S

PI0

_M

OS

I/F

TM

0_C

H1

39

PT

B4/N

MI/K

BI0

_P

12/F

TM

2_C

H4/S

PI0

_M

ISO

/AC

MP

1_IN

223

PT

B5/K

BI0

_P

13/F

TM

2_C

H5/S

PI0

_P

CS

/AC

MP

1_O

UT

22

PT

B6/X

TA

L/K

BI0

_P

14/I2C

0_S

DA

14

PT

B7/E

XT

AL/K

BI0

_P

15/I2C

0_S

CL

13

PT

C0/K

BI0

_P

16/F

TM

2_C

H0/A

DC

0_S

E8

32

PT

C1/K

BI0

_P

17/F

TM

2_C

H1/A

DC

0_S

E9

31

PT

C2/A

DC

0_S

E10/K

BI0

_P

18/F

TM

2_C

H2

25

PT

C3/A

DC

0_S

E11/K

BI0

_P

19/F

TM

2_C

H3

24

PT

C4/S

WD

_C

LK

/KB

I0_P

20/R

TC

_C

LK

OU

T/F

TM

1_C

H0/A

CM

P0_IN

278

PT

C5/K

BI0

_P

21/F

TM

1_C

H1/R

TC

_C

LK

OU

T77

PT

C6/K

BI0

_P

22/U

AR

T1_R

X/C

AN

0_R

X64

PT

C7/K

BI0

_P

23/U

AR

T1_T

X/C

AN

0_T

X63

PT

D0/K

BI0

_P

24/F

TM

2_C

H2/S

PI1

_S

CK

2

PT

D1/K

BI0

_P

25/F

TM

2_C

H3/S

PI1

_M

OS

I1

PT

D2/K

BI0

_P

26/S

PI1

_M

ISO

58

PT

D3/K

BI0

_P

27/S

PI1

_P

CS

57

PT

D4/K

BI0

_P

28

56

PT

D5/K

BI0

_P

29/P

WT

_IN

028

PT

D6/K

BI0

_P

30/U

AR

T2_R

X27

PT

D7/K

BI0

_P

31/U

AR

T2_T

X26

PT

E0/K

BI1

_P

0/S

PI0

_S

CK

/TC

LK

1/I2C

1_S

DA

76

PT

E1/K

BI1

_P

1/S

PI0

_M

OS

I/I2

C1_S

CL

75

PT

E2/K

BI1

_P

2/S

PI0

_M

ISO

/PW

T_IN

068

PT

E3/K

BI1

_P

3/S

PI0

_P

CS

67

PT

E4/K

BI1

_P

447

PT

E5/K

BI1

_P

521

PT

E6/K

BI1

_P

620

PT

E7/K

BI1

_P

7/T

CLK

2/F

TM

1_C

H1/C

AN

0_T

X6

PT

F0/K

BI1

_P

8/F

TM

2_C

H0

55

PT

F1/K

BI1

_P

9/F

TM

2_C

H1

54

PT

F2/K

BI1

_P

10/U

AR

T1_R

X44

PT

F3/K

BI1

_P

11/U

AR

T1_T

X43

PT

F4/A

DC

0_S

E12/K

BI1

_P

12

38

PT

F5/A

DC

0_S

E13/K

BI1

_P

13

37

PT

F6/A

DC

0_S

E14/K

BI1

_P

14

36

PT

F7/A

DC

0_S

E15/K

BI1

_P

15

35

PT

G0/K

BI1

_P

16

74

PT

G1/K

BI1

_P

17

73

PT

G2/K

BI1

_P

18

72

PT

G3/K

BI1

_P

19

71

PT

G4/K

BI1

_P

20/F

TM

2_C

H2/S

PI1

_S

CK

53

PT

G5/K

BI1

_P

21/F

TM

2_C

H3/S

PI1

_M

OS

I52

PT

G6/K

BI1

_P

22/F

TM

2_C

H4/S

PI1

_M

ISO

51

PT

G7/K

BI1

_P

23/F

TM

2_C

H5/S

PI1

_P

CS

50

PT

H0/K

BI1

_P

24/F

TM

2_C

H0

19

PT

H1/K

BI1

_P

25/F

TM

2_C

H1

18

PT

H2/K

BI1

_P

26/B

US

OU

T/F

TM

1_C

H0/C

AN

0_R

X7

PT

H3/K

BI1

_P

27/I2C

1_S

DA

34

PT

H4/K

BI1

_P

28/I2C

1_S

CL

33

PT

H5/K

BI1

_P

29

5

PT

H6/K

BI1

_P

30

4

PT

H7/K

BI1

_P

31/P

WT

_IN

13

PT

I0/IR

Q/U

AR

T2_R

X17

PT

I1/IR

Q/U

AR

T2_T

X16

PT

I2/IR

Q66

PT

I3/IR

Q65

PT

I4/IR

Q15

PT

I5/IR

Q30

PT

I6/IR

Q29

VDD_88

VDD_4949

VDD_7070

VDDA9

VREFH10

VREFL11

VSS_4848

VSS_6969

VSS/VSSA12

D1

HS

MA

_C

170

A C

R8

1.0

M

R6

1K

D18

HS

MG

-C170

A C

SW

2

12

R3

4.7

K

C3

0.1

uF

Y1

16M

HZ

1 2

C5

0.1

uF

J1

12

34 6

5 78

910

SW

4

12

R4

4.7

K

D2

HS

MS

-C170

A C

C11

12P

F




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TARG

ET M

CU

IN

TERFA

CE

SIG

NALS

DEBUG / SERIAL INTERFACE

K20_R

ES

ET

_S

WD

SI_

SP

I0_S

OU

T

UA

RT

1_R

XU

AR

T1_T

XS

I_S

PI0

_S

CK

SI_

SP

I0_S

IN

USB-SHLD

US

B_D

N_S

WD

US

B_V

BU

S_S

WD

US

B_V

BU

S

JT

AG

_T

CLK

_S

IJT

AG

_T

DI_

SI

JT

AG

_T

DO

_S

IJT

AG

_T

MS

_S

I

EX

TA

L_C

LK

_8M

HZ

_S

WD

XT

AL_C

LK

_8M

HZ

_S

WD

TR

ES

ET

_O

UT

SW

D_E

N

US

B_K

20_D

N

US

B_K

20_D

P

LE

D_S

IJT

AG

_T

CLK

_S

I

JT

AG

_T

DI_

SI

JT

AG

_T

DO

_S

I

JT

AG

_T

MS

_S

I

K20_R

ES

ET

_S

WD

EX

TA

L_R

ES

SW

D_C

LK

SW

D_C

LK

UA

RT

1_T

XU

AR

T1_R

X

SW

D_S

OU

TS

WD

_S

IN

SW

D_S

IN

SW

D_S

OU

T

SW

D_E

N

SW

D_O

E_B

SW

D_O

E_B

P5V

_U

SB

P5V

_U

SB

VO

UT

33_K

20

VO

UT

33_K

20

VO

UT

33_K

20

P5V

_U

SB

VO

UT

33_K

20

VO

UT

33_K

20

VO

UT

33_K

20

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

DG

ND

GN

D

VO

UT

33_K

20

5V

_M

CU

5V

_M

CU

VO

UT

33_K

20

GN

D

VO

UT

33_K

20

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

VO

UT

33_K

20

GN

D

GN

D

5V

_M

CU

SW

D_D

IO_T

GT

MC

U{p

g2}

/RE

SE

T{p

g2,4

}

TX

_T

GT

MC

U{p

g2}

RX

_T

GT

MC

U{p

g2}

SW

D_C

LK

_T

GT

MC

U{p

g2}

Dra

win

g T

itle

:

Siz

eD

ocum

ent N

um

ber

Rev

Date

:S

heet

of

Page T

itle

:

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ner:

Dra

wn b

y:

Appro

ved:

Aut

omot

ive

Prod

uct G

roup

6501 W

illia

m C

annon D

rive W

est

Austin, T

X 7

8735-8

598

This

docum

ent conta

ins info

rmation p

roprieta

ry to F

reescale

and s

hall

not be u

sed for

engin

eering d

esig

n,

pro

cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XS

KE

AZ1

28R

EFD

ES

A3

Tuesday, M

ay 2

0, 2014

DEB

UG

INTE

RFA

CE

B. Z

UC

ZE

K

J. K

RA

MO

LIS

B. Z

UC

ZE

K

36

X____

____

Dra

win

g T

itle

:

Siz

eD

ocum

ent N

um

ber

Rev

Date

:S

heet

of

Page T

itle

:

Desig

ner:

Dra

wn b

y:

Appro

ved:

Aut

omot

ive

Prod

uct G

roup

6501 W

illia

m C

annon D

rive W

est

Austin, T

X 7

8735-8

598

This

docum

ent conta

ins info

rmation p

roprieta

ry to F

reescale

and s

hall

not be u

sed for

engin

eering d

esig

n,

pro

cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XS

KE

AZ1

28R

EFD

ES

A3

Tuesday, M

ay 2

0, 2014

DEB

UG

INTE

RFA

CE

B. Z

UC

ZE

K

J. K

RA

MO

LIS

B. Z

UC

ZE

K

36

X____

____

Dra

win

g T

itle

:

Siz

eD

ocum

ent N

um

ber

Rev

Date

:S

heet

of

Page T

itle

:

Desig

ner:

Dra

wn b

y:

Appro

ved:

Aut

omot

ive

Prod

uct G

roup

6501 W

illia

m C

annon D

rive W

est

Austin, T

X 7

8735-8

598

This

docum

ent conta

ins info

rmation p

roprieta

ry to F

reescale

and s

hall

not be u

sed for

engin

eering d

esig

n,

pro

cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XS

KE

AZ1

28R

EFD

ES

A3

Tuesday, M

ay 2

0, 2014

DEB

UG

INTE

RFA

CE

B. Z

UC

ZE

K

J. K

RA

MO

LIS

B. Z

UC

ZE

K

36

X____

____

C18

0.1

uF

C14

0.1

uF

R10

12.0

K

C23

4700 P

FD

NP

R19

0

VC

C

GN

D

U5A

74A

HC

T125

23

141

7

5V D- D+ ID G

MIC

RO

USB

AB

5J2

1 2 3 4

S2

5

S1S3 S4

D3

HS

MG

-C170

AC

X1

8.0

0M

HZ

13

2

MK

20D

X128V

FM

5

U2 VD

D1

1

VS

S1

2

VD

DA

7

VS

SA

8

VB

AT

11

JT

AG

_T

CLK

/SW

D_C

LK

/EZ

P_C

LK

/TS

I0_C

H1/P

TA

0/U

AR

T0_C

TS

/UA

RT

0_C

OL/F

TM

0_C

H5

12

JT

AG

_T

DI/E

ZP

_D

I/T

SI0

_C

H2/P

TA

1/U

AR

T0_R

X/F

TM

0_C

H6

13

JT

AG

_T

DO

/TR

AC

E_S

WO

/EZ

P_D

O/T

SI0

_C

H3/P

TA

2/U

AR

T0_T

X/F

TM

0_C

H7

14

JT

AG

_T

MS

/SW

D_D

IO/T

SI0

_C

H4/P

TA

3/U

AR

T0_R

TS

/FT

M0_C

H0

15

NM

I/E

ZP

_C

S/T

SI0

_C

H5/P

TA

4/F

TM

0_C

H1

16

EX

TA

L/P

TA

18/F

TM

0_F

LT

2/F

TM

_C

LK

IN0

17

XT

AL/P

TA

19/F

TM

1_F

LT

0/F

TM

_C

LK

IN1/L

PT

MR

0_A

LT

118

AD

C0_S

E8/T

SI0

_C

H0/P

TB

0/I2C

0_S

CL/F

TM

1_C

H0/F

TM

1_Q

D_P

HA

20

AD

C0_S

E9/T

SI0

_C

H6/P

TB

1/I2C

0_S

DA

/FT

M1_C

H1/F

TM

1_Q

D_P

HB

21

AD

C0_S

E4B

/CM

P1_IN

0/T

SI0

_C

H15/P

TC

2/S

PI0

_P

CS

2/U

AR

T1_C

TS

/FT

M0_C

H1/I2S

0_T

X_F

S23

CM

P1_IN

1/P

TC

3/S

PI0

_P

CS

1/U

AR

T1_R

X/F

TM

0_C

H2/C

LK

OU

T/I2S

0_T

X_B

CLK

24

PT

C4/S

PI0

_P

CS

0/U

AR

T1_T

X/F

TM

0_C

H3/C

MP

1_O

UT

25

PT

C5/S

PI0

_S

CK

/LP

TM

R0_A

LT

2/I2S

0_R

XD

0/C

MP

0_O

UT

26

CM

P0_IN

0/P

TC

6/S

PI0

_S

OU

T/P

DB

0_E

XT

RG

/I2S

0_R

X_B

CLK

/I2S

0_M

CLK

27

CM

P0_IN

1/P

TC

7/S

PI0

_S

IN/U

SB

_S

OF

_O

UT

/I2S

0_R

X_F

S28

PT

D4/S

PI0

_P

CS

1/U

AR

T0_R

TS

/FT

M0_C

H4/E

WM

_IN

29

AD

C0_S

E6B

/PT

D5/S

PI0

_P

CS

2/U

AR

T0_C

TS

/UA

RT

0_C

OL/F

TM

0_C

H5/E

WM

_O

UT

30

AD

C0_S

E7b/P

TD

6/S

PI0

_P

CS

3/U

AR

T0_R

X/F

TM

0_C

H6/F

TM

0_F

LT

031

PT

D7/C

MT

_IR

O/U

AR

T0_T

X/F

TM

0_C

H7/F

TM

0_F

LT

132

VR

EG

IN6

VO

UT

33

5

US

B0_D

M4

US

B0_D

P3

EX

TA

L32

10

XT

AL32

9

RE

SE

T19

AD

C0_S

E15/T

SI0

_C

H14/P

TC

1/S

PI0

_P

CS

3/U

AR

T1_R

TS

/FT

M0_C

H0/I2S

0_T

XD

022

EP

AD

33

U5C

74A

HC

T125

98

10

R18

12.0

K

R12

12.0

K

R14

33

C24

0.1

uF

J3

12

34 6

5 78

910

R15

4.7

K

C26

0.1

uF

L1

1000O

HM

C21

47P

F

C19

0.1

uF

R24

0

C13

0.1

uF

L2

1000O

HM

U3

GS

OT

05C

-GS

08

1

23

U5B

74A

HC

T125

56

4

R20

0

C22

47P

F

R25

0

C15

2.2

uF

R27

0

R109

4.7

K

C20

0.1

uF

R13

33

R22

12.0

K

U5D

74A

HC

T125

12

11

13

R110

4.7

K

VCC GND

2Y

1Y

1A

1O

E

2A

2O

E

U6

74LV

C2G

125

6 3

2 71 548

R26

0

R21

0

R23

1K

C12

2.2

uF

C25

0.1

uF

R16

4.7

KU

4

NT

S0102

GND2

B2

1

VCCB7

VCCA3

B1

8

OE

6

A1

5

A2

4

R11

1.0

M

R17

6.8

0K




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Close to

Vsup pin

CAN/LIN

MASTER OPTION

RS

T

VC

AN

CA

N_L0

CA

N_H

I

SAFE

SA

FE

SB

C_IO

_0

LIN

DB

G

RS

T

PG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

5V

_M

CU

5V

_M

CU

VS

UP

5V

_M

CU

GN

D

VS

UP

VB

AT

VD

DA

GN

DG

ND

GN

D

GN

D

VS

UP

GN

D

GN

D

GN

D

PG

ND

GN

DVS

UP

SB

C_M

ISO

{pg2,6

}

SB

C_S

CK

{pg2,6

}S

BC

_M

OS

I{p

g2,6

}

SB

C_C

S{p

g2}

SB

C_C

AN

_T

X{p

g2}

SB

C_C

AN

_R

X{p

g2}

SB

C_LIN

_T

X{p

g2}

SB

C_LIN

_R

X{p

g2}

SB

C_M

UX

{pg2}

SB

C_IN

T{p

g2}

PG

ND

{pg2}

/RE

SE

T{p

g2,3

}

Dra

win

g T

itle

:

Siz

eD

ocum

ent N

um

ber

Rev

Date

:S

heet

of

Page T

itle

:

Desig

ner:

Dra

wn b

y:

Appro

ved:

Auto

mot

ive

Prod

uct G

roup

6501 W

illia

m C

annon D

rive W

est

Austin, T

X 7

8735-8

598

This

docum

ent conta

ins info

rmation p

roprieta

ry to F

reescale

and s

hall

not be u

sed for

engin

eering d

esig

n,

pro

cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XSK

EAZ1

28R

EFD

ES

A3

Tuesday, M

ay 2

0, 2014

POW

ER S

UPPL

Y

B. Z

UC

ZE

K

J. K

RA

MO

LIS

B. Z

UC

ZE

K

46

X____

____

Dra

win

g T

itle

:

Siz

eD

ocum

ent N

um

ber

Rev

Date

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reescale

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hall

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n,

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cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XSK

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Tuesday, M

ay 2

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docum

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ins info

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reescale

and s

hall

not be u

sed for

engin

eering d

esig

n,

pro

cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XSK

EAZ1

28R

EFD

ES

A3

Tuesday, M

ay 2

0, 2014

POW

ER S

UPPL

Y

B. Z

UC

ZE

K

J. K

RA

MO

LIS

B. Z

UC

ZE

K

46

X____

____

J6

12

34 6

5

R41

1K

R34

0

SW

5E

VQ

-PE

105K

DN

P

12

C42

47P

F

D7

HS

MG

-C170

A C

R29

0

L4

1000O

HM

C34

220P

F

R37

12.0

K

DN

P

R45

1K

DN

P

C37

0.1

uF

D4

MB

R230LS

FT

1G

AC

R44

0

R30

4.7

K

D6

HS

MS

-C170

A C

R35

0

C38

82pF

J11

11

22

C41

2.2

uF

C43

4700 P

FJ7

12

34 6

5

C32

0.1

uF

EB

C

Q1

BC

P52-1

6

1

324

R36

120.0

L3

1000O

HM

C39

0.1

uF

DN

P

R31

0

U7

MC

Z33903C

D5E

K

MU

X-O

UT

11

IO-0

12

VSUP2

DB

G13

RX

D31

VE32

VB1

SA

FE

5

RX

D-L

216

TX

D-L

120

GND115

RX

D-L

121

CA

NH

7

SP

LIT

10

CA

NL

8

LIN

-T1/I/O

-24

LIN

217

MIS

O28

VS

EN

SE

22

RS

T23

SC

LK

26

CS

25

MO

SI

27

INT

24

TX

D-L

214

5V

-CA

N6

VD

D29

TX

D30

GND218

LIN

119

GND_CAN9

EX_PAD33

LIN

-T2/I/O

-33

D9

MM

SD

914T

1D

NP

AC

R38

12.0

K

DN

P

R39

4.7

KD

NP

J12

11

22

C31

2.2

uF

+C

28

47U

F

L5

B82789C

0513N

002

1 3

2 4

C27

0.1

uF

R40

1K

C29

10uF

C35

0.1

uF

C44

220P

F

C40

0.1

uF

R42

60.4

D5

MM

SZ

8V

2T

1G

AC

R33

0

SH

2

0

R43

60.4

C36

2.2

uF

R32

4.7

K

R28

1K

C33

0.1

uF




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

3W MAX

OUTPUT TERMINAL

BRAKE RES.

TERMINAL

PH

B_H

SS

PH

C_H

SS

PH

A_H

SS

PG

ND

VB

AT

DC

B_V

_P

OS

PG

ND

PG

ND

PH

A_H

SG

{pg6}

PH

B_H

SG

{pg6}

PH

C_H

SG

{pg6}

PH

A_LS

G{p

g6}

PH

B_LS

G{p

g6}

PH

C_LS

G{p

g6}

PH

A_H

SS

{pg6}

PH

B_H

SS

{pg6}

PH

C_H

SS

{pg6}

PH

A_LS

S{p

g6}

PH

B_LS

S{p

g6}

PH

C_LS

S{p

g6}

DCB_I_POS

{pg6}

DCB_I_NEG

{pg6}

PH

A_I_

PO

S{p

g6}

PH

A_I_

NE

G{p

g6}

PH

B_I_

PO

S{p

g6}

PH

B_I_

NE

G{p

g6}

PH

C_I_

PO

S{p

g6}

PH

C_I_

NE

G{p

g6}

BR

AK

E_P

WM

{pg2}

PG

ND

{pg2}

Dra

win

g T

itle

:

Siz

eD

ocum

ent N

um

ber

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Date

:S

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itle

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ive

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annon D

rive W

est

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X 7

8735-8

598

This

docum

ent conta

ins info

rmation p

roprieta

ry to F

reescale

and s

hall

not be u

sed for

engin

eering d

esig

n,

pro

cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XSK

EAZ1

28R

EFD

ES

A3

Tuesday, M

ay 2

0, 2014

POW

ER B

RIDG

E

B. Z

UC

ZE

K

J. K

RA

MO

LIS

B. Z

UC

ZE

K

56

X____

____

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itle

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eD

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ber

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heet

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itle

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annon D

rive W

est

Austin, T

X 7

8735-8

598

This

docum

ent conta

ins info

rmation p

roprieta

ry to F

reescale

and s

hall

not be u

sed for

engin

eering d

esig

n,

pro

cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XSK

EAZ1

28R

EFD

ES

A3

Tuesday, M

ay 2

0, 2014

POW

ER B

RIDG

E

B. Z

UC

ZE

K

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X 7

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598

This

docum

ent conta

ins info

rmation p

roprieta

ry to F

reescale

and s

hall

not be u

sed for

engin

eering d

esig

n,

pro

cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XSK

EAZ1

28R

EFD

ES

A3

Tuesday, M

ay 2

0, 2014

POW

ER B

RIDG

E

B. Z

UC

ZE

K

J. K

RA

MO

LIS

B. Z

UC

ZE

K

56

X____

____

R46

33

R54

33

Q6

AU

IRF

R3607

1

34

Q3

AU

IRF

R3607

1

34

R56

33

J8 1 2

R49

33

Q4

AU

IRF

R3607

1

34

Q8

AU

IRF

R3607

1

34

D12

BA

S16H

AC

SG

D

Q2

AU

IRF

R5305

43

1

R51

33

D11

BA

S16H

AC

R58

4.7

KD

NP

D14

MBR230LSFT1G

DN

P

AC

J9 1 2

J13

1702473

DN

P

12

R47

33

D10 MMSZ5248ET1

AC

R61

0.0

1

R62

0.0

1

R60

0.0

1

Q7

AU

IRF

R3607

1

34

R57

33

DN

P

R52

1.0

K

J10

1 2

+C

45

220uF

R48

33

R59

0.0

1

Q5

AU

IRF

R3607

1

34

D13

BA

S16H

AC

R55

33

Q9

RS

R025N

05F

RA

DN

P

1

23

R50

33




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DC BUS Current Sensing

Back EMF Voltage sensing

DC BUS Voltage sensing

5V @ 25V * (3K/(12K+3K))

A = 12K / 1K = 12

Ua = (Idcb * 0.01 * A) + 2.5V

PHASE A/B/C CURRENT SENSING

Close to ADC pin

DC BUS Current/Phase_A current switch

Close to ADC pin

Iner

nal

pull

-up

must

be

acti

vate

d in

MCU

Idcb = <-20.83 .. 20.83> [A]

Ua = <0 .. 5> [V]

AM

P_N

AM

P_P

VR

EF

/2

DC

BI

AM

P_N

AM

P_P

GN

D

VLS

DC

BI

OC

_T

H

VLS

_C

AP

PH

C_H

SS

PH

B_H

SS

PH

A_H

SS

PH

_A

_I

VR

EF

/2

VR

EF

/2

VR

EF

/2

PH

_A

_I

DC

BI

OC

_T

H

VR

EF

/2

PG

ND

GN

D

GN

DG

ND

GN

D

DC

B_V

_P

OS

VLS

VD

DA

VD

DA

5V

_M

CU

GN

D

GN

D

VD

DA

GN

D

GN

D

DC

B_V

_P

OS

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

VD

DA

PG

ND

PG

ND

PG

ND

MC

33937A

_C

S{p

g2} M

C33937A

_S

CK

{pg2,4

}

MC

33937A

_E

N{p

g2} M

C33937A

_R

ST

{pg2}

MC

33937A

_S

I{p

g2,4

}

MC

33937A

_S

O{p

g2,4

}

MC

33937A

_IN

T{p

g2}

PW

MC

_LS

{pg2}

PW

MC

_H

S{p

g2}

PW

MB

_H

S{p

g2}

PW

MB

_LS

{pg2}

PW

MA

_H

S{p

g2}

PW

MA

_LS

{pg2}

DC

B_I_

PO

S{p

g5}

DC

B_I_

NE

G{p

g5}

PH

C_LS

S{p

g5}

PH

B_LS

S{p

g5}

PH

A_LS

S{p

g5}

PH

C_H

SS

{pg5}

PH

B_H

SS

{pg5}

PH

A_H

SS

{pg5}

PH

A_H

SG

{pg5}

PH

B_H

SG

{pg5}

PH

C_H

SG

{pg5}

PH

A_LS

G{p

g5}

PH

B_LS

G{p

g5}

PH

C_LS

G{p

g5}

BE

MF

_A

{pg2}

BE

MF

_B

{pg2}

BE

MF

_C

{pg2}

PH

B_I_

PO

S{p

g5}

PH

B_I_

NE

G{p

g5}

PH

C_I_

PO

S{p

g5}

PH

C_I_

NE

G{p

g5}

PH

A_I_

PO

S{p

g5}

PH

A_I_

NE

G{p

g5}

PH

_B

_I

{pg2}

PH

_C

_I

{pg2}

PH

_C

_O

C{p

g2}

PH

_B

_O

C{p

g2}

AN

_S

W{p

g2}

DC

BI/P

H_A

_I

{pg2}

DC

BV

{pg2}

MC

33937A

_O

C{p

g2}

PG

ND

{pg2}

Dra

win

g T

itle

:

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eD

ocum

ent N

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ber

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Date

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itle

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uct G

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annon D

rive W

est

Austin, T

X 7

8735-8

598

This

docum

ent conta

ins info

rmation p

roprieta

ry to F

reescale

and s

hall

not be u

sed for

engin

eering d

esig

n,

pro

cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XSK

EAZ1

28R

EFD

ES

A3

Tuesday, M

ay 2

0, 2014

MO

SFET

DRI

VERS

/ VI

SEN

SING

B. Z

UC

ZE

K

J. K

RA

MO

LIS

B. Z

UC

ZE

K

66

X____

____

Dra

win

g T

itle

:

Siz

eD

ocum

ent N

um

ber

Rev

Date

:S

heet

of

Page T

itle

:

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ner:

Dra

wn b

y:

Appro

ved:

Auto

mot

ive

Prod

uct G

roup

6501 W

illia

m C

annon D

rive W

est

Austin, T

X 7

8735-8

598

This

docum

ent conta

ins info

rmation p

roprieta

ry to F

reescale

and s

hall

not be u

sed for

engin

eering d

esig

n,

pro

cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XSK

EAZ1

28R

EFD

ES

A3

Tuesday, M

ay 2

0, 2014

MO

SFET

DRI

VERS

/ VI

SEN

SING

B. Z

UC

ZE

K

J. K

RA

MO

LIS

B. Z

UC

ZE

K

66

X____

____

Dra

win

g T

itle

:

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eD

ocum

ent N

um

ber

Rev

Date

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heet

of

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itle

:

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ner:

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wn b

y:

Appro

ved:

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mot

ive

Prod

uct G

roup

6501 W

illia

m C

annon D

rive W

est

Austin, T

X 7

8735-8

598

This

docum

ent conta

ins info

rmation p

roprieta

ry to F

reescale

and s

hall

not be u

sed for

engin

eering d

esig

n,

pro

cure

ment or

manufa

ctu

re in w

hole

or

in p

art

without th

e e

xpre

ss w

ritten p

erm

issio

n o

f F

reescale

.

ICA

P C

lassific

ation:

FC

P:

FIU

O:

PU

BI:

SC

H-2

8289 P

DF

: S

PF

-28289

C

XSK

EAZ1

28R

EFD

ES

A3

Tuesday, M

ay 2

0, 2014

MO

SFET

DRI

VERS

/ VI

SEN

SING

B. Z

UC

ZE

K

J. K

RA

MO

LIS

B. Z

UC

ZE

K

66

X____

____

-+U

8D AD

8648W

AR

UZ

12

13

14

R93

12.0

K

C55

0.1

uF

D15

MB

R230LS

FT

1G

AC

R65

1K

C50

47P

F

R82

1K

R74

120.0

+C

48

47U

F

C80

82pF

C67

47P

F

C60

0.1

uF

R85

1.0

M

C58

47P

F

R73

12.0

K

R104

120.0

C65

82pF

R108

3.0

K

R107

3.0

K

C57

0.1

uF

C61

0.1

5U

F

R71

12.0

K

R94

12.0

K

C84

82pF

R106

3.0

K

R84

1.0

M

-+U

8C

AD

8648W

AR

UZ

10 9

8

R101

120.0

R76

1K

R89

12.0

KC68

47P

F

C72

0.1

uF

C49

0.1

uF

R98

12.0

KR

88

12.0

K

R69

120.0

R83

12.0

K

C47

1uF

C70

0.1

uF

C63

0.1

5U

F

R90

1K

C82

82pF

R96

12.0

K

R77

12.0

K

C77

47P

FR

112

4.7

K

R80

12.0

K

C79

4700 P

F

C78

220P

F

R67

1K

-+U

8B AD

8648W

AR

UZ

5 67

R75

12.0

K

C83

82pF

C54

2.2

UF

C74

0.1

uF

C75

4700 P

F

R63

1K

C76

47P

F

-+V

+

V-U

8A

AD

8648W

AR

UZ

3 21

4 11

R95

12.0

KD

NP

C71

2.2

uF

C53

0.1

uF

R81

12.0

K

R103

120.0

R102

120.0

C66

0.1

5U

F

R92

12.0

K

D16

MBR230LSFT1G

AC

R91

12.0

K

R72

1K

C62

47P

F

NLV

AS

B3157D

FT

2G

U11

B1

1

GN

D

2

B0

3

A4

VC

C5

S6

R105

3.0

K+C

59

47U

F

C81

82pF

R100

120.0

R70

1K

R99

12.0

K

C52

2.2

UF

R64

12.0

K

C56

2.2

uF

C73

2.2

uF

R97

12.0

K

C69

82pF

U9

MC

33937A

PE

K

PH

AS

EA

1

PGND2

EN

13

EN

24

RS

T5

PUMP7

VPUMP8

VSUP9

PH

AS

EB

10

PH

AS

EC

11

PA

_H

S12

PA

_LS

13

VDD14

PB

_LS

16

INT

17

CS

18

SI

19

SC

LK

20

SO

21

PC

_LS

22

AM

P_O

UT

24

AM

P_N

25

AM

P_P

26

OC

_O

UT

27

OC

_T

H28

VSS29

GND130

GND231

VLS_CAP32 PC_LS_S

34

PC

_LS

_G

35

PC

_H

S_S

36

PC

_H

S_G

37

PC

_B

OO

T38

PB_LS_S39

PB

_LS

_G

40

PB

_H

S_S

41

PB

_H

S_G

42

PB

_B

OO

T43

PA_LS_S44

PA

_LS

_G

45

PA

_H

S_S

46

PA

_H

S_G

47

PA

_B

OO

T48

VLS51

NC

66

VPWR54

PB

_H

S15

PC

_H

S23

NC

33

33

NC

49

49

NC

50

50

NC

52

52

NC

53

53

EP_PAD55

C64

47P

F

R68

12.0

K

U10

NC

V2903

OU

TA

1-I

NA

2+

INA

3

+IN

B5

-IN

B6

OU

TB

7

GND4

V+8

R66

12.0

K



Bill of Materials

Appendix B Bill of Materials

Table 7-2. Bill of materials

Item number

Quantity Value Part reference Manufacturer Manufacturer part number

1 10 2.2 μF C1, C7, C12, C15, C31, C36, C41, C56, C71, C73

Murata GCM188R70J225KE22D

2 29 0.1 μF C2, C3, C4, C5, C8, C9, C13, C14, C18, C19, C20, C24, C25, C26, C27, C32, C33, C35, C37, C39,C40, C49, C53, C55, C57, C60, C70, C72, C74

Murata GCM188R71H104KA57D

3 2 12 pF C10, C11 AVX 06033A120KAT2A

4 11 47 pF C21, C22, C42, C50, C58, C62, C64, C67, C68, C76, C77

AVX 06035U470KAT2A

5 2 4700 pF C23, C43, C75, C79 AVX 06035C472JAT2A

6 3 47 μF C28, C48, C59 Panasonic EEEFK1H470XP

7 1 10 μF C29 TDK CGA4J1X7R0J106K125AC

8 3 220 pF C34, C44, C78 Kemet C0603C221K5RAC

9 8 82 pF C38, C65, C69,C80, C81, C82, C83, C84

Kemet C0603C820K5GACTU

10 1 220 μF C45 Panasonic EEEFK1H221P

11 1 1.0 μF C47 Murata GCM21BR71H105KA03

12 2 2.2 μF C52, C54 Capax Technologies, Inc. 0805X225J500SNT

13 3 0.15 μF C61, C63, C66 Venkel Ltd. C0805X7R250-154KNE

14 1 – D1 Avago Technologies HSMA-C170

15 2 – D2, D6 Avago Technologies HSMS-C170

16 3 – D3, D7, D18 Avago Technologies HSMG-C170

17 4 – D4, D14, D15, D16 ON Semiconductor MBR230LSFT1G

18 1 – D5 ON Semiconductor MMSZ8V2T1G

19 1 – D9 ON Semiconductor MMSD914T1G

20 1 – D10 ON Semiconductor MMSZ5248BT1G

21 3 – D11, D12, D13 ON Semiconductor BAS16HT1G

22 2 – J1, J3 Samtec FTS-105-01-F-DV-P-TR

23 1 – J2 Molex 47589-0001

24 2 – J6, J7 Samtec TSM-103-01-S-DV-P-TR



Bill of Materials

25 3 – J8, J9, J10 TE Connectivity Ltd. 928814-1

26 2 – J11, J12 TE Connectivity Ltd. 63849-1

27 1 – J13 Phoenix Contact 1702473

28 4 – L1, L2, L3, L4 Murata BLM18AG102SH1

29 1 – L5 Epcos B82789C0513N002

30 1 – Q1 NXP Semiconductors BCP52-16

31 1 – Q2 International Rectifier AUIRFR5305

32 6 – Q3, Q4, Q5, Q6, Q7, Q8 International Rectifier AUIRFR3607

33 1 – Q9 ROHM RSR025N05FRA

34 13 4.7 kΩ R1, R2, R3, R4, R15, R16, R30, R32, R39, R58, R109, R110, R112

Vishay Intertechnology CRCW06034K70JNEA

35 16 1.0 kΩ R5, R6, R7, R23, R28, R40, R41, R45, R63, R65, R67, R70, R72, R76, R82, R90

ROHM ESR03EZPF1001

36 3 1.0 MΩ R8, R84, R85 Walsin Technology Corp. WR06X1004FTL

37 27 12.0 kΩ R10, R12, R18, R22, R37, R38, R64, R66, R68, R71, R73, R75, R77, R80, R81, R83, R88, R89, R91, R92, R93, R94, R95, R96, R97, R98, R99

KOA Speer RK73H1JTTD1202F

38 1 1.0 MΩ R11 Bourns CR0603-JW-105ELF

39 12 33 Ω R13, R14, R46, R47, R48, R49, R50, R51, R54, R55, R56, R57

Vishay Intertechnology CRCW060333R0JNEA

40 1 6.8 kΩ R17 KOA Speer RK73H1JTTD6801F

41 13 0 Ω R19, R20, R21, R24, R25, R26, R27, R29, R31, R33, R34, R35, R44

Vishay Intertechnology CRCW06030000Z0EA

42 8 120.0 Ω R36, R69, R74, R100, R101, R102, R103, R104

KOA Speer RK73H1JTTD1200F

43 2 60.4 Ω R42, R43 Vishay Intertechnology CRCW120660R4FKEA

44 1 1.0 kΩ R52 Bourns CR1206-JW-102ELF

45 4 0.01 Ω R59, R60, R61, R62 Bourns CRA2512-FZ-R010ELF

46 4 3.0 kΩ R105, R106, R107, R108 KOA Speer RK73H1JTTD3001F

48 4 – SW1, SW2, SW4, SW5 Panasonic EVQPE105K

49 1 – SW3 C&K Components JS102011SAQN

Table 7-2. Bill of materials (continued)

Item number




Bill of Materials

50 1 – U1 Freescale Semiconductor SKEAZ128MLK4

51 1 – U2 Freescale Semiconductor MK20DX128VFM5

52 1 – U3 Vishay Intertechnology GSOT05C-GS08

53 1 – U4 NXP Semiconductors NTS0102DP

54 1 – U6 NXP Semiconductors 74LVC2G125DP,125

55 1 – U7 Freescale Semiconductor MCZ33903CD5EK

56 1 – U9 Freescale Semiconductor MC33937APEK

57 1 – U10 ON Semiconductor NCV2903DMR2G

58 1 – U11 ON Semiconductor NLVASB3157DFT2G

59 1 – U5 NXP Semiconductors 74AHCT125PW

60 1 – U8 Analog Devices AD8648WARUZ

61 1 – X1 Murata CSTCE8M00G55-R0

62 1 – Y1 TXC Corp. AA-16.000MALE-T

Table 7-2. Bill of materials (continued)

Item number




Bill of Materials



Document Number: DRM151Rev. 006/2014

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