International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 2 Issue 6, September 2014, ISSN No.: 2348 – 8190

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DRAM TESTING USING INTERLEAVING TEST ALGORITHM

T.Boobalan, Anila Ramachandran,V.Kavitha, S.Rathimeena

Assistant professor, ECE Department, Sri Eshwar college of engineering, Coimbatore.

ME-VLSI design students, Sri Eshwar College of Engineering, Coimbatore.

ABSTRACT For more than four decades, the simple structure of the

dynamic RAM (DRAM) cell and continuous

improvement in lithography and dry-etching

technology has made DRAM grow exponentially in a

large-scale integration and has decreased the minimum

feature size in memory chips. In the field of testing,

more appropriate test algorithms are required to protect

DRAM cell data.In this paper an Interleaving test

algorithm is presented, which requires a read time of

110µs. This test algorithm allows screening of weak

cells that cannot hold cell data due to the sub threshold

leakage current with a screen coverage of 35.2%.

During the stress period, the algorithm can also detect

other leakage currents.

Index Terms—Read time, screen coverage, stress

period, sub-threshold leakage current, Test algorithm.

I. INTRODUCTION

For better performance and lower power consumption,

the memory chip has been scaled down every year.

The 2010 ITRS Roadmap reports that the minimum

feature size of DRAM will be 20 nm in 2017 and 10

nm in 2023 [1]. However, with this down-scaling trend

of the minimum feature size and power, many

problems (capacitor/bit-line/word-line bridges, coup-

ling noise, P-MOS/N-MOS ratio, leakage current and

so on) need to be considered. With the short length of

the word-line channel, the sub threshold leakage

current will increase more. To prevent this subth-

reshold leakage-current problem, channel doping

should be increased in order to maintain adequate

control of short-channel effects.However, junction

leakage current due to band-to-band tunneling and

gate-induced drain leakage current may increase as a

result of high channel doping. The variability of the

threshold voltage can also increase due to defects

resulting from manufacturing aberrations [2]–[6].

To detect these complicated defects, it is

necessary to analyze the fail mechanism and find

appropriate test algorithms. Conventional DRAM

testing can be grouped into retention testing and

functional testing [7]. Retention testing is a test

method that screens leakage current defects by

operating read and write functions containing a

particular delay time. In functional testing, March

elements that are a finite sequence of read or write

operations applied to a cell in memory before

proceeding to the next cell are conducted on each

memory cell in order to detect the cell-to-cell bridge

and coupling noise. Due to the flexibility of these

March elements, most Built-In Self Test (BIST)

architectures adopt functional test algorithms using the

conventional March elements [8], [9].

To test for leakage-current defects, several studies

have attempted to implement retention testing using

special techniques. The word-line-pulsing technique

has been proposed as a means of detecting weak cells

by coupling nearby neighbour word lines [10]. This

technique results in an adjustable test stress based on

setting the word-line enable time. This method can be

used to detect sub threshold leakage-current defects;

but when it is used in DRAM, it has to consider stress

equality according to the cell location during the stress

enable time. March complex read faults (CRF, which

is also suggested in static RAM) detects faulty cells

induced by the leakage current using the voltage gap

between the bit line and the target cell with opposite

data [11]. However, according to our experimental

results, March CRF has lower screenability than the

wordline pulsing technique. X-direction-Extended

March C- and Y -direction MATS are proposed to

screen retention faults using self-refresh and time

delay in eDRAM [12], but these studies mainly deal

with detecting retention faults and analyzing the

relationship between the leakage current and

temperature. They do not focus on the sub threshold

leakage-current defects. A large VDS data retention

test is also proposed to detect leakage-current defects

in DRAM [13]. However, most of the previous works

have not considered stress differences among cells

caused by cell locations due to the refresh operation of

DRAM. Therefore, the quality problems can occur.

Thus, a more powerful screening technique is needed

to detect sub threshold leakage-current defects. This

paper proposes a new efficient test algorithm for equal

bit-line stress in order to screen for sub threshold

leakage current defects. During the stress time, the

algorithm can detect other leakage-current defects.

This paper is organized as follows. Section II

introduces the simplified DRAM architecture. Sections

III and IV explain the interleaving test algorithm and

the simulation results obtained by using Tanner13.0.

Finally, Section V concludes the paper.

International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 2 Issue 6, September 2014, ISSN No.: 2348 – 8190

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II. BACKGROUND

A.DRAM OVERVIEW

Dynamic Random Access Memory

(DRAM) devices are used in a wide range of

electronics applications. Although they are produced in

many sizes and sold in a variety of packages, their

overall operation is essentially the same. DRAMs are

designed for the sole purpose of storing data. The only

valid operations on a memory device are reading the

data stored in the device, writing (or storing) data in

the device, and refreshing the data periodically. To

improve efficiency and speed, a number of methods

for reading and writing the memory have been

developed.

DRAMs evolved from the earliest

1-kilobit (Kb) generation to the recent 1-gigabit (Gb)

generation through advances in both semiconductor

process and circuit design technology. Tremendous

advances in process technology have dramatically

reduced feature size,permitting ever higher levels of

integration.These increases in integration have been

accompanied by major improvements in component

yield to ensure that overall process solutions remain

cost-effective and competiti-ve.Technology

improvements, however, are not limited to

semiconductor processing.Many of the advances in

proc-ess technology have been accompanied or

enabled by advances in circuit design technology. In

most cases, advances in one have enabled advances in

the other.

B. DRAM OPERATION

DRAM chips are large, rectangular arrays of memory

cells with support logic that is used for reading and

writing data in the arrays, and refresh circuitry to

maintain the integrity of stored data The gates of the

DRAM cells are tied to the row decoder, and the bit-

line pairs are connected to the sense amplifier, as

shown in Fig. 1 [14].

B. i. Memory Arrays

Memory arrays are arranged in rows and columns

of memory cells called wordlines and bit lines,

respectively.Each memory cell has a unique location or

address defined by the intersection of a row and a

column.

B. ii. Memory Cells

A DRAM memory cell is a capacitor that is

charged to produce a 1 or a 0. Over the years, several

different structures have been used to create the

memory cells on a chip. In today's technologies,

trenches filled with dielectric material are used to

create the capacitive storage element of the memory

cell.

B. iii. Support Circuitry

The memory chip's support circuitry allows the

user to read the data stored in the memory's cells, write

to the memory cells, and refresh memory cells. This

circuitry generally includes:

• Sense amplifiers which is used to amplify the signal

or charge detected on a memory cell. Sense amplifier

is a pair of cross connected inverters.

• Address logic to select rows and columns. •Row

Address Select (RAS) and Column address Select

(CAS) logic to latch and resolve the row and column

addresses and to initiate and terminate read and write

operations. Using RAS and CAS we can select a

particular transistor.

Fig. 1. Simplified DRAM diagram.

C.ROW DECODER

Decoders address a specific cell in the memory

cell array. Row decoders are used to select a

particular row of cells in the memory array.

Decoders can be implemented using simple logic

gates.In the DRAM circuit (fig.1.) Gates of

transistors are tied to the row decoder.Fig.2.shows

row decoder circ-uit schematic diagram using

nand, nor (universal gates) and not gates in s-edit.

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Fig.2. Row decoder circuit schematic.

D.SENSE AMPLIFIER

The gates of the DRAM cells are tied to the row

decoder, and the bit-line pairs are connected to the

sense amplifier, as shown in fig.1 [14].A sense

amplifier is composed of a pair of cross-connected

inverters between the bit lines. When the address and

Row Access Signal (RAS) instruction are loaded to the

device, each row of the selected cells is active. In this

operation, the data stored in the cells of the selected

row address are amplified and stored again by the

sense amplifiers.This operation of an RAS instruction

to read or write is like the DRAM refresh operation,

which is activated periodically to store the cell data.

When the address and Column Access Signal (CAS)

instruction are transferred, the selected column cells of

the activated row cells are accessed. Through these

operations, the desired data can be read or written via

the Din or Dout pin.The bit-line pairs are connected in

parallel to the sense amplifier to reduce the bit-line

coupling noise. This array archit-ecture is called the

folded bit-line array. This array usually has a small

feature size of 8F2 (F: feature size),and has proven to

be the most reliable design. Another array

scheme called the open bit-line array[15], [16]has

smaller feature sizes (6F2 or 4F2) than the folded bit

line. This scheme has high density and cell efficiency,

and is also used when reducing the number of word

lines to ease the impact of a bit-line interference noise

on DRAM scaling. But there is no difference in

operating the DRAM cells between the folded bit line

and open bit-line architecture. Therefore, the folded

bit-line array architecture is used in this paper for

better understanding.

Fig 3 shows sense amplifier circuit using n-mos and p-

mos field effect transistors.

Fig.3. Sense amplifier circuit schematic.

III. INERLEAVING TEST ALGORITHM

A.BASIC CONCEPT

When a test algorithm is implemented, different types

of data backgrounds are used and Fig. 4 shows

commonly used Data Backgrounds (DB), which are

listed below.

1) Solid: All cells are filled with “0.”

2) 1-Row Bar: Alternating between “0” and “1,” and

all cells are written in the row direction.

3) 1-Column Bar: Alternating between “0” and “1,”

and all cells are written in the column direction.

4) 2-Row Bar: Alternating between a pair of “0” and

“1,”and all cells are written in the row direction.

Fig.4.Commonly used data backgrounds.

International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 2 Issue 6, September 2014, ISSN No.: 2348 – 8190

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The concept of the proposed test algorithm is

shown in Fig.5.This simplified DRAM array is

composed of eight rows and one column, and is

implemented using a 2-Row Bar data background with

scrambling enabled. Cells of word lines 0, 1, 4, and 5

are stored as “0,” and cells of word lines2,3,6, and 7

are stored as “1”. When a word line is selected, the

selected cell data (Dk ) is transferred to the sense

amplifier through the bit lines or bit bar lines. The

sense amplifier then pulls the bit line or bit bar line to

the data level of the selected cell.

During the activated time of the word line k, the cell i

receive the stress that causes the subthreshold leakage-

current and Sk indicates the stress effect of each cell k,

Rt is the read time when the word line of cell k is

activated.During the read operation of the first word

line, the data stored as “0” is transferred to the bit On

the contrary, if Di = Dk, then Sk can be expressed as 0,

and Rt can be set depending on the screen condition of

the sub threshold leakage-current.Thus, it is necessary

to determine the appropriate read-time conditions

considering the quality level, test time, and

screenability.

Fig.5. Concept of interleaving test algorithm.

IV. SIMULATION RESULTS DRAM circuit schematic is designed in s-edit

and simulated to obtain output waveforms which can

be viewed in w-edit. When we simulate the row

decoder circuit (fig.2.) waveforms are obtained as

shown in fig.6.

Sense amplifier is not only an amplifier but a positive

feedback device that quickly pushes the readout

voltage to 1 or 0.The sense amplifier circuit (fig.3.)

schematic is designed in s-edit and simulated to obtain

output waveforms in w-edit which is shown in fig.7.

Fig.6. Input and output waveforms of row decoder in

w-edit.

Fig.7.Input and output waveforms of sense amplifier

circuit.

The DRAM circuit and its output waveforms

(when enable line of sense amplifier circuit is

high) is shown in fig.8. and fig.9.Sense amplifier

circuit (fig.3.) will properly work only when

enable is high.

International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 2 Issue 6, September 2014, ISSN No.: 2348 – 8190

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Fig.8. DRAM circuit schematic in s-edit

International Journal of Advanced Engineering Research and Technology (IJAERT) Volume 2 Issue 6, September 2014, ISSN No.: 2348 – 8190

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Fig.9. Output waveforms of DRAM circuit using Tanner13.0.

Table.1.Computation of parameters

Interleaving algorithm requires separate circuits for

different data backgrounds.If we go for functional

algorithm different data backgrounds can be

implemented in a single circuit. Some circuit level

modifications in sense amplifier circuitry help to reduce

power upto 20% as compared to above method.

When the enable is high the DRAM circuit

consumes an average power of 37.22 µw and static

power of 14.53µw. Different parameters such as power,

area, power delay product,energy delay product and

static current are computed as shown in table.1.The

DRAM circuit has a total area of 950 µm².

V. CONCLUSION Various algorithms have been proposed to detect

faults in DRAMS. Interleaving test algorithm has good

screen coverage compared to other algorithms. As a

result of the experiment, we find that the interleaving

test algorithm has an average power consumption of

37.22µw and static power of 14.53mw. This test

algorithm can differ depending on the DRAM cell array,

PARAMETERS

INTERLEAVING TEST

Average power

37.22 µw

Static power

14.53 mw

Static current

8.072 mA

Power Delay product

0.581 µws

Energy Delay Product

23.248 pws²

Total area of transistors

950 µm²

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design and data backgrounds. In case of interleaving test

algorithm it is difficult to use different circuits for

separate data backgrounds. This drawback can be

overcome if we use functional algorithm.

REFERENCES [1] International Technology Roadmap for

Semiconductors. (2010) [Online].

Available:http://www.itrs.net/Links/2010ITRS/Home20

10.htm.

[2] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-

Meimand, “Leakage current mechanism and leakage

reduction techniques in deep sub micrometer CMOS

circuits,” Proc. IEEE, vol. 9, no. 2, pp. 305–327,Feb.

2003.

[3] N. Yamauchi, K. Kato, and T. Wada, “Channel edge

doping (CED)

method for reducing the short-channel effect,” Proc.

IEEE Electron Device Lett., vol. 4, no. 11, pp. 406–408,

Nov. 1983.

[4] M. F. Zakaria, Z. A. Kassim, M. P.-L. Ooi, and S.

Demidenko, “Reducing burn-in time through high-

voltage stress test and Weibull statistical analysis,” Proc.

IEEE Design Test Comput., vol. 23, no. 2, pp. 88–98,

Mar.-Apr. 2006.

[5] M. Meterelliyoz, H. Mahmoodi,and K. Roy, “A

leakage control system for thermal stability during burn-

in test,” in Proc. Int. Test Conf.,Nov. 2005, pp. 991–

1000.

[6] C. Minki, S. Nikhil, R. Arijit, and M. Saibal,

“Optimization of burn in test for many-core processors

through adaptive spatiotemporal power migration,” in

Proc. Int. Test Conf., Nov. 2010, pp. 1–9.

[7] M.C.-T. Chao, Y. Hao-Yu, H. Rei-Fu, L. Shih-Chin,

and C. Ching-Yu,“Fault models for embedded-DRAM

macros,” in Proc. Design Autom.Conf., Jul. 2009, pp.

714–719.

[8] T. Po-Chang, W. Sying-Jyan, and C. Feng-Ming,

“FSM-based programmable

memory BIST with macro command,” in Proc. IEEE

Int.Workshop Memory Technol., Aug. 2005, pp. 72–77.

[9] H. Chih-Tsun, H. Jing-Reng, W. Chi-Feng, W.

Cheng-Wen, and C. Tsin-Yuan, “A programmable BIST

core for embedded DRAM,”=IEEE Design Test

Comput., vol. 16, no. 1, pp. 59–70, Jan.–Mar. 1999.

[10] A. Pavlov, M. Azimane, J. P. De Gyvez, and M.

Sachdev, “Word line pulsing technique for stability fault

detection in SRAM cells,” in Proc. Int. Test Conf., Nov.

2005, pp. 825–835.

[11] L. Dilillo and B. M. Al-Hashimi, “March CRF: An

efficient test for complex read faults in SRAM

memories,” in Proc. Design Diag. Electron. Circuits

Syst., Apr. 2007, pp. 1–6.

[12] C.-M. Chang, M. C.-T. Chao, H. Rei-Fu, and C.

Ding-Yuan, “Testing methodology of embedded

DRAMs,” in Proc. Int. Test Conf., Oct. 2008,pp. 1–9.

[13] R. L. Franch, S. H. Dhong, and R. E. Scheuerlein,

“A large VDS data retention test pattern for DRAM’s,”

Proc. IEEE J. Solid, State Circuits,vol. 27, no. 8, pp.

1214–1217, Aug. 1992.

[14]Memory,Integr.CircuitEng. Corporation, Phoenix,

AZ, USA, 1997.

[15] D. Takashima, S. Watanabe, H. Nakano, Y.

Oowaki, and K. Ohuchi, “Open/folded bit-line

arrangement for ultra-high-density DRAM’s,”Proc.

IEEE J. Solid, State Circuits, vol. 29, no. 4, pp. 539–

542,Apr. 1994.

[16] T. Sekiguchi, K. Itoh, T. Takahashi, M.

Sugaya,H.Fujisawa,M.Nakamura,K.Kajigaya, and K.

Kimura, “A low impe-dance open-bit line array for multi

gigabit DRAM,” Proc. IEEE J. Solid, State Circuits, vol.

37,no. 4, pp. 487–498, Apr. 2002.

[17]Interleaving Test Algorithm for Subthreshold

Leakage-Current Defects in

DRAM Considering the Equal Bit Line Stress Hyoyoung

Shin,Youngkyu Park, Gihwa Lee, Jungsik Park, and

Sungho Kang, Member, IEEE, IEEE transactions on

very large scale integration (vlsi) systems, vol. 22, no. 4,

april 2014.