Draft ass1 pe q2

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design the ipad charger

Transcript of Draft ass1 pe q2

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Po = 10W Vs = 240Vrms F = 50Hz Fswitching = 20kHz Vo = 5.1 VDC, 5% (+ 2%) voltage ripple factor Io = 2.1A Repeat the design for <3% ( + 2%) voltage ripple factor THE IDEA VAC INPUT --- RECTIFIER --- BUCK -----VO, Io, Po RECTIFIER CIRCUIT

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RECTIFIER PARAMETER

THE CALCULATION - REFER PAGE 123 DANIEL W HART

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RECTIFIER WAVEFORM Vs Is Ic + Ir Vo

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BUCK CIRCUIT

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BUCK PARAMETER

THE BUCK CALCULATION VO = 5.1, IO = 2.1, FSWITCHING = 2O kHz, VSMAX = 339.411V, RIPPLE V = 2% VO = DVS Thus, D = 0.015 IO = IR = VO/R R = 2.43 LMIN = (1 – D) R / 2F LMIN = 0.0598mH L = 10LMIN L = 0.598Mh ΔVO = (1 – D) / 8LCF2 C = 25.7368uF

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BUCK WAVEFORM (RALF VIEW) – the Vo decreased from Vm = 339.411V to 5.1V

Vs Vmosfet Gate signal Io Vo

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BUCK WAVEFORM (STEADY STATE; DETAIL VIEW) Vs Vmosfet Gate signal; D = 0.015 FROM THE WAVEFORM IO = 2.1A VO = 5.08V RIPPLE, ΔVO = (5.11 – 5.05) / 5.08 = 1.2%

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AFTER COMBINE THE CIRCUIT

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THE WAVEFORM AFTER COMBINATION (RECTIFIER -- BUCK --- 2A, 5V, ripple 6%, 10W)

Vo(rec) = Vs(buck) Vmosfet Gate signal SINCE THE DESIGN IS TO GET THE Io = 2.1A, Vo = 5.1 VDC, 5 %( +- 2%) ripple and Po = 10W THUS, THIS OUTPUT IS ACCEPTABLE Io = 2A VO = 4.95V Vripple ͌ (5.1-4.8)/4.95 = 6% Po = IoVo = 9.9W

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REDUCE THE RIPPLE BY ADDING THE CAPASITOR FILTER

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REDUCE THE RIPPLE BY ADDING THE CAPASITOR FILTER AND THE OUTPUT WAVEFORM AS BELOW

Vo(rec) = Vs(buck) Vmosfet Gate signal SINCE THE DESIGN IS TO GET THE Io = 2.1A, Vo = 5.1 VDC, < 3 %( +- 2%) ripple and Po = 10W THUS, THIS OUTPUT IS ACCEPTABLE Io = 2A VO = 5.04V Vripple ͌ (5.11-4.95)/5.04 = 3% Po = IoVo = 10.1W