Dr Stein Introduction to Microelectronics

7/27/2019 Dr Stein Introduction to Microelectronics

1/57

Chemical Processing for

Microelectronics

CHEE 1131


2/57

Introduction

1. Moores Law - a predictor of transistor packing density inSilicon integrated circuits.

2. Building semiconductor devices.


3/57

The Incredible Shrinking Transistor1947 1997

1 cm 60 nm

2007

FUTURE?


4/57

Moores Law

Moores Law has been the economic driving force behind the

semiconductor industry for the past ~40 years. It will continue to be a driving force in the future, but for how long?

The number of transistors in an integrated circuit (e.g., Intel micro-processors)continues to increase as the size of each transistor shrinks. Check out Intels

website.


5/57

Scaling Enabler of Moores Law*

*cf. Robert Doering, Texas Instruments

500

350

250

180

130

95 97 99 01 04 07 10 13 16

90

65

45

32

22

95 97 99 01 04 07 10 13 16

FeatureSize[nm]

Year of Production

ITRS Gate Length

9

13

* For Speed, Low-Cost,

Low-Power, etc.

ITRS Lithography Half-Pitch (DRAM)


6/57

Moores Law

My first portable computer!IBM compatibleApprox 30 lbs

128 KB; Two 5.25"

My current laptop Approx 3 lbs4 GB memory; 150 GB hard drive

Compaq Portable (1980s)


7/57

What Are Semiconductor Devices?

Solid-state electronic components based on semiconducting

materials. Usually inorganic.

Discrete (single) devices Diodes

Transistors

light-emitting diodes (LED) lasers

Integrated devices (many devices on the same substrate) silicon integrated circuit (SIC) consists of millions of transistors,

capacitors, resistors. gallium arsenide IC

optoelectronic circuits (lasers, detectors, modulation circuitry all onsame chip)


8/57

Semiconductor Manufacturing

1. Grow large (many kilogram) crystals

2. Slice them up into wafers (i.e. substrates) and polish them

3. Deposit layers on the polished substrate

4. Define patterns on top of the layers by photolithography(also called optical lithography, projection lithography)

5. Transfer the pattern to the film and sometimes the wafer byplasma etching.

6. Repeat steps 3-5 many times (20+)

7. Slice the wafer into devices (IC, laser, etc.)8. Package the devices (put it in a case, attach wires, etc.)


9/57

Integrated Devices


10/57

Environment

UH Nanofab (class 10/100 clean room).

10

Class Particles per Cubic Foot

ParticleSize:

0.1m 0.2m 0.3m 0.5m

10 350 75 3 1

100 NA 750 30 101000 NA NA 300 100

Lithography Bay Plasma Etching Wet Chemistry

Reference:http://nanofab.uh.edu


11/57

Unit Operations

Many unit operations in semiconductor fabrication

Today overview of the following steps: Silicon growth

Ion implantation (silicon doping)

Optical lithography

Plasma Etching

11


12/57

c-Silicon Silicon is used in many types of semiconductor devices (FETs, etc.).

Usually single crystal is needed. Usually silicon is doped to increase the density of charge carriers (electrons, holes)

at room temperature.

Intrinsic and doped Si.

Doped Si is n-type, 1021/m3.

12


13/57

Silicon Growth

1. Purification of silica sand to produce 98% pure silicon: Reduce with

carbon (coke, wood chips).

13

Metallurgical grade silicon (MGS)

2( ) ( ) ( ) ( ) ( )SiC s SiO s Si s SiO g CO g+ + +


14/57

Silicon Growth

2. Convert MGS to trichlorosilane: Pulverize Si, react with HCl in fluidized

bed:

14

3 2( ) 3 ( ) ( ) ( )Si s HCl g SiHCl g H g+ +

31.8C boiling pt

Main impurities in reactant are Fe, B, P. So impurities in product are

Low bp (12.5 C)

High bp (315, 76, 160C)

* Purify trichlorosilane with distillation


15/57

Silicon Growth

3. Convert back to solid silicon by decomposition of silane:

15

3 2( ) ( ) ( ) 3 ( )SiHCl g H g Si s HCl g+ +

Electronic Grade Si (EGS)Polycrystalline! (known as Polysilicon)Purity of 99.9999999%


16/57

16


17/57

Process Flow Diagram

17

http://www.greenrhinoenergy.com/solar/technologies/pv_manufacturing.php


18/57

Silicon Growth

4. Convert polysilicon to c-Si with czochralski (CZ) crystal growth.

18

Fill silica crucible (SiO2) with undopedEGS

Add dopant: Pieces of doped of silicon (for

low doping concentrations); Elemental dopants (high doping

concentrations). Heat crucible in vacuum to 1420 C to

melt poly Si. Add single-crystal Si seed of known

crystal orientation. This directs the

growth of Si into a single crystal solid.


19/57

Silicon Growth

4. Convert polysilicon to c-Si with Czochralski (CZ) crystal growth.

19

After seeding, quickly draw a thinneck. This suppresses defects due tolarge temperature gradient betweenmelt and solid.

After neck forms, lower the pullingrate. Lower pulling rates give largercrystal diameters.

Crystal length depends on yieldstrength of silicon neck, crucible size.


20/57

Silicon Growth

Common challenges: Contamination.

Silica crucible is slightly dissolved, generates oxygen. CZ-Si has around 10 ppma oxygen (partsper million atoms)

Silica crucible has impurities like B, Na, Al. These can be incorporated into the CZ-Si.

Silica crucible is not very strong. Reinforced by graphite cup. Reaction between crucible andcup generates CO, this leads to carbon contamination in CZ-Si (1016/cm3).

Time and energy consumption ($$$$$).

For 200 mm wafers, pulling time is 30 h. Heating and cooling time takes another 30 h.

Slow, high temperature, batch process.

20


21/57

21


22/57

Ion Implantation

More common approach for building junctions (doping

silicon). Used since the 1980s. Ionized impurity atoms are accelerated through an

electrostatic field, strike the surface of the wafer. Typicalenergies of 5-200 keV.

Dose controls implant concentration (measure the ioncurrent).

Electrostatic field controls penetration depth (junction depth).

22


23/57

Ion Implantation

Advantages: Low temp, good control and reproducibility,

flexible. Can use photoresist as implant mask. Disadvantages: Throughput, capital cost ($2MM each), and

damage to the semiconductor lattice.

23


24/57

Ion Implantation

24

1. Ion Source

2. Mass Spectrometer

3. High-Voltage Accelerator (Up to 5 MeV)

4. Scanning System

5. Target Chamber

Includes Faradaycup for dosemeasurement


25/57

Optical Lithography

Lithography: Lithos (stone), graphos (writing)

Critical step topattern microscale or nanoscale devices.

Replicate a master pattern.

25


26/57


27/57

Optical Lithography

Pattern transfer (to build a device).

27


28/57

Optical Lithography

Initial template is called a mask.

Typical mask is fused silica with chromium patterns.

Quartz = UV transparent, Chrome = opaque.

28

http://www.phonon.com


29/57

Optical Lithography

Different ways to transfer the mask pattern:

1. Contact printing (press mask onto the resist-coated wafer). 1960s.Damage to the mask was a problem.

2. Proximity printing (mask near the wafer). No damage to mask, butlots of blur.

3. Projection lithography (image projected with lenses). 1970s. Nodamage, minimal blur.

Projection lithography is the current industry standard. Stepper design.

Systems have evolved to meet the demands of Moores Law.

29


30/57

Optical Lithography

30


31/57

Optical Lithography

Light sources: Hg lamp (80s to early 90s):

g-line: 436 nm

h-line: 405 nm

i-line: 365 nm Excimer lasers (90s to Now):

Krypton fluoride: 248 nm

Argon fluoride: 193 nm

Future?

31

Decrease(historically) Increase

(recent)


32/57

Lithography

Light sources: 157 nm was next. However, the industry could not develop

appropriate ``glass for optics and masks.

In general, when you move to shorter wavelengths you encounterproblems with transparency.

Next-generation light sources: Extreme ultraviolet: 13.5 nm. Reflection optics.

Electrons: 0.62 . Usually mask-less.

Ions: 0.12 . Usually mask-less.

Hard X-rays: < 4 nm. Masks and optics OK. Hard to develop resists.

32


33/57

Projection Lithography

Resolution limit = Rmin = k1 */NA = wavelength of light source;

k1 = process parameter;

NA = numerical aperture of your optics.

For academic lithography: = g, h, and i-line. Rmin 1- 2 m.

NA < 1.

For industrial lithography:

= 193 nm. Rmin 20-40 nm.

NA 0.9-1.3.

33


34/57

Tricks to Enhance Resolution

1. New optics

2. New light sources

3. New technologies

34

These are techniques used in industrial manufacturing, not academic facilities.


35/57

New Optics

193 nm light. Optics immersed in water

(n=1.33). Similar to opticalmicroscopes!

Single exposure resolves 40

nm (half-pitch). (k1 0.3) Double exposure hits 32 nm.

35

Source: IBM


36/57

New Light Source

=13.5 nm. Soft X-Rays. Called EUV. NA 0.25-0.45.

Reflective optics and masks

Vacuum operation

Single exposure, so might be

simpler than multiple patterning. Very expensive tools (ca. $80 MM)

36

Decrease(historically)


37/57

EUV Lithography: Reflective Mask

37

http://www.photomask.com/products/euv-masks

40-50 alternating layers of silicon and molybdenum,Period /2.Low thermal expansion substrate.

Absorber/buffer

13.5 nm


38/57

Academic Instrumentation

38


39/57

Lithography Contact aligner (academic facility).

Broadband light (436, 405, 365 nm). Resolution limit of approximately 1-2 m.

39

Reference:

http://nanofab.uh.edu

What you need: Photomask, resist and developer.

mask

substrate joystick

microscope

timer

hv


40/57

Contact/Proximity Printing

40

Reference:

http://www.cleanroom.byu.edu

Instrumentation:


41/57

Contact/Proximity Lithography

41

Reference:

http://www.cleanroom.byu.edu

Operation:

Alignment is criticalto build a multilayerdevice.

Wafer must belevel, or your imagewill look terrible.This means yoursubstrate should be

free of dust.


42/57

Process Flow Diagram for

PhotolithographyValid for academic or industrial lithography

42


43/57

43

Depends on resistchemistry.

HMDS = hexamethyldisilizane


44/57

Materials Overview

Common positive-tone, negative-tone resistmaterials for academia and industry.

44


45/57

Positive-Tone DQN Resist

45


46/57


Diazo compounds are of the general structure:

Solvent removed by baking after spin-on

Matrix : PAC = 1:1

Expose to UV light (g, h, i-line). Matrix is not changed, butPAC is:

46

+

== NNR


47/57


47

R =

Developer


48/57


Developer is a basic solution (such as TMAH dissolved in

water, or KOH dissolved in water). Carboxylic acid dissolves, but un-exposed DQ does not.

Typically, you post-bake the resist to drive off volatilecompounds and make the resist better for plasma etching.

The DQN chemistry is very popular for academic lithography.For example, S1813 by MicroChem.

48


49/57

Chemically-Amplified Resists

Industry standard. Invented at IBM by Willson, Ito, and Frechet.

Can be positive or negative tone. Positive tone is standard in industry.

49


50/57

Chemically-Amplified Resists

Advantages: Really fast exposures. (Very sensitive to radiation.)

Tons of choices for resin and catalyst, so can be used withmany different types of radiation sources.

Disadvantages: Resolution will ultimately be limited by acid catalyst

diffusion.

Sensitivity and resolution are inversely proportional:

50


51/57

Plasma Etching

Critical pattern transfer unit operation.

51


52/57

Plasma Etching

52

Important classifications:Isotropic vs. anisotropic


53/57

Plasma Basics

53

A partially ionized gas. Equal number of positive charges (e.g.

positive ions) and negative charges (e.g. electrons, negative ions).


54/57

Plasma Overview

Types of processes:

Ion milling: Uses A+ (noble gas ions like Ar+) to physicallysputter material.

Ion etching: Radicals and ions react with sample. Volatileproducts.

54* Means an excited state with energy much higher than ground state

(produces radicals)


55/57

Plasma Reactor1. Two parallel plate electrodes attached to power supply (DC or RF, DC in cartoon below).

2. Gas initially acts as an insulator.

3. Connect high-voltage source to start the plasma. Electric field in the reactor exceeds thebreakdown field of the gas. High voltage arc will flash between the two electrodes, create alarge number of ions and free electrons.

4. Electrons are accelerated toward the anode (fast), ions move to cathode (slow).

5. Ions strike the sample at the cathode, sputters and/or etches material. Volatile products.

55

+

++

electron Ion

Cathode Anode

V R I

Gas breakdown by avalanche ionization


56/57

Plasma Etching at UH Nanofab

56


57/57

Nano Cougar

Dr Stein Introduction to Microelectronics

Documents

Transcript of Dr Stein Introduction to Microelectronics