Dr. Panos Nasiopoulos Chapter 4courses.ece.ubc.ca/.../Digital_Logic_Design_ch4_2009.pdf · 2009. 9....
32
Dr. Panos Nasiopoulos Combinational Logic 1 Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Chapter 4
Transcript of Dr. Panos Nasiopoulos Chapter 4courses.ece.ubc.ca/.../Digital_Logic_Design_ch4_2009.pdf · 2009. 9....
Dr. Panos Nasiopoulos
Combinational Logic 1
Combinational:Circuitswithlogicgateswhoseoutputsdependonthepresentcombinationoftheinputs.
Sequential:Inaddition,theyincludestorageelements
Chapter4
Dr. Panos Nasiopoulos
Combinational Logic 2
1. Determinethenumberofinputsandoutputs2. Assignsymbols3. Derivethetruthtable4. Obtainsimplifiedfunctionsforeachoutput5. Drawthelogicdiagram
ADDERSThemostbasicarithmeticoperationostheadditionoftwobinarydigits.
DesignProcedure
Dr. Panos Nasiopoulos
Combinational Logic 3
Half-Adder- Needs2inputsand2outputs.- x,y:inputs;S,Coutputs.
DesignProcedure
X Y C S
Dr. Panos Nasiopoulos
Combinational Logic 4
• FullAdderConsistsof3inputsandtwooutputs: • x,y:twosignificantbits• z:carry
• UseKmapsforthetwooutputs
x y z0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Dr. Panos Nasiopoulos
Combinational Logic 5
• FullAdder• S=• C=xy+xz+yz
• S=z⊕(x⊕y)• C=m3+m5+m6+m7=
Dr. Panos Nasiopoulos
Combinational Logic 6
CodeConversion
• ConvertcodeAtoB:
• BCD Excess-3(selfcomplementing)
? A B BCD Excess-3 code
A B C D w x y z
Dr. Panos Nasiopoulos
Combinational Logic 7
A B C D w x y z0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
Dr. Panos Nasiopoulos
Combinational Logic 8
• z=• y=• x=
• w=
Dr. Panos Nasiopoulos
Combinational Logic 9
• Given:alogicdiagram• WewanttoderivetheoutputBooleanfunction(s)• Procedure:
AnalysisProcedure
Dr. Panos Nasiopoulos
Combinational Logic 10
T2=ABCT1=A+B+CF2=AB+AC+BCT3=F2‘T1F1=T3+T2
F1=
AnalysisProcedure
Dr. Panos Nasiopoulos
Combinational Logic 11
TRUTHTABLE:– Determinethenumberofinputvariables– Labeltheoutputs– Obtainthetruthtable
AnalysisProcedure
A B C F2 F’2 T1 T2 T3 F1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
T2 = ABC T1 = A+B+C F2 = AB + AC + BC T3 = F2 ‘T1 F1 = T3 + T2
Dr. Panos Nasiopoulos
Combinational Logic 12
BinaryParallelAdder
• TwobinarynumbersofnbitscanbeaddedbyusingFAs.
• Thesumoftwonbitbinarynumbers,AandB,canbegeneratedinserialorinparallel.
• Serial:
Dr. Panos Nasiopoulos
Combinational Logic 13
BinaryParallelAdder
• Paralleladder: – UsesnFAs.
Dr. Panos Nasiopoulos
Combinational Logic 14
Example:BCDtoexcess3codeconverter
• Recallthatweneeded11gatesforthisdesign.
BCD
input
1
Excess-3 output
IC FA
Dr. Panos Nasiopoulos
Combinational Logic 15
CarryPropagation
• Recallthatforthedesignoftheparalleladdertowork,thesignalmustpropagatethroughthegatesbeforethecorrectoutputsumisavailable.
• Totalpropagationtime=propagationdelayofatypicalgatexthenumberofgates
• Let’slookatS3.– InputsA3andB3areavailableimmediately.– However,C3isavailableonlyafterC2isavailable.– C2hastowaitforC1,etc.
• ThenumberofgatelevelsforthecarrytopropagateisfoundfromtheFAcircuit
C4
2 gates
Dr. Panos Nasiopoulos
Combinational Logic 16
Dr. Panos Nasiopoulos
Combinational Logic 17
• Carrylookahead:
Pi=Gi=
Si=
Gi:calledacarrygenerate;itproducesacarryof1whenbothAiandBiare1,regardlessoftheinputcarryCi.
Pi:calledcarrypropagatebecauseitisthetermassociatedwiththepropagationofthecarryfromCitoCi+1.
C0=inputcarryC1=C2=C3=
Dr. Panos Nasiopoulos
Combinational Logic 18
C0=inputcarryC1=C2=C3=
Dr. Panos Nasiopoulos
Combinational Logic 19
A4-bitadderusingacarrylookaheadscheme:
• Notethatalloutputcarriesaregeneratedafteradelayoftwolevelsofgates.– S1toS3haveequalpropagationdelaytimes
Dr. Panos Nasiopoulos
Combinational Logic 20
B3 A3 B2 A2 B1 A1 B0 A0
BinarySubtractor
• Recallthatthesubtractionoftwonumbers(A-B)isdonebytaking2’scomplementofthe–venumberandthenweaddthe2numbers.
• 2’scomplementis1’scomplement+1
• Wewanttofigureouthowtocomplementthe–venumber(e.g.,B).
Dr. Panos Nasiopoulos
Combinational Logic 21
Overflow
• Twon-bitnumbersaddedresultinn+1– Itmayresultinoverflow
• Example(4-bits)
• Notethatoverflowoccurswhen
• So,ifwewanttodetecttheoverflow,wecanuse
Dr. Panos Nasiopoulos
Combinational Logic 22
DesignofaBCDAdder• AddtwoBCDnumbers;showoutputinBCDformat
– IfweaddtwoBCDnumbers,themaximumoutputwillbe:9+9+carry(if1)=19decimal.
– UsingFAs,wegetbinaryrepresentation.– WeMUSTconvertittoBCDusingtwoBCDs
Dr. Panos Nasiopoulos
Combinational Logic 23
DesignofaBCDAdder
Dr. Panos Nasiopoulos
Combinational Logic 24
Decoders
• Abinarycodeofnbitscanrepresent2ndistinctcombinations(orunique“cases”).
• Decoder:acombinationalcircuitthatconvertsnbinarylinesinto2nuniqueoutputlines
• Example:a3-to-8linedecoder– 3inputsaredecodedto8outputs–representingthe8minterms
Dr. Panos Nasiopoulos
Combinational Logic 25
Decoders
• Truthtableforadecoder:
• DecoderwithNANDgates:
Inputs Outputs
x y z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Dr. Panos Nasiopoulos
Combinational Logic 26
Decoders
• DecoderwithNANDgatesandenable:
• Decoderswithenablecanbeconnectedtogethertoformlargerdecoders.
• Example:Designa4-to-16decoder
Dr. Panos Nasiopoulos
Combinational Logic 27
Decoders:ImplementingBooleanfunctions
ImplementaFAusingadecoder:• Recallthatthefulladderhas3inputsandtwooutputs:
– S(x,y,z)=Σ(1,2,4,7)– C(x,y,z)=Σ(3,5,6,7)
Dr. Panos Nasiopoulos
Combinational Logic 28
Encoders
• Inverseoperationofadecoder – Ithas2ninputsandgeneratesncodewords
• Example:Designa4x2encoder
• Problems:
D0 D1 D2 D3 x yENCODER
Dr. Panos Nasiopoulos
Combinational Logic 29
Design:Priorityencoder
D0 D1 D2 D3 x y
0 0
0 1
1 0
1 1
Dr. Panos Nasiopoulos
Combinational Logic 30
Multiplexers• Amultiplexerselectsoneofmanyinputsanddirectsittotheoutput.
• Theselectionmaybecontrolledby“selectlines”• Normally2nlines:nselectlines
Example:2x1multiplexer
Howcanwedesignthis?Let’sconsidera4x1multiplexer
• Usecodetodirectinput
Transmission line
ch1 ch2
chn
y
x out MUX
out MUX
Dr. Panos Nasiopoulos
Combinational Logic 31
Multiplexers
Dr. Panos Nasiopoulos
Combinational Logic 32
1
z
z
0
Z’
MultiplexersusedtoimplementBooleanfunctions
• Useamultiplexertoimplementthefollowingfunction:– F=x’y’z+x’yz’+xy’z+xyz
• DesignaFull-adderS(x,y,z)=Σ(1,2,4,7);C(x,y,z)=Σ(1,2,4,7)
x y z S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
