DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National...

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DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory

Transcript of DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National...

Page 1: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

DOM Main BoardRev 3/Rev 4

Status

December 2, 2003

Gerald Przybylski

Lawrence Berkeley National Laboratory

Page 2: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

Major Rev 3 Goals

• Booting to –50°C, or colder

• Memory Interface Layout• PMT Waveform integrity:

Ringing, Clamping, Baseline Bounce

• Component Substitutions

Deferred:-- Front-End Pulser -- Local Coincidence

Page 3: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

We’re

On Track

Page 4: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

Rev 3 First Items (4)

• Boot at -70°C, measured by on-board sensor: from Flash and from Configuration Memory

• Memory test OK at -50°C, at 40 MHz, long term...• Good PMT waveforms. Good clamping. No bounce.• Perfect MB – to – Delay board fit• Power Under 3W (at CPU @ 80MHz & Memory @ 40MHz)

• 2 boards: -60°C, 160 MHz CPU, 125 MHz Mem• RAP at -60°C

Page 5: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

Rev 3 Problems• PC Fab House Testing Failure

Shorts on Top Layer: 2 pcs. 4 shorts

• Two New Schematic Errors (Mentor/EDIF)

• Loading/Bill-of-Materials errors• Two Footprint errors (QFP-100, Oscillator)

• Minor, but Unsightly Quirks in Front-End Pulser Waveform - product/brand dependency

- Suppressible

Page 6: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

Rev 4 Changes

• Component Value Changes -- optimizations -- schematic corrections

• Power Supply Load Balancing (One trace, one resistor)

• On-Board LED Pulser Power (Several parts)

• Component Substitutions for Reliability,- A few; mainly inductors… 99% finalized- Availability issues

• Front End Pulser Corrections

• Layout Design Rule Optimizations

Page 7: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

Open Issues• Chevette vs. Buick vs. Cadillac quality PCBs (Class 1, 2, 3)

• Verification (Qualtest) Split between LBNL and UWe.g. Thermal Cycling: How many? What range?e.g. Vibration Testing: What acceleration? Where?e.g. Humidity: Will UW measure RH at -40°C? at -70°C?? in purged and sealed DOM…(VPH2O 0.002mm Hg@-70°C vs. 0.1mm Hg@-40°C vs. 24mm Hg@25°C)>> No problem, says RI…<<

Design for EMS, when mature (what measure of maturity?)

Page 8: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

Late Breaking News

• Receiving & Testing 12 More Rev 3 Boards- 6 Evenstar boards, 6 Data Circuits boards- Looking good so far; Many loading changes in batch

• Rev 4 Schematic Updates In Progress - 90% of schematic pages to date- Few additional Components.- Working from Detailed List; Configuration Control

Page 9: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

Rev 4 schedule Ongoing test stand parallel development (STF)

-- To be available 1/23 -- Move to room 50a-6105 11/21Modification Review/approval of Spreadsheet and File

III11/25 Design rules Review 12/15 - 12/19 “line-by-line” Reviews 12/24 - 1/6 Fab 1/7 - 1/20 Assembly 1/23 - 2/19 Acceptance Testing at LBNL (STF based) 2/20 First 20 cards to UW 2/23 - 5/21 integration at UW, verification testing at UW and

LBNL

Page 10: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

The End

Page 11: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

Changes Spreadsheet

Bob… you can change this link to point to your copy of the changes spreadsheet

Page 12: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

Digital Optical Module Block Diagram

FPGA

CPU

CPLDFlash Flash

PMT Power

SDRAM

SDRAM

ATWD

ATWD

fADC

DAC

Monitor& Control

LPF

LC

x16

x2

x0.25

FlasherBoard

Pulser

DACs & ADCs

Corning Frequency Ctl (was Toyocom)

4Mb 4Mb

16Mb

16Mb

+/-5V, 3.3V, 2.5V, 1.8V

64 Bytes

Trigger (2)ADC

Oscillator

20 MHz

40 MHzMUX

(n+1)

(n–1)

DOR

OB-LED

1 5

4 8

x 2.6 x 9

10b

10b

10b

10b

8b

32b

16b

8b

8b, 10b, 12b

DPRam

1 megabaud

DC-DC

ConfigurationDevice

8Mbit

Delay

Page 13: DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory.

DOMFPGABlock

Diagram

ATWD Readout Engine

Communications Engine

Control & Status Registers