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AMBA DMA Controller (with AXI memory interface) DMA Core Reference Guide Version 1.1 - January 2015 1 DMA Core Reference Guide 32-Bit/64-bit AXI modes

Transcript of DMA Core Reference Guide · interface from a FIFO buffer that connects to the DMA IP core module...

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DMA Core Reference

Guide

32-Bit/64-bit AXI modes

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CONTENTS

1 INTRODUCTION ............................................................................................................................. 7

1.1 EXISTING HARDWARE MODULE COMPATIBILITY ........................................................................... 7 1.2 DIRECT MEMORY ACCESS.......................................................................................................... 8

2 CONTEXT OF A TYPICAL SOFTWARE DRIVER & IP CORE ...................................................... 9

3 CORE OBJECTIVES ..................................................................................................................... 11

3.1 PRODUCT OBJECTIVE .............................................................................................................. 11 3.2 SOFTWARE DRIVER ................................................................................................................. 12

4 TOP AMBA DMA CONTROLLER BLOCK DIAGRAM ................................................................ 13

4.1 OVERVIEW .............................................................................................................................. 13 4.1.1 DMA Controller .................................................................................................................. 13

5 TOP LEVEL AMBA DMA CONTROLLER PIN-OUT .................................................................... 14

5.1 OVERVIEW .............................................................................................................................. 14 5.2 CONTROL BLOCK (PART 1 OF THE TOP-LEVEL CORE) ............................................................... 14 5.3 RX/TX BLOCK (PART 2 OF THE TOP-LEVEL CORE) ................................................................... 15

6 THE TOP-LEVEL PIN-OUT OF THE DMA CONTROLLER HARDWARE .................................. 16

7 DMA SPEED & THROUGH-PUT CAPABILITY ........................................................................... 22

7.1 INTRODUCTION ........................................................................................................................ 22 7.2 ISOLATED DMA HARDWARE MODELING .................................................................................... 22 7.3 ISOLATED DMA REAL-WORLD CONSIDERATIONS ...................................................................... 24

8 SYNTHESIS OPTIONS ................................................................................................................. 25

8.1 GLOBAL SYNTHESIS OPTIONS .................................................................................................. 25

9 RX DMA MECHANISM.................................................................................................................. 28

9.1 OVERVIEW .............................................................................................................................. 28 9.2 RX DESCRIPTOR ..................................................................................................................... 28 9.3 DEFINITIONS ............................................................................................................................ 30 9.4 FLOW ILLUSTRATION OF RECEIVE RX ENGINE (LANDSCAPE VIEW) ............................................. 32

10 TX DMA MECHANISM ............................................................................................................. 33

10.1 OVERVIEW .............................................................................................................................. 33 10.2 TX DESCRIPTOR...................................................................................................................... 33 10.3 DEFINITIONS ............................................................................................................................ 35 10.4 FLOW ILLUSTRATION OF TRANSMIT TX DMA CORE (LANDSCAPE VIEW) ..................................... 37

11 FIFO INTERFACE .................................................................................................................... 38

11.1 32-BIT MAC/SWITCH INTERFACE DATA STRUCTURE .............................................................. 38 11.2 64-BIT MAC/SWITCH INTERFACE DATA STRUCTURE .............................................................. 38 11.3 FIFO INTERFACE TRANSMIT OPERATION .................................................................................. 39 11.4 FIFO INTERFACE RECEIVE OPERATION .................................................................................... 41 11.5 FIFO INTERFACE MODULO DEFINITION ..................................................................................... 43

11.5.1 32-bit Usage .................................................................................................................. 43 11.5.2 64-bit Usage .................................................................................................................. 44

11.6 FRAME STATUS ....................................................................................................................... 44

12 EXPANSION IO-REGISTER INTERFACE ............................................................................... 46

12.1 OVERVIEW .............................................................................................................................. 46 12.2 REGISTER WRITE .................................................................................................................... 47

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12.3 REGISTER READ ...................................................................................................................... 47 12.4 AHB-LITE TIMEOUT FOR EXTERNAL REGISTER ACCESS ............................................................ 47

13 INTERRUPT CHANNELS ......................................................................................................... 48

13.1 OVERVIEW .............................................................................................................................. 48 13.2 INTERRUPT SOURCES .............................................................................................................. 48 13.3 INPUT DESIGN ......................................................................................................................... 51 13.4 ACKNOWLEDGEMENT OUTPUTS ................................................................................................ 51

14 REGISTER INTERFACE (CONTROL BLOCK) ....................................................................... 52

14.1 OVERVIEW .............................................................................................................................. 52 14.2 DMA CONTROLLER/STATUS REGISTERS .................................................................................. 53 14.3 TX_GLOBAL_CONTROL REGISTER ..................................................................................... 69 14.4 TX_STATUS REGISTER ......................................................................................................... 70 14.5 RX_GLOBAL_CONTROL REGISTER ..................................................................................... 71 14.6 RX_STATUS REGISTER ......................................................................................................... 72 14.7 ADDITIONAL INFORMATION ....................................................................................................... 72

15 REFERENCES .......................................................................................................................... 73

16 CONTACT ................................................................................................................................. 74

17 DOCUMENT HISTORY ............................................................................................................ 75

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About This Specification

This specification introduces the MorethanIP AMBA DMA Controller top-level architecture, design and general information about how a software driver would interface and operate the IP hardware

Intended Audience

This document is fully intended to be viewed and reference by MorethanIP/Nine Ways customers using the technology for larger designs and projects.

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List of Figures

Figure 1 - Context of the Linux Driver ..................................................................................................... 9 Figure 2 - Different scenarios of DMA Controller usage ....................................................................... 10 Figure 3 – Top Model AMBA DMA Controller Schematic ..................................................................... 13 Figure 4 - AHB-Lite Bus Interface for the IO-Register component of the DMA Controller Top Module 14 Figure 5 – AXI Bus Interface for the DMA Core component of the DMA Controller Top Module ......... 15 Figure 6 - Receive DMA Descriptor Entry ............................................................................................. 29 Figure 7 - Flow Chart Diagram of the RX Receive DMA Engine .......................................................... 32 Figure 8 - Transmit DMA Descriptor Entry ............................................................................................ 34 Figure 9 - Flow Chart Diagram of the TX DMA Engine ......................................................................... 37 Figure 10: FIFO Transmit Interface – Single Frame ............................................................................. 39 Figure 11: FIFO Transmit Interface - Frame Transfer with DMA Controller Pause .............................. 39 Figure 12: FIFO Transmit Interface - Four Back-to-Back Frames ........................................................ 40 Figure 13: FIFO Transmit Interface - Transfer with MAC/SWITCH Pause ........................................... 40 Figure 14: FIFO Transmit Interface - Errored Frame ............................................................................ 41 Figure 15: FIFO Receive Interface - Single Frame Transfer ................................................................ 42 Figure 16: FIFO Receive Interface - Transfer with DMA Controller Pause .......................................... 42 Figure 17: FIFO Receive Interface – Frame with Errors ....................................................................... 43 Figure 18: Register Write Timing Diagram ............................................................................................ 47 Figure 19: Register Read Timing Diagram ........................................................................................... 47 Figure 20: External IRQ Acknowledgement Timing Diagram ............................................................... 51

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List of Tables

Table 1: AMBA DMA Controller Pin-out Description ............................................................................. 16 Table 2: Isolated DMA capabilities also expressed as data rate in Gbit/s for bus frequencies ............ 23 Table 3: Synthesis Package Definitions (mtip_dma_pack_package.verilog) ....................................... 25 Table 4: Receive Descriptor Definition .................................................................................................. 30 Table 5: Transmit Descriptor Definition ................................................................................................. 35 Table 6: 32-bit FIFO Interface Data Structure ....................................................................................... 38 Table 7: 64-bit FIFO Interface Data Structure ....................................................................................... 38 Table 8: Transmit/Receive 32-bit FIFO Interface word Modulo Definition ............................................ 43 Table 9: Transmit/Receive 64-bit FIFO Interface word Modulo Definition ............................................ 44 Table 10: Frame Status Word Bits ........................................................................................................ 45 Table 11: Global Register Map (Control Block) .................................................................................... 46 Table 12: Interrupt Sources................................................................................................................... 50 Table 13: Global Register Map (Control Block) .................................................................................... 52 Table 14: IO-Register Map .................................................................................................................... 53 Table 15: TX_GLOBAL_CONTROL Register (Offset 0x00) ................................................................. 69 Table 16: TX_STATUS Register (Offset 0x04) ..................................................................................... 70 Table 17: RX_GLOBAL_CONTROL Register (Offset 0x100) ............................................................... 71 Table 18: RX_STATUS Register (Offset 0x104)................................................................................... 72 Table 19: Contact Information ............................................................................................................... 74 Table 20: Document History Entry Log ................................................................................................. 75

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1 Introduction

This document outlines and covers all aspects of the AMBA DMA Controller IP Core hardware that facilitates a method of enabling high speed bandwidth in both directions from an Ethernet pathway to a CPU sub-system. The emphasis is to allow Ethernet frames to/from a MAC/SWITCH into the CPU sub-system using hardware in the form of an AXI master.

Application programmers particularly those who are increasingly benefitting from being able to port powerful data processing software into an embedded environment are increasingly looking for an ability to process huge exposure to network traffic on target platforms. This is in stark contrast to previously only having the processing ability to observe or manage data network traffic on behalf of other systems because of the bottleneck and restrictions of software layers associated with network hardware including master DMA blocks as part of a wider processor system.

The primary objective of such a solution confidently provides a rare ability to exceed the traditional boundaries of fast Ethernet 100Mbit/s throughput full duplex with application software running on off-the-shelf affordable target devices. This is achieved by the pioneering architecture of MorethanIP design technology with DMA (Direct Memory Access) in the fabric of a silicon device.

Any software device driver needed would be minimal in processor execution overhead; the constraints and responsibility are placed upon the application programs instead. The hardware is designed to perform as much processing of the data transfer as possible with only the setup and completion work to be carried out between any software driver and the DMA hardware IP core.

The DMA controller is also very flexible in its footprint and capabilities in terms of how it can interface and support different data widths, bus types, silicon device vendors, packet priority behavior, and the way the data is interpreted from physical memory.

The deliverable package provides full Verilog source, simulation, synthesis, optional device driver (with source code) depending on customer requirements, documentation and scripts. All of these will be discuss later in the document.

1.1 Existing Hardware Module Compatibility

Currently, there are many different network IP cores and modules for FPGA and ASIC silicon devices. These cores vary in terms of the position they fit into building a network controller system or high-end Ethernet switch fabric.

Usually, the boundary of logic core deliverable is the application side of the MAC or an Ethernet switch which always presents a generic FIFO interface. It is this standardization of a powerful interface from a FIFO buffer that connects to the DMA IP core module with the host processor bus technology on the other side. With the processor and the FPGA fabric together, the common standard bus mechanism is AXI and/or AHB-Lite is required to allow both to communicate.

As will be seen later on in this documentation, the DMA Controller IP will comfortably position between a vendor’s processor environment and all the current MorethanIP IP cores with a FIFO interface. Traditionally, the FIFO interface would have been accessed via slave DMA modules via PCI Express or AXI buses from the processor and would have required exhaustive processor execution or at best, costly DMA setup per transaction.

Now, with this new DMA Controller master, many packets will pass either way full duplex exerting only minimal interrupt IRQ house-keeping on the packet memory transactions. Moreover, multi-packet setup using descriptor tables keeps the processing execution even lower within the kernel device driver leaving the majority share of processor execution time to the operating system and application software.

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1.2 Direct Memory Access

DMA has been around for a long time and more and more solutions are looking for hardware to process data in order to allow critical resources to be freed up. This product has been developed as high speed DMA solution to allow Ethernet network traffic destined for a device to be exposed to application software processing physical memory content. The main emphasis is exposing the packets in memory visible to application code to the network as efficiently as possible. This will not invoke huge processing resources beyond what the application is performing, thus – the customer program is not be aware of the mechanism on how the hardware that is controlled by the software device driver will be performing.

The solution uses advanced DMA in the fabric driving the memory bus of a given system environment. Therefore, simple application interfacing to the surrounding IP network has been achieved without forcing the end user to have to utilize non-standard distributions of software and more importantly, all of the logical hardware can reside in the same target device.

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2 Context of a typical Software driver & IP core

Important Note: This chapter is an example environment illustrating a device driver under Linux. This can be provided by MorethanIP/Nine Ways, but for this document, only serves as an example. Any software platform can be used to interface to the DMA IP hardware.

The controlling software driver needed to initialize and handle the RX and TX Ethernet frames through the DMA Controller IP hardware, can be written in any language, in any operation system environment, or even bare-metal situations where the driver functionality controlling the DMA occupies near full execution of the CPU.

However, most commonly, users prefer the C-language, and more commonly they do like to choose a good well established OS and that a device driver is therefore needed. MorethanIP/Nine Ways do provide a pre-supplied flavor of device driver for an OS, but this is detailed in other documents. For now, we will concentrate on the generic functionality and concept of the DMA Controller.

Below is an illustration of a typical driver, its surrounding environment, and the interface to the hardware module blocks. For the purpose of the illustration shown, it indicates how it would typically fit into a Linux environment for example:

Figure 1 - Context of the Linux Driver

The Linux device driver and its associated hardware DMA Controller are highlighted in dashed red. They only form a small part of the overall infrastructure that will integrate to provide an overall solution for an application.

The hardware DMA Controller is represented by the thick red arrow and is only concerned with reading and writing Ethernet packet frames into a buffer in the processor subsystem memory. Multiple

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packets can be fetched and transmitted to/from the DMA controller to the MAC/SWTICH FIFO forming a transmit TX packet and data can be written to the RAM constituting a receive RX.

A black arrow is shown from the memory linking the IP stack with the application API. This shows how the memory allocation in RAM is constant for all of those. The DMA device driver, the IP stack and application software in the layers above only pass on and process the pointer location to the frame buffer in working RAM. In its most ideal operation, the only transfer of data is performed by the DMA Controller IP in and out of the DDR memory, and then the Linux kernel transfers a pointer around the entire software OSI layer. If the packet then replies from the application layer API with just modified data contents performed by the intended algorithm of its usage, then essentially the DMA Controller moves packets into RAM, they are processed by high-level software and then DMA transferred back out to the MAC forming a read-process-write mechanism. (Note: this is only achievable with careful management of memory buffers and full control of the IP stack with regards to minimum CPU-copy).

Figure 2 - Different scenarios of DMA Controller usage

The Figure (above) illustrates the typical IP cores that may be requested by a system designer that is to be an integrated design inside a target device such as an FPGA. The Linux device driver that is provided only handles and interacts primarily with this DMA Controller which is common to all of the examples in the illustration.

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3 Core Objectives

The DMA Controller implements the following functionalities:

1. Flexible DMA controller to attach MorethanIP FIFO interfaces to system busses such as

AMBA AXI.

2. Support flexible bus width of 32-bit and 64-bit system memory busses.

3. Support flexible FIFO data-width of 32-bit and 64-bit to the hardware.

4. At minimum supporting two independent channels (descriptor rings), one for ingress (FIFO to bus) and one for egress (bus to FIFO) data transfers.

a. Scalability to support more than 1 descriptor ring per direction (e.g. to allow multiple rings for traffic of different priority)

5. Three Independent AMBA Interfaces

a. AHB-Lite Control Block to allow internal and external register access for control and

configuration of the DMA controller as well as provide access to registers within the externally connected module (MAC, Switch configuration etc)

b. AXI Write Master (TX) to transfer data from memory to FIFO interface.

c. AXI Read Master (RX) to transfer data from FIFO interface to memory.

6. Fully independent (parallel) operation of Egress (TX) and Ingress (RX) channels.

7. Up to 128-bit of control and status (side-band) in formation transferred transparently with frames for arbitrary use by system and application (e.g. timestamps carrying PTP-1588 L2 frames)

8. Flexible interrupt support for efficient transmit and receive handshaking.

9. Pass-through ability to SWITCH/MAC for hardware calculation of UDP/TCP header checksum removing CPU processor burden per packet.

10. IO-Register control/status with MUX providing throughput access to cascaded hardware cores.

3.1 Product Objective The DMA Controller core exists as an encapsulated modular design that is device vendor independent and will modularly connect to the user interface – that being the FIFO interface of a MAC/SWITCH. The other side of the data transfer from the FIFO is a memory bus interface complying with the AMBA standard for AXI. Essentially, the is a hardware efficient method of interchanging the FIFO Ethernet frame traffic from other IP Ethernet cores to a common memory bus so that useful user application software can run in order to process the data in the real world. This can only be achieved by providing the user applications a realistic chance of ever being able to process such large amounts of Ethernet packets in either direction. By using a software device driver to allow a program to run it will now be able to facilitate far more of a complete solution to the user than just a generic FIFO (client) interface from a MAC/SWITCH core.

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It is most important to conclude (for this introduction) that this DMA Controller hardware provides the ability for a user to use a single silicon device to process as an end-point to the Ethernet traffic at ~100Mbit and above (not just as a burst – but as sustained average consumption). Most commonly, other IP cores have allowed very high speed Ethernet passing through the devices – but not as part of a solution to consume and process that data as something useful.

3.2 Software Driver

Whilst it is not assumed or compulsory to have to use a Linux driver, one has been provided as a start point for users. Any driver can be written and customized to users’ needs, but most commonly a Linux based environment is chosen by system designers. Any software driver’s objective is to manage the DMA Controller hardware and potentially initialize all MorethanIP associated hardware alongside (MAC, PHY, PCS and SWITCH).

The uCLinux device driver that is provided with the DMA Controller, as standard provides the C files to compile the basic device driver only. Other packages on other Nine Ways products such as NetFusion, include PTP-1588 and a customized “iperf” feature. However, this document relates only to the AMBQ DMA Controller as a deliverable stand-alone package.

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4 Top AMBA DMA Controller Block Diagram

4.1 Overview

Below illustrates the Top-Level DMA core. Within the core it shows a Control Block next to an RX/TX DMA Engine. The RX/TX engine handles all RX and TX DMA transfers between AXI memory bus and the FIFO bus. The Control Block handles the AHB-Lite IO-Registers, IRQs and general control of the RX/TX block.

Figure 3 – Top Model AMBA DMA Controller Schematic

4.1.1 DMA Controller

The DMA Controller Core is divided into two main functional blocks:

1. Control Block: Implements an AHB-Lite Slave interface to allow access to internal and external registers for management and status.

2. Combined Read/Write AXI Master (RX/TX): Transfers data from FIFO receive interface into system memory (write) and independently transfers data from system memory (read) to FIFO transmit interface.

The Control Block DMA IO-Registers allows memory mapped control and status of the DMA Controller core. Additionally, it provides a throughput via a MUX to other addressable hardware cores such as MACs, PCSs and SWITCHs. This provides the processor sub-system a simple mapped DMA primary interface which then delegates the addressing in a cascaded fashion to additional hardware cores that are typically associated with this controller when considering the design.

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5 Top Level AMBA DMA Controller Pin-out

5.1 Overview

The overall DMA Controller deliverable will be synthesized with the following memory bus mechanisms;

1. AHB -Lite 2. AXI (Specifically AXI-4)

The AXI is a fast streaming bus that will cope with the flow of RX and TX bursts from the DMA Master AXI interfaces. This is the main bus mechanism for the transferred data. However, the IO-Register access for read/write control and feedback is mapped on an AHB-Lite bus. All silicon device architecture now uses some form of AHB-Lite bus system.

Important Note: The figure in the previous section shows the blocks in the Top Level DMA

core. Within the core it shows a Control Block next to an RX/TX DMA Engine. The RX/TX engine handles all RX and TX DMA transfers between AXI memory bus and the FIFO bus. The Control Block handles the AHB-Lite IO-Registers, IRQs and general control of the RX/TX block.

For the purpose of neatness and clarity, those two separate blocks with-in the top-level core, are separately shown below. In effect, both combine to form the overall pin-out but are just shown separately.

5.2 Control Block (Part 1 of the Top-Level Core)

Figure 4 - AHB-Lite Bus Interface for the IO-Register component of the DMA Controller Top Module

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5.3 RX/TX Block (Part 2 of the Top-Level Core)

Figure 5 – AXI Bus Interface for the DMA Core component of the DMA Controller Top Module

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6 The Top-Level Pin-out of the DMA Controller Hardware

Table 1: AMBA DMA Controller Pin-out Description

Signal Name Mode

Description

reset_clk_ahb in

Active high reset signal for clk clock domain. Reset the logic synchronized by

the clock hclk. (ahb_aresetn – AHB-Lite AMBA bus system reset). This pin

is tied to the ahb_aresetn of the main ARM AMBA bus.

Note: As this is active HIGH, a negative clock source will require inversion.

hclk in System Clock (AHB-Lite AMBA bus system clk).

Note: This can be tied together with aclk if the system shares a common clk.

reset_clk_axi in

Active high reset signal for clk clock domain. Reset the logic synchronized by

the clock aclk (axi_resetn - AXI AMBA bus system reset). This pin is tied to

axi_resetn of the main ARM AMBA bus.

Note: As this is active HIGH, a negative clock source will require inversion.

aclk in System Clock. System Clock (AXI AMBA bus system clk).

Note: This can be tied together with hclk if the system shares a common clk.

AXI Bus Write Signals (synchronized to the AXI clk)

awid[AXI_ID_WIDTH-1:0]

out Write address ID. This signal is the identification tag for the wriet address group of signals.

awlen[3:0] out Burst length. The burst length gives the exact number of transfers in a burst.

awsize[2:0] out Burst size. This signal indicates the size of each transfer in gthe burst.

awburst[1:0] out Burst type. The burst type, coupled with the size of the information, details how the address for each transfer within the burst is calculated.

awaddr[AMBA_ADDR_WIDTH-1:0]

out AXI write address. The write address bus gives the address of the first transfer in a write burst transaction.

awcache[3:0] out Cache type. This signal indicates the buffer, cache, write-through, write-back, and allocate attributes of the transaction.

awprot[2:0] out

Protection type. This signal indicates the normal, priviledged, or secure protection level of the write transaction and whether the transaction is a data access or an instruction access. The default value is normal, non-secure, data acess. Default: 2

awvalid out Write address valid. This signal indicates that valid write address and control information are available.

awlock[1:0] out Lock type. This signal provides the additional information about the atomic characteristics of the transfer. Default: normal

wdata[AMBA_DATA_

WIDTH-1:0] out Write data bus.

wstrb[AMBA_DATA_

WIDTH/8-1:0] out

Write strobes. This signal indicates which byte lanes to update in physical DDR memory.

wlast out Write last. This signal indicates the last transfer of a burst transaction.

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wvalid out Write valid. This signal indicates that valid write data and strobes are available.

awready in Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

wready in Write ready. This signal indicates that the slave can accept the write data.

bid[AMBA_DATA_

WIDTH-1:0] in Response ID. This is the identification tag for the write response signals.

bresp[1:0] in Write response. This indicates the status of the write transaction.

bvalid in Write response valid. This signal indicates that a valid write response is available.

AXI Bus Read Signals (synchronized to the AXI clk)

bready out Response ready. This signal indicates that the master can accept the response information.

arid[AXI_ID_WIDTH-1:0] out Read address ID. This signal is the identification tag for the read address group of signals.

araddr[AMBA_ADDR_

WIDTH-1:0] out

Read address. The read address bus gives the initial address of a read burst transaction.

arprot[2:0] out Protection type. This signal provides protection unit information for the read transactions. The default value is normal, non-secure, data acess. Default: 2

arcache[3:0] out Cache type. This signal provides additional information about the cache characteristics of the transfer.

arvalid out Read address valid. When HIGH, this signal indicates that the read address and control information are valid. The signal remains stable until the address acknowledgement signal, M_AXI_ARREADY, is HIGH.

arlen[3:0] out Burst length. The burst length gives the exact number of transfers in a burst.

arsize[2:0] out Burst size. This signal indicates the size of each transfer in the burst.

arburst[1:0] out Burst type. The burst type, coupled with the size of the information, determines how the address for each transfer within the burst is calculated.

arlock[1:0] out Lock type. This signal provides the additional information about the atomic characteristics of the transfer. Default: normal

rready out Read ready. This signal indicates that the master can accept the read data and response information.

rmw out

Read-Modify-Write. This is controlled by a register bit and signals to a host processor environment such as the ARM sub-system the policy of whether to enable RMW. This is normally just a configuration setting for the sub-system which varies depending on the vendor. This is set in software.

arready in Read address only.This indicates that the slave is ready to accept an address and associated control signals.

rid[AXI_ID_WIDTH-1:0] in Read ID tag. This is the identification tag for the read data group of signals.

rdata[AMBA_DATA_

WIDTH-1:0] in Read data bus.

rresp[1:0] in Read response. This signal indicates the status of the read transfer.

rvalid in Read valid. This signal indicates the last transfer in a read burst.

rlast in Read last. This indicates the last transfer in a read burst.

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RX FIFO Interface (MAC or SWITCH) (synchronized to the AXI clk)

ff_rx_err_stat[4:0] in

Receive Frame Status and Error indications from MAC/SWITCH. A status word is available with each received frame with the final octet (ff_rx_eop set to ‘1’).

bit 0: Current Frame invalid length

bit 1: Current Frame CRC-32 error

bit 2: Frame was truncated due to FIFO RX overflow

bit 3: PHY signal error (gmii_rx_err from PHY to MAC/SWITCH)

bit 4: Current frame implements VLAN tag

Note: Any additional bits such as VLAN Payload Length and Collision detection will have to be placed into the xstat extended bits as per project design required by a customer.

ff_rx_data[C_FIFO_DATA_WIDTH-1:0]

in Received Data. The first bytes received is ff_rx_data[7:0] and upwards......

ff_rx_sop in Received Start of Packet. Set to ‘1’ when the first octet of a frame is driven on ff_rx_data[7:0].

ff_rx_eop in Received End of Packet. Set to ‘1’ when the last word of a frame is driven on ff_rx_data[31:0] or ff_rx_data[63:0] depending on bus width selected.

ff_rx_err in Received Frame Error. Asserted with the frame final word to indicate that an error was detected by the MAC/SWITCH when receiving the frame. Error code is described and presented on lines ff_rx_err_stat[4:0]

ff_rx_mod[2:0] in

Received Data Modulo. This indicates which portion of the final frame word is valid. There are 3 bits here as it supports the inclusion of utilizing 64-bit data bus widths.

Note: See Tables further documented for bit-meanings and descriptions for 32-bit and 64-bit variants.

ff_rx_xstat[127:0] in Received Extra Status Vector information. A 128-bit side-band data block presented from the MAC/SWITCH on the last word received from the FIFO

interface.

ff_rx_dval in Received Data Valid. Asserted to ‘1’ by the MAC/SWITCH to indicate that data on ff_rx_data[C_FIFO_DATA_WIDTH-1:0], ff_rx_sop, ff_rx_eop, ff_rx_err and ff_rx_err_stat[4:0] are valid.

ff_rx_dsav in Receive Frame Data Available Indicator. Indication that the receive FIFO of the MAC/SWITCH contanis data to be read (not necessarily the complete frame at that point in time). The DMA RX Controller could start to read the FIFO if desired.

ff_rx_protocol_checksum[15:0]

in

This receives the UDP/TCP checksum range data to be stored in the RX Descriptor entries for each frame. This stores the 16-bit byte-swapped result back in to the descriptor entry for application use.

Note: This data is presented from the MAC/SWITCH on the last word received from the FIFO interface.

ff_rx_protocol_checksum_valid

in

If set to ‘1’, the ff_rx_protocol_checksum[15:0] signal is driven with the UDP/TCP checksum data from the MAC/SWITCH as the functionality is therefore supported..

Note: signal is valid from ff_tx_sop throughout ff_tx_eop.This is acheived as a MAC/SWITCH has FIFO buffers to store and hold tha packet frame to analyse.

ff_rx_ch in

This indicates which Descriptor channel the received RX packet frame should go to. If asserted to ‘1’ then it indicates that the frame should go to CH1 otherwise if kept LOW then CH0. If it is asserted then it must be stable when ff_rx_sop is set. It must remain stable until ff_rx_eop is set.

It should already be valid and stable when ff_rx_dsav asserts, hence the RX DMA scheduler can prepeare the correct DMA RX channel to read.

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ff_rx_ready out Receive Application Ready. Set to ‘1’ by DMA RX Contoller to indicate that it is ready to receive data from the MAC/SWITCH. ff_rx_ready must be generated on clk rising edge.

TX FIFO Interface (MAC or SWITCH) (synchronized to the AXI clk)

ff_tx_ready in

MAC/SWITCH hardware FIFO is ready for transmission when set to ‘1’. Only when there are more than 2 entries free in a given channel descriptor table, will this signal be de-asserted and set to ‘0’.

Note: The TX DMA should stop writing to the interface with in one clock cycle (1

cycle latency)

Note: five entries gives the fast FIFO activity time to react without loosing packets when no free entries are available.

ff_tx_dsav out Transmit Data Available Indicator. Set to ‘1’ when the DMA TX Controller is ready to transmit to MAC/SWITCH because it has data to send.

ff_tx_data[C_FIFO_DATA_WIDTH-1:0]

out Transmit Data. The first bytes received is ff_tx_data[7:0] and upwards......

ff_tx_sop out Transmit Start of Packet. Set to ‘1’ when the first octet of the frame is driven on ff_tx_data[7:0].

ff_tx_eop out Transmit End of Packet. Se to ‘1’ when the final word of a frame is driven on ff_tx_data[31:0] or ff_tx_data[63:0] depending on bus width selected.

ff_tx_dval out Transmit Data Valid. Asserted to ‘1’ by this DMA TX Controller to indicate that data on ff_tx_data[C_FIFO_DATA_WIDTH-1:0], ff_tx_sop, ff_tx_eop and ff_tx_err are valid.

ff_tx_mod[2:0] out

Transmit Data Modulo. This indicates which portion of the final frame word is valid. There are 3 bits here as it supports the inclusion of utilizing 64-bit data bus

widths.

Note: See Tables further documented for bit-meanings and descriptions for 32-bit and 64-bit variants.

ff_tx_xstat[127:0] out

Transmit Extra Status Vector information. A 128-bit side-band data block presented to the MAC/SWITCH on the first octet transmitted to the FIFO interface.

Note: This is in contrast to the receive xstat function. For TX, the xstat

information must be available and present at the beginnig of the packet frame. There could be certain important bits of information that the MAC/SWITCH needs to know before handling the frame. With RX, it is only presented at the end of the packet frame ff_rx_eop before being stored in the RX descriptor entry.

ff_tx_err out Transmit Frame Error. Set to ‘1’ with the frame final word to indicate that the transmitted frame is invalid.

ff_tx_crc_fwd out

TX MAC/SWITCH CRC forward from the software device driver. If set to ‘0’ together with ff_tx_eop, a CRC is calculated and appended to the frame in the MAC/SWITCH core. If set to ‘1’, the MAC/SWITCH does not append a FCS to the frame. Instead the frame is transmitted unchanged. ie/ The CRC is forwarded from the software device driver.

ff_tx_protocol_checksum_enable

out

If set to ‘1’, the ff_tx_protocol_checksum[31:0] signal is driven with the UDP/TCP checksum data so that the MAC/SWITCH (if supporting this functionality) can hardware calculate the TCP/IP or UDP/IP protocol header/payload chechsum and insert into the TCP/IP or UDP/IP header.

Note: Must be valid from ff_tx_sop throughout ff_tx_eop.

ff_tx_protocol_checksum[31:0]

out

If ff_tx_protocol_checksum_enable is asserted, this transmits the UDP/TCP checksum range data stored in the TX Descriptor entries for each frame. This is used to calculate the start and size of the UDP/TCP protocol arithmatic in the Ethernet frame and also where to store the 16-bit byte-swapped result. Assert this bus before ff_tx_sop active.

Note: Must be valid from ff_tx_sop throughout ff_tx_eop.

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ff_tx_ch out

This indicates which Descriptor channel the transmitted TX packet frame originated from. If asserted to ‘1’ then it indicates that the frame came from CH1 otherwise if kept LOW then CH0. If it is asserted then it must be stable when ff_rx_sop is set. It must remain stable until ff_rx_eop is set.

Note: This can be used as a priority system for the tranportation mechanism.

AHB-Lite Control Block Interface (synchronized to the AHB clk)

haddr[31:0] in The 32-bit address bus.

hburst[2:0] in

These signals indicate if the transfer forms part of a burst. Four, eight, and sixteen beat bursts are supported and the burst can be either incrementing or wrapping.

hmaster_lock in Indicates that the current master is performing a locked sequence of transfers. This signal has the same timing as the HMASTER signals.

hprot[3:0] in

The protection control signals provide additional information about a bus access and are primarily intended for use by any module that requires some level of protection. The signals indicate if the transfer is an op-code fetch or data access, as well as if the transfer is a privileged mode access or User mode access. For bus masters with a memory management unit these signals also indicate whether the current access is cacheable or buffer capable.

hready in When HIGH, the HREADY signal indicates that a transfer has finished on the bus. You can drive this signal LOW to extend a transfer.

hsel in

Each AHB slave has its own slave select signal and this signal indicates that the current transfer is intended for the selected slave. This signal is simply a combinatorial decode of the address bus.

hsize[1:0] in

These signals indicate the size of the transfer, typically byte (8-bit), half-word (16- bit), or word (32-bit). The protocol permits larger transfer sizes up to a maximum of 1024 bits.

htrans[1:0] in This indicates the type of the current transfer. This can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY.

hwdata [31:0] in

The write data bus transfers data from the master to the bus slaves during write operations. ARM recommends a minimum data bus width of 32-bits. However, you can easily extend this to enable higher bandwidth operation.

hwrite in When HIGH, this signal indicates a write transfer, and when LOW, a read

transfer.

hrdata[31:0] out

The read data bus transfers data from bus slaves to the bus master during read operations. ARM recommends a minimum data bus width of 32-bits.

However, you can easily extend this to enable higher bandwidth operation.

hresp[1:0] out The transfer response provides additional information on the status of a transfer. Four different responses are provided, OKAY, ERROR, RETRY, and SPLIT.

hready_out out Transfer Done. The AHB slave uses this signal to extend an AHB transfer. Default state: 1

External Register bus (synchronized to the AHB clk)

ext_reg_busy in Register interface busy signal. Assert ‘1’ during register read or write access. Set to ‘0’ to indicate the completion of the current register access.

ext_reg_interrupts[15:0] in 16 external interrupt lines from general purpose cascaded hardware cores such as MACs and SWITCHs. These are level sensitive and are standardized to forward an interrupt on a positive ‘1’ assertion when the logic is clocked.

ext_reg_intack[15:0] out

Acknowledge strobe for each of the 16 external interrupt lines respectively ext_reg_interrupts [15:0]. These lines strobe positively for one clock cycle then restore back to ‘0’ to clear a pending interrupt generated externally. The INTERRUPT_PENDING register drives this operation when the user application or Linux device driver software clears the corresponding pending flags.

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ext_reg_rd out Register interface READ control signal (Register Read Enable). Assert ‘1’ during register read access. Set to ‘0’ when not attempting a register read.

ext_reg_wr out Register interface WRITE control signal (Register Write Enable). Assert ‘1’ during register write access. Set to ‘0’ when not attempting a register write.

ext_reg_addr[19:0] out Register Address bus. Bit 0 is the least significant bit.

ext_reg_ wdata[31:0] out Register Write Data bus. Bit 0 is the least significant bit.

cpu_int out Connects to the CPU sub-system usually the ARM for embedded applications in device silicon

ext_resetn out

The internal reset_clk line from the AMBA bus is forwarded to this pin to be tied to other cores e.g. MAC or SWITCH. As the IO-Register Interface is compulsory

with the DMA RX/TX core, and that this block handles the forwarding of configuration IO Registers – it therefore has this active LOW reset line derived from the AHB-Lite bus system. This allows further logic hardware to be synchronized reset with the main system.

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7 DMA Speed & Through-put Capability

7.1 Introduction

The most important section in this manual is probably this one. You will probably want to know what performance this DMA hardware IP core will enable you to have!

It is always very ambiguous when expressing such performance capabilities as the environment that this DMA product shall be running is never the same and is affected by software, memory bus contention, bus system clock speed and other caching architecture.

It also has to be understood that what clocking capabilities the DMA hardware core can achieve in isolation is a “perfect environment” and is going to be much higher performance and throughput than any real-world environment whether low-end platforms or high-end.

Nevertheless, for comparative reasons, this section will state the isolated throughput tests and capability separate to the platform bench-tests. Also, the platform measurements are only a start point at this time, which the DMA hardware has been established working – and that beyond the initial release of the product, more target devices, supporting hardware and higher clocking speeds can be utilized.

7.2 Isolated DMA Hardware Modeling

For each and every RX or TX Ethernet frame to the DMA Controller:

1. There are 3 clock cycles of overhead in the IO-Register layers (this does not apply to the RX DMA process)

2. Followed by 2 clock cycles overhead for the AXI initial addressing

3. Per FIFO transaction to the MAC/SWITCH (this can be 32-bit or 64-bit) there are 2 clock cycles.

4. Per setup of AXI burst sequences, there are usually no additional clock cycles on good AXI models. This is because the address bus setup and confirmation can be achieved simultaneously with previous data burst transactions. This assumption will be used for this section.

5. A single clock cycle for the AXI completion

6. Finally, 2 clock cycles for IO-Register updating and re-synchronization before next frame can be handled by the DMA TX block.

For isolation tests and performance, it is ideal criteria that we are trading with maximum size (MTU) Ethernet Frames of 1518 octets (plus overhead from the MAC layer). However, the results below will show the variation with some different sized Ethernet frames.

Please Note: This is the whole frame including MAC header, IP, and all IP payload and protocols but NOT the CRC at the end or preamble at the start of a frame.

Additional Note: the reduction in the 3 clock cycles for setup with the RX will be ignored for the following tables of results as this will make negligible difference to the noticeable rate. It will assume that the RX does induce 3 clocks just like the TX DMA at the start of each frame. This simplifies the results to view.

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Table 2: Isolated DMA capabilities also expressed as data rate in Gbit/s for bus frequencies

MTU 512 1024 1518

Data Width 32-bit 64-bit 32-bit 64-bit 32-bit 64-bit

Total Clock Cycles 264 136 520 264 766 386

Bus Frequency 20.750 MHz 0.32 0.75 0.325 0.64 0.33 0.67

Bus Frequency 41.5 MHz 0.64 1.25 0.65 1.28 0.66 1.3

Bus Frequency 83 MHz 1.28 2.50 1.30 2.57 1.31 2.61

Bus Frequency 166 MHz 2.56 5.00 2.60 5.14 2.62 5.22

Bus Frequency 333 MHz 5.12 10.00 5.20 10.28 5.24 10.44

Data Rates expressed in Gbit/s

Note: An assumption that a CRC has been included and added on to the MTU size. Preamble will have been stripped by the MAC/SWITCH.

Additional Note: An assumption has been made that once a frame has completed, another one starts immediately and there is no gaps in between the DMA processes from the end of IO-Register updates for the previous frame and the setup process for the next frame.

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7.3 Isolated DMA Real-World Considerations

The clocking table (above previously) illustrates a very simplistic measurement with wild assumptions. However, if comparing the effectiveness and efficiency of other DMA mechanisms, then this information may prove indispensable for selecting the best solution to your design.

Below are several important realistic considerations to take into account when seeing differences between real-world platform measurements against the isolated (test-bench ModelSIM) DMA Controller:

1. The processor sub-system could not ever cope with constant data saturation at maximum bus frequency. The cached instructions would need to access memory.

2. The application code would need to process the information taking up more execution time, clock frequency and creating bus contention.

3. The AXI bus would not necessarily provide an acknowledgement for address and data read/write transactions after the minimum 2 clock cycles.

4. The MAC/SWITCH connected beyond the FIFO interface could be a bottleneck restriction.

5. MTU packet sizes will vary and not always utilize the maximum efficient size.

6. The processor has to take time to access the RX and TX descriptor tables using the memory bus.

7. Other peripheral hardware will more than likely share the same memory bus architecture. This will cause contention that will be observed by the DMA AXI Master hardware as long delays waiting for an initial acknowledgement to the first address request of a given Ethernet frame or even per AXI read/write burst chunk.

8. The IP stack of any system chosen will always even with minimal CPU-copy techniques, inevitably bottleneck the data flow.

9. AXI timeouts on hardware glitches and possible contention errors will introduce an average drop in throughput.

10. Pipelining of AXI host hardware will introduce delays for each Ethernet frame. Pipelining will attempt to keep the consecutive AXI read/write bursts flowing with the address request far ahead of the data equivalent burst. However, initial setup per frame and occasional timeouts and contention on the AXI bridges and the DDR controller will affect the response time.

11. Ultimately, the nature of the memory storage will also bottleneck the independence of the RX TX pathways through the DMA Controller. If the DDR interface to the SDRAM device is half duplex, which can occur in LPDDR devices, and then this shall cause contention across the RX and TX pathways. Only full-duplex DDR interfaces keep ideal separation.

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8 Synthesis Options

8.1 Global Synthesis Options

The following table lists the relevant synthesis options found in the global package file. This file is included by all sources to set global definitions. These are for size optimizations and to include/exclude features that affect pin-outs of modules.

The file is included by every relevant source file to configure several options during synthesis. The following settings in this file can be changed. All others must remain unchanged.

Table 3: Synthesis Package Definitions (mtip_dma_pack_package.verilog)

Setting Name Type Description Default

Revision Configuration

MTIP_CUSTOMER_ SPECIFIC_REVISION

parameter

This can be any 16-bit integer value. It is stated in hexadecimal in the package file and is used as a sub-version number by a project integrator using this DMA Controller package in their design.

0001 (HEX)

MTIP_CORE_VERSION parameter DO NOT CHANGE 1301 (HEX)

Data Width & AXI Master Configuration

AMBA_ADDR_WIDTH parameter Global AMBA system data width. This affects the AXI address width only in this case. It sets the number of bit of the AXI Master address bus and MUST match the width of the system memory bus of the host device system architecture.

Note: Must be a power of 2, at least 32.

32

MTIP_MAC_UUT_64BIT

`define

This define states whether the DMA system data width is 64-bit or not. By `defining it declares the parameter AMBA_DATA_WIDTH to be 64. Else, it allows parameter AMBA_DATA_WIDTH to be 32. This parameter governs the width of the FIFO data interface and the AXI Master data width for both RX and TX pathways.

The parameter AMBA_DATA_WIDTH is controlled by a `define because of a ModelSIM Testbench requirement.

Note: The width of the DMA system data width (AXI and FIFO) is restricted to 32 or 64 only. Other attempted values will cause problems with operation.

Defined

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AXI_ID_WIDTH

parameter

Sets the number of bits for the write AXI address ID, write AXI data ID, read AXI address ID and read AXI data ID (rid).

This width is variable and you can use this to match the size of the AXI Slave that the DMA Controller Master connects to.

Note: Usual values are 2, 3 or 4.

4

AXI_RXDMA_ BACKPRESSURE_SIZE

parameter

Depth of the RX-DMA backpressure FIFO. This FIFO cushions the initial [sop] data to activate the RX mechanism, and also allows for the MAC to react slowly to an RX-DMA ready signal de-assertion. This, if set too low (less than 4 can cause problems with the RX if the ready signal is dropped to the MAC).

Note: This can be set as high as 2048 but optimally is operates well at 16 or 32.

32

RX & TX Descriptor Table Configuration

RXCH0_DESCSIZE

parameter

Sets the size of the High priority RX-DMA (Channel 0) descriptor table size in terms of entries.

This value if <zero> effectively disables the RX-DMA CH0 mechanism. Maximum allowed value is 256.

Note: Values in the higher range provide for better burst and high throughput performance, but may not synthesize well in smaller device families.

4

RXCH1_DESCSIZE parameter Sets the size of the Low priority RX-DMA (Channel 1) descriptor table size in terms of entries.

This value if <zero> effectively disables the RX-DMA CH1 mechanism. Maximum allowed value is 256.

Note: Values in the higher range provide for better burst and high throughput performance, but may not synthesize well in smaller device families.

4

TXCH0_DESCSIZE

parameter

Sets the size of the High priority TX-DMA (Channel 0) descriptor table size in terms of entries.

This value if <zero> effectively disables the TX-DMA CH0 mechanism. Maximum allowed value is 256.

Note: Values in the higher range provide for better burst and high throughput performance, but may not synthesize well in smaller device families.

4

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TXCH1_DESCSIZE

parameter

Sets the size of the Low priority TX-DMA (Channel 1) descriptor table size in terms of entries.

This value if <zero> effectively disables the TX-DMA CH1 mechanism. Maximum allowed value is 256.

Note: Values in the higher range provide for better burst and high throughput performance, but may not synthesize well in smaller device families.

4

Other Settings All other settings must be left unchanged. N/A

Special Consideration:

1. The Number of DMA channels is fixed at two TX channels additional to two RX channels. This allows for a priority of CH0 TX and CH0 RX over CH1 TX and CH1 RX for Ethernet frame prioritization.

2. The AXI and the AHB-Lite (Control Block IO-Registers) AMBA bus interface is little-endian. The FIFO Interface is always little-endian (bit7:0 is first byte, bit31:24 is last byte of a 32-bit word).

3. The Number of Descriptors per RX/TX channel for CH0 and CH1 are independently definable and configurable by synthesis parameters. The default value for each exists from reset until the device driver issues a configuration change before enabling the DMA engines.

4. The Descriptor Size is fixed to six words.

5. CH0 of both RX and the TX independent full-duplex pathways take priority over the CH1 descriptor entries for each respectively. For TX: The DMA engine will always search the CH0 first before CH1. For RX: The software device driver should transact CH0 receive entries before assessing the CH1 entries.

6. AHB-Lite Data Width (for Register-IO Control Block) = 32-bit.

Note: The AHB address width is limited to 32-bit. However, the AHB-Lite bus is only utilized from the host system for the access to the IO-Registers as this bus is just for register read/write control.

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9 RX DMA Mechanism

9.1 Overview

The system software (device driver) initializes two descriptor rings in IO-Register space. Each ring is AHB-Lite IO-Register space which holds the descriptors one after each other.

For each ring a read and write pointer register exists in the controller hardware. These pointers are used by the hardware to determine if there is space available in memory to receive data. The pointer is a simple number giving the position of the descriptor within the descriptor ring (i.e. it is not the real address).

When data is available at the FIFO interface, the current descriptor data provides all necessary information for the DMA engine to know where to write the data to (address) and how many words it can store in such buffer.

When the DMA has completed processing the data, a status word is generated and will update the status word (word0 of the descriptor) in the IO-Registers. A done indication is given back to the descriptor selection function, which will start another transaction as needed.

9.2 RX Descriptor

The descriptors are held in an IO-Register space in the hardware. The hardware accesses them in order implementing a ring-buffer. The size of the buffer (i.e. number of descriptors) is defined in hardware by parameterized options and limited to a maximum of 256 descriptors entries.

The descriptors are initialized by the software device driver. When the transaction is completed it will write the information into the table entry including also (if configured and enabled) write the xstat field when the side-band status signals have been captured by the hardware during the transaction.

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The following shows the descriptor definitions:

Figure 6 - Receive DMA Descriptor Entry

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9.3 Definitions

Table 4: Receive Descriptor Definition

Field name Position Width (bits)

Description

‘1’ word0, bit 31

1 Set to ‘1’ by hardware for validation purposes.

‘0’ word0, bit 30

1 Set to '0’ by hardware for validation purposes.

‘1’ word0, bit 29

1 Set to ‘1’ by hardware for validation purposes.

‘0’ word0, bit 28

1 Set to '0’ by hardware for validation purposes.

‘1’ word0, bit 27

1 Set to ‘1’ by hardware for validation purposes.

VALID word0, bit 26

1 Set to 0 by software when initializing the descriptor. Set to 1 by the controller hardware to indicate it has written this word with the status (i.e. RX transaction completed and length information stored and error bits are valid). The software can clear this bit for its own purpose if it chooses to but will be ignored by the RX DMA hardware.

DISC word0, bit 25

1 Read Only bit. Updated with RX Received IRQ event. If set to ‘1’, the received Ethernet frame was not fully transferred due to total bytes in the frame to be received in full exceeding the maximum allowed (set in IO Register globalframebuffermax). This bit is only updated after the attempted reception of this entry. Writing to this bit by software causes no harm but has no effect.

MACERR word0, bit 24

1 Error indication from the FIFO interface. Indicates some receive error and the frame should be ignored by the software.

DMAERR word0, bit 23

1 DMA or interface error. Indicates some local interface problem occurred during the transaction and the frame should be ignored.

CHKSUM word0, bit 22

1 Read Only bit. Updated with RX Received IRQ event. If set to ‘1’, the received Ethernet frame has generated an arithmetic checksum (Protocol Checksum in the descriptor – below). This bit is only updated after the attempted reception of this entry. Writing to this bit from software causes no harm but has no effect. Note: If the MAC/SWITCH associated hardware is not included with checksum analysis on RX, then this bit is cleared upon packet receive.

XSTAT word0, bit 21

1 xstat field is valid. Updated by hardware. The hardware has captured the xstat field from the FIFO interface during the transaction and the xstat field therefore contains valid information.

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ERR0 word0, bit 20

1 Error bit 0 indicator of MAC/SWITCH beyond FIFO. Set to ‘1’ if MAC/SWITCH indicates Current Frame invalid length.

ERR1 word0, bit 19

1 Error bit 1 indicator of MAC/SWITCH beyond FIFO. Set to ‘1’ if MAC/SWITCH indicates Current Frame CRC-32 error.

ERR2 word0, bit 18

1 Error bit 2 indicator of MAC/SWITCH beyond FIFO. Set to ‘1’ if MAC/SWITCH indicates Frame was truncated due to FIFO-RX overflow.

ERR3 word0, bit 17

1 Error bit 3 indicator of MAC/SWITCH beyond FIFO. Set to ‘1’ if MAC/SWITCH indicates PHY signal error (gmii_rx_err from PHY to MAC/SWITCH)

ERR4 word0, bit 16

1 Error bit 4 indicator of MAC/SWITCH beyond FIFO. Set to ‘1’ if MAC/SWITCH indicates Current Frame implements VLAN tag.

Bytes Received word0, bits 15:0

8 Number of valid bytes stored in the data buffer of this descriptor. Updated by hardware. Note: This is the true number of bytes. The hardware will transfer always 32-bit/64-bit words from the FIFO, but then indicate which bytes are valid when the last data word was stored in the data buffer. The field is updated at the end of the transaction by the hardware (then also setting the VALID bit).

Desc. Chksum word1, bits31:24

8 Not to be confused with the Protocol Checksum field, this is filled in when an Ethernet frame has been received. It is a one’s-compliment checksum of the entire 8 word RX descriptor entry. This can be used by the Linux software device driver in conjunction with bits 31:27 to check if this entry is a valid memory structure. Data validation can be performed. Updated by hardware.

Protocol Checksum

word1, 15:0

16 When an Ethernet frame is received and is valid, the hardware calculates the TCP or UDP protocol checksum if this functionality is included in the associated MAC/SWITCH hardware functionality. This field is the 16-bit result of the arithmetic analysis and can be used by the device driver to accept or reject the received Ethernet packet frame. Updated by hardware. The MAC/SWITCH hardware is not required to be told the offsets and sizes within the IP headers as it is not known what type of packet protocol will be received so it is all intelligent in the hardware. The Checksum bit (above) is set to ‘1’ also.

xstat words 2..5

128 A direct representation of up to 128-bit of side-band data that will be transferred to the FIFO interface at begin of a transaction (if XSTAT bit=1). The data is available for arbitrary use by the connected FIFO module and application. Updated by hardware.

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9.4 Flow Illustration of Receive RX Engine (Landscape View)

Figure 7 - Flow Chart Diagram of the RX Receive DMA Engine

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10 TX DMA Mechanism

10.1 Overview

The system driver (software) initializes two descriptor rings in system memory. Each ring is AHB-Lite IO-Register space which holds the descriptors one after each other.

For each ring a read and write pointer (or number) register exists in the controller hardware. These pointers are used by the hardware to determine if there is data present for transmission. The pointer is a simple number giving the position of the descriptor within the descriptor ring (i.e. it is not the real address).

When data is available, the current descriptor data is read from the IO-Registers in the hardware which provides all necessary information for the DMA engine to know where data is found (address) and how many bytes need to be copied.

When the DMA completed processing the data of the descriptor, a done indication is given back to the descriptor selection function, which will start another transaction as indicated by the descriptor pointers.

Note: The handshaking which descriptor had been transmitted is done by the read pointer which is updated by the hardware and can be inspected by the software.

10.2 TX Descriptor

The descriptors are held in IO-Register in the DMA hardware accessible by the AHB-Lite interface. The size of the buffer (i.e. number of descriptors) is defined by hardware (parameterized option) and is limited to 256 entries.

To access the descriptor the hardware uses pointers / counter variables to keep track of used and available descriptors.

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The following shows the descriptor definitions:

Figure 8 - Transmit DMA Descriptor Entry

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10.3 Definitions

Table 5: Transmit Descriptor Definition

Field name Position Width (bits)

Description

IRQ word0, bit 31

1 When set, the hardware will trigger a transmit interrupt when the descriptor has been served (i.e. all buffer data has been copied). The system could use this for example to set the interrupt only on the very last descriptor within a sequence of descriptors to get informed when the complete list of data has been transferred, instead of receiving an interrupt per transmitted block.

XSTAT word0, bit 30

1 xstat field is valid. The hardware will read the xstat field of the descriptor and produce it to the extended status bits at the FIFO interface. Typically the bit is set with the very first descriptor of a frame to ensure any side-band data is transferred and valid at the FIFO interface with the first data word written (and then stays constant).

DMAERR word0, bit 29

1 Read Only bit. Updated with TX Transmission IRQ event. If set to ‘1’, the transmission of this entry Ethernet frame was not successful due to an internal DMA error. This bit is only updated after the attempted transmission of this entry. Writing to this bit from software causes no harm but has no effect.

XMITDONE word0, bit 28

1 Read Only bit. Updated with TX Transmission IRQ event. If set to ‘1’, the transmission of this entry Ethernet frame was completed irrespective of a FIFO MAC/SWITCH error. This bit is only updated after the attempted transmission of this entry. Writing to this bit from software causes no harm but has no effect.

DISC word0, bit 27

1 Read Only bit. Updated with TX Transmission IRQ event. If set to ‘1’, the transmission of this entry Ethernet frame was not fully transferred due to total bytes in the frame to be sent exceeding the maximum allowed (set in IO-Register globalframebuffermax). This bit is only updated after the attempted transmission of this entry. Writing to this bit from software causes no harm but has no effect.

MACSUM word0, bit 26

1 If set to ‘0’, the Descriptor fields MAC Checksum START, MAC Checksum COUNT, MAC Checksum INSERTION have no effect and are ignored during TX transmission. However, if set to ‘1’, then those fields are used to program the connected MAC/SWITCH beyond the DMA Controller with values to calculate the UDP/TCP outgoing checksum. This is if the MAC/SWITCH hardware is to calculate as opposed to the software device driver or if the user wishes, the Linux IP stack as normal.

CRCFWD Word0, bit25

1 CRC forward flag. If set to ‘1’, the DMA TX core instructs the connected MAC/SWITCH not to append any CRC calculation to the packet frame being transmitted. It is assumed by the DMA hardware that the CRC has been constructed and stored by the

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software application layer. However, if set to ‘0’ then the MAC/SWITCH hardware is allowed to be generated by the logic and appended to the frame instead.

Bytes to Send word0, bits 15..0

16 Number of valid bytes stored in the data buffer of this descriptor. Note: This is the true number of bytes. The hardware will read always 32/64-bit words from memory, but then indicate which bytes are valid when transferring the very last word to the FIFO interface based on this information.

MAC Checksum START

word1, 31:22

10 (If MACSUM=1) this word has to be set with the value offset into the Ethernet frame of the UDP/TCP checksum start byte to be arithmetically processed. This is passed onto the connected MAC/SWITCH that supports store/forward arithmetic.

MAC Checksum COUNT

word1, 21:12

10 (If MACSUM=1) this word has to be set with the consecutive bytes in the Ethernet frame for the UDP/TCP checksum to be arithmetically processed. This is passed onto the connected MAC/SWITCH that supports store/forward arithmetic.

MAC Checksum INSERTION

word1, 11:0

12 (If MACSUM=1) this word has to be set with the value offset into the Ethernet frame of the UDP/TCP checksum 16-bit result word. This is in the TCP/UDP header. This is passed onto the connected MAC/SWITCH that supports store/forward arithmetic.

xstat words 2..5

128 A direct representation of up to 128-bit of side-band data that will be transferred to the FIFO interface at begin of a transaction (if XSTAT bit=1). The data is available for arbitrary use by the connected FIFO module and application.

Ethernet Frame Physical Address

Word7 32 Physical SDRAM memory location of this particular packet in memory. Unlike the RX descriptors that do not have this field and rely on a global MemPool register on a 2K/64K per packet basis, the TX is different. It has memory locations from the upper layer of software determining the location.

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10.4 Flow Illustration of Transmit TX DMA Core (Landscape View)

Figure 9 - Flow Chart Diagram of the TX DMA Engine

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11 FIFO Interface

11.1 32-Bit MAC/SWITCH Interface Data Structure

When the 32-bit AMBA_DATA_WIDTH implemented (synthesis option) the following is defined.

The data structure defined in the following tables for the FIFO interface must be respected to ensure proper data transmission on the Ethernet line. Byte 0 is transmitted or received first.

Table 6: 32-bit FIFO Interface Data Structure

31 24 23 16 15 8 7 0

word 0 byte 3 byte 2 byte 1 byte 0

word 1 byte 7 byte 6 byte 5 byte 4

...

The size of a frame on the FIFO interface may not be modulo of 32-bit. Together with the last word

of the frame, the valid byte(s) of data are defined by the interface signal ff_tx_mod(1:0) for

transmit and ff_rx_mod(1:0) for receive respectively.

11.2 64-Bit MAC/SWITCH Interface Data Structure

When the 64-bit FIFO is implemented (synthesis option) the following is defined.

The data structure defined in the following tables for the FIFO interface must be respected to ensure proper data transmission on the Ethernet line. Byte 0 is transmitted or received first.

Table 7: 64-bit FIFO Interface Data Structure

63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0

word 0 byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0

word 1 byte 15 byte 14 byte 13 byte 12 byte 11 byte 10 byte 9 byte 8

... ...

The size of a frame on the FIFO interface may not be modulo of 64-bit. Together with the last word

of the frame, the valid byte(s) of data are defined by the interface signal ff_tx_mod(2:0) for

transmit and ff_rx_mod(2:0) for receive respectively.

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11.3 FIFO Interface Transmit Operation

When the MAC/SWITCH is ready to receive data (signal ff_tx_rdy asserted) 1, the DMA

Controller asserts the FIFO write enable signal (ff_tx_wren) 2 to transfer data to the

MAC/SWITCH transmit FIFO.

The DMA Controller must send the first word of a frame with the start of frame signal

(ff_tx_sop)(3) and the last word with the end of frame signal (ff_tx_eop) asserted 4.

With the last word, a word modulo signal (ff_tx_mod(1/2:0)) must indicate which portion of the

bus is valid 5. Also the error signal (ff_tx_err) and CRC append signal (ff_tx_crc) must be

valid.

100 ns 200ns 300 ns 400 ns

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1 2

3 4

5

ff_tx_clk

ff_tx_rdy

ff_tx_wren

ff_tx_data(31/63:0)

ff_tx_mod(1/2:0)

ff_tx_sop

ff_tx_eop

ff_tx_err

Figure 10: FIFO Transmit Interface – Single Frame

The DMA Controller can effectively pause a frame transfer by de-asserting the data write enable

signal (ff_tx_wren for one or multiple clock cycles 1. The data transfer stops immediately when

ff_tx_wren is de-asserted. The transfer immediately restarts when the DMA Controller re-

asserts ff_tx_wren 2.

100 ns 200 ns 300 ns 400 ns 500 ns 600 ns

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1 2

ff_tx_clk

ff_tx_rdy

ff_tx_wren

ff_tx_data(31/63:0)

ff_tx_mod(1/2:0)

ff_tx_sop

ff_tx_eop

ff_tx_err

Figure 11: FIFO Transmit Interface - Frame Transfer with DMA Controller Pause

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By keeping the write enable (ff_tx_wren) asserted between two consecutive frames, the DMA

Controller can send back to back frames to the MAC/SWITCH.

500 ns 1 us 1500 ns

11 01 10 11

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ff_tx_clk

ff_tx_rdy

ff_tx_wren

ff_tx_data(31/63:0)

ff_tx_mod(1/2:0)

ff_tx_sop

ff_tx_eop

ff_tx_err

Figure 12: FIFO Transmit Interface - Four Back-to-Back Frames

The MAC/SWITCH can request to stop the data transfer, for example when the MAC/SWITCH

internal FIFOs are full. It then de-asserts the ready signal (ff_tx_rdy) 1.

To simplify the design of the DMA Controller, the MAC/SWITCH accepts up to two words after

ff_tx_rdy is de-asserted 2.

When the MAC/SWITCH re-asserts ff_tx_rdy 3, the DMA Controller can start sending new

data 4 at any time.

1

2

34

ff_tx_clk

ff_tx_rdy

ff_tx_wren

ff_tx_data(d:0)

ff_tx_mod(m:0)

ff_tx_sop

ff_tx_eop

ff_tx_err

Figure 13: FIFO Transmit Interface - Transfer with MAC/SWITCH Pause

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An error from the DMA Controller can be reported to the MAC/SWITCH by asserting ff_tx_err

at the end of a frame transfer to the FIFO 1. The frame is then transferred on the eGMII / GMII

interface with an Error control code during the frame transfer.

100 ns 200 ns 300ns 400ns

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1

ff_tx_clk

ff_tx_rdy

ff_tx_wren

ff_tx_data(31/63:0)

ff_tx_mod(1/2:0)

ff_tx_sop

ff_tx_eop

ff_tx_err

Figure 14: FIFO Transmit Interface - Errored Frame

11.4 FIFO Interface Receive Operation

On the FIFO Receive interface, the MAC/SWITCH initiates frame transfers to the DMA Controller. The interface masks the FIFO to the DMA Controller and the handshake protocol is limited to two

signals. The DMA Controller indicates it is ready to accept data by asserting (ff_rx_rdy) 1.

The MAC/SWITCH then starts transmitting data to the DMA Controller, whereby data is marked

with a valid signal (ff_rx_dval) 2.

The MAC/SWITCH asserts a start of frame signal (ff_rx_sop) at the beginning of a frame and

the end of frame (ff_rx_eop) with the very last word transfer 3. In addition, a word modulo

(ff_rx_mod(1/2:0)) and status information (ff_rx_err_stat(23:0)) is provided with the

last word of the frame 4.

To enable port arbitration within the DMA Controller, a section available indication (ff_rx_dsav)

is given, when a programmed number of words or a complete frame is available in the FIFO for

reading. Note that ff_rx_rdy is unrelated to the section available indication and it is valid to

assert ready even prior to the section available indication.

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750 ns 800 ns 850 ns 900 ns

ff_rx_clk

ff_rx_data 0000 000000 000000 00 00 000 000 00 000 0 00 00 00 00 00 00 00 00

ff_rx_sop

ff_rx_eop

ff_rx_mo d 000 110 000

ff_rx_err

ff_rx_err_s tat 0000 00 00 28 00 0000 00

ff_rx_rdy

ff_rx_dval

ff_rx_dsav

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1 2 3

4

Figure 15: FIFO Receive Interface - Single Frame Transfer

The DMA Controller can insert pauses during a frame transfer by de-asserting the ready signal

(ff_rx_rdy) at any time 1. The MAC/SWITCH samples the ready signal and stops sending data

after (but anything up to) four clock cycles 2.

When the DMA Controller is able to accept data again, the MAC/SWITCH restarts the data transfer

when the ready is reasserted by the user application 3. The MAC/SWITCH samples the ready

signal and starts driving data after four clock cycles 4.

850 ns 900 ns 950 ns 1 us

ff_rx_clk

ff_rx_data 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 4450EE1122334450 01013D000E112233 0807060504030201 100F0E0D0C0B0A09 1817161514131211 201F1E1D1C1B1A19 0000000000000000 2827262524232221 302F2E2D2C2B2A29 3837363534333231 FD2228CBF53B3A39 0000000000000000

ff_rx_sop

ff_rx_eop

ff_rx_mod 000 011 000

ff_rx_err

ff_rx_err_stat 000000 0 0 3 D0 0 000000

ff_rx_rdy

ff_rx_dval

ff_rx_dsav

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1 2 3 4

Figure 16: FIFO Receive Interface - Transfer with DMA Controller Pause

When an Ethernet frame is received with an error, the frame is transmitted to DMA Controller with

the frame error signal (ff_rx_err) asserted with the last word of the frame 1.

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Important Note: The ff_rx_err is valid only when ff_rx_eop is asserted. It may assert any time during the transfer and is ignored by the DMA Controller when ff_rx_eop is de-asserted.

In addition, the MAC/SWITCH provides a 24-bit error status word (ff_rx_err_stat(23:0)) that

gives an indication on the error source 2.

1020 ns 1040 ns 1060 ns 1080 ns

ff_rx_clk

ff_rx_data 0000000000000000 4450AA123456789C 01033F000E112233 0A09080706050403 1211100F0E0D0C0B 1A19181716151413 2221201F1E1D1C1B 2A29282726252423 3231302F2E2D2C2B 3A39383736353433 C13EEF3F3E3D3C3B 0000000000000000

ff_rx_sop

ff_rx_eop

ff_rx_mod 000 101 000

ff_rx_err

ff_rx_err_stat 000000 003F02 000000

ff_rx_rdy

ff_rx_dval

ff_rx_dsav

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Figure 17: FIFO Receive Interface – Frame with Errors

11.5 FIFO Interface Modulo Definition

11.5.1 32-bit Usage

ff_tx_mod[2:0] ff_rx_mod[2:0]

Valid Bytes

X00 ff_tx_data[31:0] ff_rx_data[31:0]

X01 ff_tx_data[7:0] ff_rx_data[7:0]

X10 ff_tx_data[15:0] ff_rx_data[15:0]

X11 ff_tx_data[23:0] ff_rx_data[23:0]

Table 8: Transmit/Receive 32-bit FIFO Interface word Modulo Definition

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11.5.2 64-bit Usage

ff_tx_mod[2:0] ff_rx_mod[2:0]

Valid Bytes

000 ff_tx_data[63:0] ff_rx_data[63:0]

001 ff_tx_data[7:0] ff_rx_data[7:0]

010 ff_tx_data[15:0] ff_rx_data[15:0]

011 ff_tx_data[23:0] ff_rx_data[23:0]

100 ff_tx_data[31:0] ff_rx_data[31:0]

101 ff_tx_data[39:0] ff_rx_data[39:0]

110 ff_tx_data[47:0] ff_rx_data[47:0]

111 ff_tx_data[55:0] ff_rx_data[55:0]

Table 9: Transmit/Receive 64-bit FIFO Interface word Modulo Definition

11.6 Frame Status

When frame reception terminates, the MAC/SWITCH writes a status word in a dedicated internal FIFO to report information and events to the DMA Controller per frame. The status is available with

each frame with the last word of the frame (ff_rx_eop asserted) and is presented on the

ff_rx_err_stat data bus.

Invalid length (Frame too long/short)

CRC-32 Error

Link error (code violation)

FIFO Overflow exception

Sequence error (e.g. local or remote fault)

Frame error character

VLAN Frame indication

Frame length/type field. This is a copy of the length/type field as it is found in the frame. Note, for VLAN frames the length/type as it is found 4-octets later in the frame is copied here.

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If any of the error conditions happened, in addition the ff_rx_err signal will be asserted together

with the frame's last word.

See below table for error meanings when an error condition occurs:

Table 10: Frame Status Word Bits

Bit # Name Description

0 LENGTH_ERROR

Set to ‘1’ if the frame has an invalid length. This can be a too short frame (less than 64 octets), a too long frame or a frame, which has a different amount of payload than specified in the frame's payload length field.

1 CRC_ERROR Set to ‘1’ if the frame was received with a CRC field that is invalid.

2 DEC_ERROR Set to '1' if a PHY/PCS decode error occurred

3 FIFO_OVERFLOW During frame reception a FIFO overflow was detected.

Note: The last bytes of the frame may contain arbitrary data.

4 FAULT_ERROR, SHORT FRAME

Set to '1' if a fault sequence (XGMII 0x9c) was detected while receiving the frame, or if the frame is a short frame (had less than 64 bytes on the line).

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12 Expansion IO-Register Interface

12.1 Overview

The control block handles the AHB-Lite memory bus, accessing the IO-Registers of the DMA Controller and also externally attached hardware to the external register interface bus. (See Section 5.2)

The following table shows the page offsets for the two pages. It illustrates the address offsets with-in the AHB-Lite memory map. The first 0x40000 addressing is allocated to external register bus space for attached hardware such as MACs. Then the next 0x10000 addressing space is reserved for the DMA Controller IO-Register map.

Table 11: Global Register Map (Control Block)

Offset Description

0x00000 to 0x3FFFF A 256Kbyte address range to allow addressing 16K 32-bit words at the external host interface.

Note: The bus for the external register interface will be mapped with address 0x00000 to 0x3FFFF incrementing by 4 (32-bit) for each register.

0x40000 to 0x4FFFF Internal registers of the DMA controller.

Note: Internally in the hardware, the local addresses get re-mapped back to 0x00000 for the internal DMA registers.

In the table (above) the externally connected hardware to the DMA Controller such as a MAC core for instance, would be visible at offset 0x00000. This external space ends at offset 0x3FFFF.

The DMA Controller itself has its own IO-Registers also (see next sub-section). These registers are visible at offset 0x40000 onwards until address offset 0x4FFFF.

To avoid confusion, the term offset in the (above) table refers to an offset with-in the AHB-Lite memory space. So for instance, a CPU may address the AHB-Lite controller at global memory address 0x3000000 in the overall CPU sub-system. Therefore, the External register space registers would be at 0x3000000.

The external register bus follows the same granularity mapping as the AHB-Lite addressing. By this, it implies that the external register address bus (top-level output signals ext_reg_addr[19:0]) MSB folow the AHB-Lite (top-level input signals haddr[19:0]).

Therefore, the first register will be at offset 0x0000, the second at 0x0004, third at 0x0008............

Do not connect the external register address bus (top-level output signals ext_reg_addr[19:0]) assuming that every increment of 1, accesses the next register if they are mapped every 4 bytes in the external MAC core. If the external MAC core for instance, does access its registers every byte in the register space, then you would connect Dma Controller top-level output signal ext_reg_addr[19:2] to MAC core reg_addr[17:0] – thus dividing by 4, or shifting right by 2.

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12.2 Register Write

When the DMA Controller writes a device register, it selects the device by putting the address on

the reg_addr pins and asserting reg_wr. Data and address is kept stable until the

MAC/SWITCH acknowledges by de-asserting reg_busy.

500 ns 505 ns 510 ns 515 ns

515016 ps

reg_clk

reg_rd

reg_wr

reg_addr 00 00

reg_data_in 00000000 AAAAAAAA 00000000

reg_data_out 00000000

reg_busy

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Figure 18: Register Write Timing Diagram

12.3 Register Read

When the DMA Controller reads a device register, it selects the device by putting the address on

the reg_addr pins and asserting the reg_rd. When data is available, the MAC/SWITCH de-

asserts reg_busy and the processor must read the data on the rising edge when reg_busy is de-

asserted.

500 ns 520 ns 540 ns 560 ns

reg_clk

reg_rd

reg_wr

reg_addr 00

reg_data_in 00000000

reg_data_out 00000000 00000001 00000000

reg_busy

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Figure 19: Register Read Timing Diagram

Note: Above figures are examples only. The de-assertion of reg_busy varies depending on which register is accessed and can take shorter or longer than shown above.

12.4 AHB-Lite Timeout for External Register Access

For the external register bus, as an extension of the AHB-Lite to the DMA Controller, there is a maximum of 20 memory bus wait states. After this, the hreadyout signal is re-asserted and a DMA severe error IRQ is generated (see Interrupt section later). An IRQ is used in this instance to indicate such an error as the AHB-Lite mechanism may have been compromised by the lockout with the possibility of IO Register internal to the DMA Controller being in-accessible. The IRQ should then force a recovery process which could reset the memory bus if necessary.

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13 Interrupt Channels

13.1 Overview

There are 32 interrupt source signals that can be handled by the DMA Controller hardware. They are configured and governed by their associated IO-Registers (next section). The first 16 sources are internally generated for use of the RX/TX DMA Controller cores. The last 16 are for external use beyond the DMA controller to inter-connecting hardware such as a MAC, SWITCH or PHY.

The resultant IRQ line (top-level DMA Controller output signal cpu_int) is therefore a single signal to the ARM host environment processor sub-system. In this way, the Linux software device driver can handle the entire different source events for the hardware deployed in one go as a single routine. This abstracts the need for the software environment to have to understand too much about the hardware as this DMA Controller serves other cores with both IRQ and IO Register mapping.

13.2 Interrupt Sources

Source Name Description

Receive RX Sources

0 Receive Coalescence

CH0+1

If IRQ enabled, when the last packet received and stored into an RX descriptor (of either CH0 or CH1) has elapsed for N milliseconds (derived from bus clock cycles upon synthesis). This is configured in the RX_COEL_TOUT Register.

This can be useful if RX IRQ is required to be minimal if large bursts or constant high levels of RX receive packet frames occur.

Reset Default: Disabled

1 RX CH0 Frame Completed

If IRQ enabled, when the RX Core has written the frame details into the required RX descriptor CH0 entry after the DMA transactions completed – this interrupt is triggered.

Reset Default: Disabled

2 RX CH1 Frame Completed

If IRQ enabled, when the RX Core has written the frame details into the required RX descriptor CH1 entry after the DMA transactions completed – this interrupt is triggered.

Reset Default: Disabled

3 RX FIFO Receive Data Available

If IRQ enabled, this interrupt signal originates from the connected FIFO RX (MAC or SWITCH) to indicate to the device driver software that DMA data is about to be transferred into physical memory. It reflects the rising edge of the ff_rx_dsav pin from the MAC/SWITCH. However, there is no way of acknowledging the ff_rx_sav source without losing interrupts so this option is only considered for lower rates of network traffic by a user space driver application through the Linux UIO mechanism.

Note: the device driver will not attempt to use this in its operation.

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Reset Default: Disabled

4 RX CH0 Empty Threshold

If IRQ enabled, this interrupt source is triggered if the number of received CH0 descriptor entries equals the RX_DESC_EMPTYTHRESHCH0 Register level after an RX CH0 descriptor entry been read.

Reset Default: Disabled

5 RX CH1 Empty Threshold

If IRQ enabled, this interrupt source is triggered if the number of received CH1 descriptor entries equals the RX_DESC_EMPTYTHRESHCH1 Register level after an RX CH1 descriptor entry been read.

Reset Default: Disabled

6 RX CH0 Full Threshold

If IRQ enabled, this interrupt source is triggered if the number of received CH0 descriptor entries equals the RX_DESC_FULLTHRESHCH0 Register level after an RX DMA packet frame has been received and stored in CH0.

Reset Default: Disabled

7 RX CH1 Full Threshold

If IRQ enabled, this interrupt source is triggered if the number of received CH1 descriptor entries equals the RX_DESC_FULLTHRESHCH1 Register level after an RX DMA packet frame has been received and stored in CH1.

Reset Default: Disabled

Transmit TX Sources

8 TX CH0 Descriptor Transfer

Completion

If IRQ enabled, and if the IRQ bit of the TX descriptor set, when the TX Core has written the frame status and results into the required TX descriptor CH0 entry after the DMA TX packet frame transaction completed – this interrupt is triggered.

Reset Default: Disabled

9 TX CH1 Descriptor Transfer

Completion

If IRQ enabled, and if the IRQ bit of the TX descriptor set, when the TX Core has written the frame status and results into the required TX descriptor CH1 entry after the DMA TX packet frame transaction completed – this interrupt is triggered.

Reset Default: Disabled

10 TX FIFO Ready for Data

If IRQ enabled, this interrupt signal originates from the connected FIFO TX (MAC or SWITCH) to indicate to the device driver software that DMA data is about to be transferred into physical memory. This bit relates to ff_tx_rdy pin from the MAC/SWITCH. However, there is no way of acknowledging the ff_tx_rdy source without losing interrupts so this option is only considered for lower rates of network traffic by a user space driver application through the Linux UIO mechanism.

Note: the device driver will not attempt to use this in its operation.

Reset Default: Disabled

11 TX CH0 Empty Threshold

If IRQ enabled, this interrupt source is triggered if the number of pending TX CH0 descriptor entries equals the

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TX_DESC_EMPTYTHRESHCH0 Register level after a TX CH0 descriptor entry been DMA transferred by the TX core.

Reset Default: Disabled

12 TX CH1 Empty Threshold

If IRQ enabled, this interrupt source is triggered if the number of pending TX CH1 descriptor entries equals the TX_DESC_EMPTYTHRESHCH1 Register level after a TX CH1 descriptor entry been DMA transferred by the TX core.

Reset Default: Disabled

13 TX CH0 Full Threshold

If IRQ enabled, this interrupt source is triggered if the number of pending TX CH0 descriptor entries equals the TX_DESC_FULLTHRESHCH0 Register level after a TX CH0 descriptor entry has been written to by the software device driver.

Reset Default: Disabled

14 TX CH1 Full Threshold

If IRQ enabled, this interrupt source is triggered if the number of pending TX CH1 descriptor entries equals the TX_DESC_FULLTHRESHCH1 Register level after a TX CH1 descriptor entry has been written to by the software device driver.

Reset Default: Disabled

15 Severe Hardware Error

If IRQ enabled, then this interrupt is generated by the DMA core hardware if a severe error has occurred. Only if AXI memory bus consistently fails will this IRQ activate. This IRQ is a last resort indicator designed to get immediate action by the device driver if necessary. The device driver must then decide how to reset the hardware.

Reset Default: Enabled

Additional Sources

31:16 Extended IRQ External MAC/SWITCH/PCS/PHY Interrupt Sources. There are16 interrupt source lines are available for use.

Table 12: Interrupt Sources

Note: Each source can be enabled and controlled individually.

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13.3 Input Design

The IRQ extended inputs (top-level DMA Controller input signals ext_reg_interrupts[15:0]) will have logic level edge detection that is configurable by bit settings in the INTERRUPT_EXT_CONFIG IO-Register. This will allow for either logic Low or logic HIGH edges to “trigger” the IRQ (top-level DMA Controller output signal cpu_int) onwards to the CPU host sub-system. In effect, the bit setting in the IO-Register will decide the polarity of the IRQ detection coming from the inter-connected additional IP core hardware blocks such as the MAC/SWITCH.

13.4 Acknowledgement Outputs

Any connected IRQ (to the top-level DMA Controller input signals ext_reg_interrupts[15:0]) from additional hardware such as a MAC/SWITCH can have the feature of an acknowledgement signal (top-level DMA Controller output signals ext_reg_intack[15:0]) feeding back from this DMA Controller core. This is provided for each and every one of the external IRQ connectors and just requires the user design to connect the signals and this will allow the external logic to decide if it wants to immediately re-trigger an interrupt or properly clear it depending on the operation of the hardware.

When an acknowledgement pulse is sent on ext_reg_intack[15:0], the signal is asserted for 3 AHB-Lite memory bus clock cycles then de-asserted. Each of the bits in ext_reg_intack[15:0] correspond to the bit IRQ meanings in ext_reg_interrupts[15:0].

The lower bits in the INTERRUPT_EXT_CONFIG IO Register control how the acknowledgement behaves. This can be either manual whereby the user software/device driver has to write to the INTERRUPT_PENDING register to ACK and clear the interrupt, or it can be automatic (See register definitions table later for setup of this mode).

For automatic mode, the ACK signal for the corresponding external interrupt line is sent as the interrupt is detected by the DMA Controller logic. This is, as with the manual ACK, an assertion for 3 AHB-Lite system bus clock cycles before being cleared.

When automatic acknowledgement is in use for a particular extended IRQ line, the corresponding pending bit is still set in the INTERRUPT_PENDING register for the user software/device driver to detect, but clears once that register is read. The ACK will have already been sent by hardware automatically to the external hardware IP core (top-level DMA Controller output signals ext_reg_intack[15:0]).

When manual acknowledgement is in use for a particular extended IRQ line, the corresponding pending bit is set in the INTERRUPT_PENDING register for the user software/device driver to detect, but does not clear until that bit is written to with a ‘1’. At this point the ACK is sent out on the acknowledgment signal as an assertion for 3 AHB-Lite system bus clock cycles.

Figure 20: External IRQ Acknowledgement Timing Diagram

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14 Register Interface (Control Block)

14.1 Overview

The control block handles the AHB-Lite memory bus, accessing the IO-Registers of the DMA Controller and also externally attached hardware to the external register interface bus. (See Section 5.2)

The following table shows the page offsets for the two pages. It illustrates the address offsets with-in the AHB-Lite memory map. The first 0x40000 addressing is allocated to external register bus space for attached hardware such as MACs. Then the next 0x10000 addressing space is reserved for the DMA Controller IO-Register map (See following Section 14.2).

Table 13: Global Register Map (Control Block)

Offset Description

0x00000 to 0x3FFFF A 256Kbyte address range to allow addressing 16K 32-bit words at the external host interface.

Note: The bus for the external register interface will be mapped with address 0x00000 to 0x3FFFF incrementing by 4 (32-bit) for each register.

0x40000 to 0x4FFFF Internal registers of the DMA controller.

Note: Internally in the hardware, the local addresses get re-mapped back to 0x00000 for the internal DMA registers.

For clarity, as a subset of the 0x40000-0x4FFFF DMA Controller internal IO-Register range, the following Register sections have been mentioned

0x40000 – 0x40007 DMA Version & Scratchpad Registers

0x40008 – 0x400FF DMA TX Registers

0x40100 – 0x401FF DMA RX Registers

0x40200 – 0x4FFFF DMA Interrupt & Miscellaneous Registers

In the table (above) the externally connected hardware to the DMA Controller such as a MAC core for instance, would be visible at offset 0x00000. This external space ends at offset 0x3FFFF.

The DMA Controller itself has its own IO-Registers also (see next sub-section). These registers are visible at offset 0x40000 onwards until address offset 0x4FFFF.

To avoid confusion, the term offset in the (above) table refers to an offset with-in the AHB-Lite memory space. So for instance, a CPU may address the AHB-Lite controller at global memory address 0x3000000 in the overall CPU sub-system. Therefore, the DMA Controller registers would be at 0x3040000 and therefore (following the next sub-section) the TX_STATUS register would be at 0x30400C then the following register after that 0x304010……………….

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14.2 DMA Controller/Status Registers

To control the functions within the DMA controller a set of local registers is defined.

The following table lists the offset with respect to the start of the register page (i.e. 0x40000, see above Section 14.1 Overview).

All offsets are given in distance of 32-bit. All registers are 32-bit wide and only 32-bit transactions are allowed.

Table 14: IO-Register Map

Offset (hex) from 0x40000

Name IO Description

Transmit Control & Configuration Registers

0x00 DMA_VERSION_REGISTER RO The Version register is divided into two 16-Bit fields:

• Bit 15:0: MorethanIP Core revision set to [0x1301]

• Bit 31:16: Customer specific revision, set during Core configuration

0x04 SCRATCH_REGISTER RW Write then read back values for test and diagnostic purposes. The scratch register provides a memory location available for the host processor to test device memory operation.

Default: 0

0x08 TX_GLOBAL_CONTROL

(See Bit Meaning Table below)

RW Transmit DMA Core TX Control Register.

0x0C TX_STATUS

(See Bit Meaning Table below)

RO TX DMA Core Live status bits of current progress.

0x10 TX_DESC_ CH0POINTER

Bit range [7:0]

RW Index pointer for the TX_DESC_CH0DATAn[n] registers.

Set this register to allow the below register fields read/write to the relevant TX descriptor table entry. Once written and operation completed, the software then sets the TX CH0 Write register to the appropriate value to start the TX CH0 DMA transfers.

Default: 0

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0x14 TX_DESC_ CH1POINTER

Bit range [7:0]

RW Index pointer for the TX_DESC_CH1DATAn[n] registers.

Set this register to allow the below register fields read/write to the relevant TX descriptor table entry. Once written and operation completed, the software then sets the TX CH1 Write register to the appropriate value to start the TX CH1 DMA transfers.

Default: 0

0x18 TX_DESC_CH0DATA1

Bit range [31:0]

RW Read/Write 32-bit 1st word of the TX

CH0 descriptor entry in IO-register space pointed to by above TX_DESC_ CH0POINTER register.

0x1A TX_DESC_CH0DATA2

Bit range [31:0]

RW Read/Write 32-bit 2nd word of the TX CH0 descriptor entry in IO-register space pointed to by above TX_DESC_ CH0POINTER register.

0x20 TX_DESC_CH0DATA3

Bit range [31:0]

RW Read/Write 32-bit 3rd word of the TX CH0 descriptor entry in IO-register space pointed to by above TX_DESC_ CH0POINTER register.

0x24 TX_DESC_CH0DATA4

Bit range [31:0]

RW Read/Write 32-bit 4th word of the TX CH0 descriptor entry in IO-register space pointed to by above TX_DESC_ CH0POINTER register.

0x28 TX_DESC_CH0DATA5

Bit range [31:0]

RW Read/Write 32-bit 5th word of the TX CH0 descriptor entry in IO-register space pointed to by above TX_DESC_ CH0POINTER register.

0x2C TX_DESC_CH0DATA6

Bit range [31:0]

RW Read/Write 32-bit 6th word of the TX CH0 descriptor entry in IO-register space pointed to by above TX_DESC_ CH0POINTER register.

0x30 TX_DESC_CH0DATA7

Bit range [31:0]

RW Read/Write 32-bit 7th word of the TX CH0 descriptor entry in IO-register space pointed to by above TX_DESC_ CH0POINTER register.

0x34 TX_DESC_CH1DATA1

Bit range [31:0]

RW Read/Write 32-bit 1st word of the TX

CH1 descriptor entry in IO-register space pointed to by above TX_DESC_ CH1POINTER register.

0x38 TX_DESC_CH1DATA2

Bit range [31:0]

RW Read/Write 32-bit 2nd word of the TX CH1 descriptor entry in IO-register space pointed to by above TX_DESC_ CH1POINTER register.

0x3C TX_DESC_CH1DATA3

Bit range [31:0]

RW Read/Write 32-bit 3rd word of the TX CH1 descriptor entry in IO-register space pointed to by above TX_DESC_ CH1POINTER register.

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0x40 TX_DESC_CH1DATA4

Bit range [31:0]

RW Read/Write 32-bit 4th word of the TX CH1 descriptor entry in IO-register space pointed to by above TX_DESC_ CH1POINTER register.

0x44 TX_DESC_CH1DATA5

Bit range [31:0]

RW Read/Write 32-bit 5th word of the TX CH1 descriptor entry in IO-register space pointed to by above TX_DESC_ CH1POINTER register.

0x48 TX_DESC_CH1DATA6

Bit range [31:0]

RW Read/Write 32-bit 6th word of the TX CH1 descriptor entry in IO-register space pointed to by above TX_DESC_ CH1POINTER register.

0x4C TX_DESC_CH1DATA7

Bit range [31:0]

RW Read/Write 32-bit 7th word of the TX CH1 descriptor entry in IO-register space pointed to by above TX_DESC_ CH1POINTER register.

0x50 TX_DESC_SIZE_CH0

Bit range [8:0]

Bits[31:9] set to zero

RO Set to the amount of the TX descriptor entries in the CH0 table.

This value is set in hardware derived from a synthesized option. Maximum value is 256.

Default: 0

0x54 TX_DESC_SIZE_CH1

Bit range [8:0]

Bits[31:9] set to zero

RO Set to the amount of the TX descriptor entries in the CH1 table.

This value is set in hardware derived from a synthesized option. Maximum value is 256.

Default: 0

0x58 TX_DESC_WR_INDEX_CH0

Bit range [7:0]

Bits[31:8] set to zero

RW Points to the next free TX CH0 entry to fill in. If this register is set larger than txch0defentries[7:0] it will modulae back to zero.

Important: This register is completely under the control of the software device driver. It must be incremented or changed when the device driver has completed its current entry into the TX CH0 descriptor table. This register is one of the controlling logic that starts the TX DMA process.

Default: 0

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0x5C TX_DESC_WR_INDEX_CH1

Bit range [7:0]

Bits[31:8] set to zero

RW Points to the next free TX CH1 entry to fill in. If this register is set larger than txch1defentries[7:0] it will modulae back to zero.

Important: This register is completely under the control of the software device driver. It must be incremented or changed when the device driver has completed its curent entry into the TX CH1 descriptor table. This register is one of the controlling logic that starts the TX DMA process.

Default: 0

0x60 TX_DESC_RD_INDEX_CH0

Bit range [7:0]

Bits[31:8] will read zero

RO Points to the next free TX CH0 entry with a packet frame to transmit TX for the DMA core. If this register reaches value defined in txch0defentries[7:0] it will modulae back to zero.

Important: This register is completely under the control of the DMA TX core.

Default: 0

0x64 TX_DESC_RD_INDEX_CH1

Bit range [7:0]

Bits[31:8] will read zero

RO Points to the next free TX CH1 entry with a packet frame to transmit TX for the DMA core. If this register reaches value defined in txch1defentries[7:0] it will modulae back to zero.

Important: This register is completely under the control of the DMA TX core.

Default: 0

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0x68 TX_DESC_CNT_INDEX_CH0

Bit range [8:0]

Bits[31:9] will read zero

RO Transmit Descriptor Table CH0 Used Entries Count.

TX CH0 Descriptor Table defined number of entries[7:0] (256 max) represents FULL (read and write should be equal) AND 0 represents EMPTY (read and write should be equal). All other values in between should ensure that read and write are NOT equal in value.

This register is arithmetically kept to the number of current TX CH0 descriptor entries filled in and pending TX DMA core transmission. It is effectively the wrapped difference between the write and read TX CH0 descriptor register values.

This register is one of the controlling logic that starts the TX DMA process.

0x6C TX_DESC_CNT_INDEX_CH1

Bit range [8:0]

Bits[31:9] will read zero

RO Transmit Descriptor Table CH1 Used Entries Count.

TX CH1 Descriptor Table defined number of entries[7:0] (256 max) represents FULL (read and write should be equal) AND 0 represents EMPTY (read and write should be equal). All other values in between should ensure that read and write are NOT equal in value.

This register is arithmetically kept to the number of current TX CH1 descriptor entries filled in and pending TX DMA core transmission. It is effectively the wrapped difference between the write and read TX CH1 descriptor register values.

This register is one of the controlling logic that starts the TX DMA process.

0x70 XSTAT_SIZE_TX

Bit range [2:0]

Bits[31:3] set to zero

RW Number of words relevant to the xstat sideband application.

The controller will only write this portion of the xstat field in the receive descriptor.

It could be reduced to save some descriptor access cycles if not all 4 entries are used in the current application.

Note: this setting does not change the size of a descriptor; it only limits which portion of the data is used.

Default: 4

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0x74 TX_DESC_FULLTHRESHCH0

Bit range [8:0]

Bits[31:9] set to zero

RW Arbitrarily set by software to indicate when a configured IRQ is made active when the register TX_DESC_CNT_INDEX_CH0 equals this value.

If the relevant IRQ is configured in the INTERRUPT_ENABLE register then as the TX CH0 descriptor entries that are pending TX DMA transmission equal then exceed this value, an IRQ FIFO FULL is generated if a TX CH0 descriptor entry has been written to by software.

This is useful for optimizing the software device driver IRQ ISR handling.

Default: 256

0x78 TX_DESC_FULLTHRESHCH1

Bit range [8:0]

Bits[31:9] set to zero

RW Arbitrarily set by software to indicate when a configured IRQ is made active when the register TX_DESC_CNT_INDEX_CH1 equals this value.

If the relevant IRQ is configured in the INTERRUPT_ENABLE register then as the TX CH1 descriptor entries that are pending TX DMA transmission equal then exceed this value, an IRQ FIFO FULL is generated if a TX CH1 descriptor entry has been written to by software.

This is useful for optimizing the software device driver IRQ ISR handling.

Default: 256

0x7C TX_DESC_EMPTYTHRESHCH0

Bit range [8:0]

Bits[31:9] set to zero

RW Arbitrarily set by software to indicate when a configured IRQ is made active when the register TX_DESC_CNT_INDEX_CH0 equals this value.

If the relevant IRQ is configured in the INTERRUPT_ENABLE register then as the TX CH0 descriptor entries that are pending TX DMA transmission equal then exceed this value, an IRQ FIFO EMPTY is generated if the TX DMA has transmitted a pending packet in the descriptor CH0.

This is useful for optimizing the software device driver IRQ ISR handling.

Default: 0

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0x80 TX_DESC_EMPTYTHRESHCH1

Bit range [8:0]

Bits[31:9] set to zero

RW Arbitrarily set by software to indicate when a configured IRQ is made active when the register TX_DESC_CNT_INDEX_CH1 equals this value.

If the relevant IRQ is configured in the INTERRUPT_ENABLE register then as the TX CH1 descriptor entries that are pending TX DMA transmission equal then exceed this value, an IRQ FIFO EMPTY is generated if the TX DMA has transmitted a pending packet in the descriptor CH1.

This is useful for optimizing the software device driver IRQ ISR handling.

Default: 0

0x84 –

0xFF

Reserved for TX Future Use N/A N/A

Receive Status & Configuration Registers

0x100 RX_GLOBAL_CONTROL

(See Bit Meaning Table below)

RW Receive DMA Core RX Control Register.

0x104 RX_STATUS

(See Bit Meaning Table below)

RO RX DMA Core Live status bits of current progress.

0x108 RX_DESC_MEMPOOL_CH0

Bit range [31:0]

RW Base 32-bit physical address of receive descriptor CH0 Ethernet frames in system memory. An allocation should be made to accommodate size of descriptor table total entries used * 2048 if globalframebuffermax[15:0] is less than 2048 or 65536 (64K) if this register is greater than 2K.

Warning: setup before use to avoid memory page faults.

Default: 0

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0x10C RX_DESC_MEMPOOL_CH1

Bit range [31:0]

RW Base 32-bit physical address of transmit descriptor CH1 Ethernet frames in system memory. An allocation should be made to accommodate size of descriptor table total entries used * 2048 if globalframebuffermax[15:0] is less than 2048 or 65536 (64K) if this register is greater than 2K.

Warning: setup before use to avoid memory page faults.

Default: 0

0x110 RX_DESC_ CH0POINTER

Bit range [7:0]

RW Index pointer for the RX_DESC_CH0DATAn[n] registers.

Set this register to allow the below register fields read/write to the relevant RX descriptor table entry. Once read and operation completed, the software then sets the RX CH0 Read register to the appropriate value to acknowledge the device driver has auctioned the previous TX CH0 DMA transfers.

Default: 0

0x114 RX_DESC_ CH1POINTER

Bit range [7:0]

RW Index pointer for the RX_DESC_CH1DATAn[n] registers.

Set this register to allow the below register fields read/write to the relevant RX descriptor table entry. Once read and operation completed, the software then sets the RX CH1 Read register to the appropriate value to acknowledge the device driver has auctioned the previous TX CH1 DMA transfers.

Default: 0

0x118 RX_DESC_CH0DATA1

Bit range [31:0]

RW Read/Write 32-bit 1st word of the RX

CH0 descriptor entry in IO-register space pointed to by above RX_DESC_ CH0POINTER register.

0x11C RX_DESC_CH0DATA2

Bit range [31:0]

RW Read/Write 32-bit 2nd word of the RX CH0 descriptor entry in IO-register space pointed to by above RX_DESC_ CH0POINTER register.

0x120 RX_DESC_CH0DATA3

Bit range [31:0]

RW Read/Write 32-bit 3rd word of the RX CH0 descriptor entry in IO-register space pointed to by above RX_DESC_ CH0POINTER register.

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0x124 RX_DESC_CH0DATA4

Bit range [31:0]

RW Read/Write 32-bit 4th word of the RX CH0 descriptor entry in IO-register space pointed to by above RX_DESC_ CH0POINTER register.

0x128 RX_DESC_CH0DATA5

Bit range [31:0]

RW Read/Write 32-bit 5th word of the RX CH0 descriptor entry in IO-register space pointed to by above RX_DESC_ CH0POINTER register.

0x12C RX_DESC_CH0DATA6

Bit range [31:0]

RW Read/Write 32-bit 6th word of the RX CH0 descriptor entry in IO-register space pointed to by above RX_DESC_ CH0POINTER register.

0x130 RX_DESC_CH1DATA1

Bit range [31:0]

RW Read/Write 32-bit 1st word of the RX

CH1 descriptor entry in IO-register space pointed to by above RX_DESC_ CH1POINTER register

0x134 RX_DESC_CH1DATA2

Bit range [31:0]

RW Read/Write 32-bit 2nd word of the RX CH1 descriptor entry in IO-register space pointed to by above RX_DESC_ CH1POINTER register.

0x138 RX_DESC_CH1DATA3

Bit range [31:0]

RW Read/Write 32-bit 3rd word of the RX CH1 descriptor entry in IO-register space pointed to by above RX_DESC_ CH1POINTER register.

0x13C RX_DESC_CH1DATA4

Bit range [31:0]

RW Read/Write 32-bit 4th word of the RX CH1 descriptor entry in IO-register space pointed to by above RX_DESC_ CH1POINTER register.

0x140 RX_DESC_CH1DATA5

Bit range [31:0]

RW Read/Write 32-bit 5th word of the RX CH1 descriptor entry in IO-register space pointed to by above RX_DESC_ CH1POINTER register.

0x144 RX_DESC_CH1DATA6

Bit range [31:0]

RW Read/Write 32-bit 6th word of the RX CH1 descriptor entry in IO-register space pointed to by above RX_DESC_ CH1POINTER register.

0x148 RX_DESC_SIZE_CH0

Bit range [7:0]

Bits[31:8] set to zero

RO Set to the amount of the RX descriptor entries in the CH0 table.

This value is set in hardware derived from a synthesized option. Maximum value is 256.

Default: 0

0x14C RX_DESC_SIZE_CH1

Bit range [7:0]

Bits[31:8] set to zero

RO Set to the amount of the RX descriptor entries in the CH1 table.

This value is set in hardware derived from a synthesized option. Maximum value is 256.

Default: 0

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0x150 RX_DESC_WR_INDEX_CH0

Bit range [7:0]

Bits[31:8] will read zero

RO Points to the next available RX CH0 entry empty to receive and store the reference of a packet frame from the RX DMA core. If this register reaches value defined in rxch0defentries[7:0] it will modulae back to zero.

Important: This register is completely under the control of the DMA RX core. This register is one of the controlling logic that indicates to the software device driver of an RX DMA process.

Default: 0

0x154 RX_DESC_WR_INDEX_CH1

Bit range [7:0]

Bits[31:8] will read zero

RO Points to the next available RX CH1 entry empty to receive and store the reference of a packet frame from the RX DMA core. If this register reaches value defined in rxch1defentries[7:0] it will modulae back to zero.

Important: This register is completely under the control of the DMA RX core. This register is one of the controlling logic that indicates to the software device driver of an RX DMA process.

Default: 0

0x158 RX_DESC_RD_INDEX_CH0

Bit range [7:0]

Bits[31:8] set to zero

RW Points to the next free RX CH0 entry to receive RX from the DMA core if a packet frame available (RX_DESC_CNT_INDEX_CH0 > 0).

If this register is set larger than rxch0defentries[7:0] it will modulae back to zero.

Important: This register is completely under the control of the software device driver. It must be incremented or changed when the device driver has completed its current entry into the RX CH0 descriptor table.

Default: 0

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0x15C RX_DESC_RD_INDEX_CH1

Bit range [7:0]

Bits[31:8] set to zero

RW Points to the next free RX CH1 entry to receive RX from the DMA core if a packet frame available (RX_DESC_CNT_INDEX_CH1 > 0).

If this register is set larger than rxch1defentries[7:0] it will modulae back to zero.

Important: This register is completely under the control of the software device driver. It must be incremented or changed when the device driver has completed its current entry into the RX CH1 descriptor table.

Default: 0

0x160 RX_DESC_CNT_INDEX_CH0

Bit range [8:0]

Bits[31:9] will read zero

RO Receive Descriptor Table CH0 Used Entries Count.

rxch0defentries[7:0] (256 max) represents FULL (read and write should be equal) AND 0 represents EMPTY (read and write should be equal). All other values in between should ensure that read and write are NOT equal in value.

This register is arithmetically kept to the number of current RX CH0 descriptor entries filled in by the RX DMA core transmition waiting to be read by the software device driver during interrupt service routine. It is effectively the wrapped difference between the read and write RX CH0 descriptor register values.

Note: This register is one of the controlling logic that indicates to the software device driver of an RX DMA process.

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0x164 RX_DESC_CNT_INDEX_CH1

Bit range [8:0]

Bits[31:9] will read zero

RO Receive Descriptor Table CH1 Used Entries Count.

rxch1defentries[7:0] (256 max) represents FULL (read and write should be equal) AND 0 represents EMPTY (read and write should be equal). All other values in between should ensure that read and write are NOT equal in value.

This register is arithmetically kept to the number of current RX CH1 descriptor entries filled in by the RX DMA core transmition waiting to be read by the software device driver during interrupt service routine. It is effectively the wrapped difference between the read and write RX CH1 descriptor register values.

Note: This register is one of the controlling logic that indicates to the device driver of an RX DMA process.

0x168 XSTAT_SIZE_RX

Bit range [2:0]

Bits[31:3] will read zero

RW Number of words relevant to the xstat sideband application.

The controller will only read this portion of the xstat field from the transmit descriptor.

It but could be reduced to save some descriptor access cycles if not all 4 entries are used in the current application.

Note: this setting does not change the size of a descriptor; it only limits which portion of the data is used.

Default: 4

0x16C RX_DESC_FULLTHRESHCH0

Bit range [8:0]

Bits[31:9] set to zero

RW Arbitrarily set by software to indicate when a configured IRQ is made active when the register RX_DESC_CNT_INDEX_CH0 equals this value.

If the relevant IRQ is configured in the INTERRUPT_ENABLE register then as the RX CH0 descriptor entries that are pending RX DMA transmission equal then exceed this value, an IRQ FIFO FULL is generated if an RX DMA packet frame has been received and stored in CH0.

This is useful for optimizing the software device driver IRQ ISR handling.

Default: 256

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0x170 RX_DESC_FULLTHRESHCH1

Bit range [8:0]

Bits[31:9] set to zero

RW Arbitrarily set by software to indicate when a configured IRQ is made active when the register RX_DESC_CNT_INDEX_CH1 equals this value.

If the relevant IRQ is configured in the INTERRUPT_ENABLE register then as the RX CH1 descriptor entries that are pending RX DMA transmission equal then exceed this value, an IRQ FIFO FULL is generated if an RX DMA packet frame has been received and stored in CH1.

This is useful for optimizing the software device driver IRQ ISR handling.

Default: 256

0x174 RX_DESC_EMPTYTHRESHCH0

Bit range [8:0]

Bits[31:9] set to zero

RW Arbitrarily set by software to indicate when a configured IRQ is made active when the register RX_DESC_CNT_INDEX_CH0 equals this value.

If the relevant IRQ is configured in the INTERRUPT_ENABLE register then as the RX CH0 descriptor entries that are pending RX DMA transmission equal then exceed this value, an IRQ FIFO EMPTY is generated if an RX CH0 descriptor entry been read.

This is useful for optimizing the software device driver IRQ ISR handling.

Default: 0

0x178 RX_DESC_EMPTYTHRESHCH1

Bit range [8:0]

Bits[31:9] set to zero

RW Arbitrarily set by software to indicate when a configured IRQ is made active when the register RX_DESC_CNT_INDEX_CH1 equals this value.

If the relevant IRQ is configured in the INTERRUPT_ENABLE register then as the RX CH1 descriptor entries that are pending RX DMA transmission equal then exceed this value, an IRQ FIFO EMPTY is generated if an RX CH1 descriptor entry been read.

This is useful for optimizing the software device driver IRQ ISR handling.

Default: 0

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0x17C RX_COEL_TOUT

Bit range [7:0]

Bits[31:8] set to zero

RW If the RX Coalescence IRQ is enabled then this register holds the value in milli-seconds of the timeout.

If set to ‘0’, the IRQ acts as a pure normal RX interrupt with no timeout which is wasteful and unnecessary. Therefore configuration of this value to non-zero is useful.

Default: 0

0x180 –

0x1FF

Reserved for RX Future Use N/A N/A

Interrupt & Miscellaneous Registers

0x200 GLOBAL_FRAMEBUFFER_MAX

Bit range [15:0]

Bits[31:16] set to zero

RW Maximum number of bytes (including the CRC) of a received or transmitted Ethernet frame allowed before further data is discarded from the FIFO interface. This is effectively a limit to the allowed RX/TX frame size and politely discards further bytes that aer unwanted until the end of the frame (ff_rx_eop or ff_tx_eop).

Default: 1522

Note: up to 65Kbytes possible to support “jumbo frames”.This causes the descriptor table mempool allocations for RX [CH0] & [CH1] To be 64K in SDRAM and not 2K.

0x204 INTERRUPT_STATUS RO Interrupt status. Indicates internal status of interrupt sources.

Note: This register only shows the status, not if actually an interrupt is pending. The status bits are then masked by the mask register to create the pending interrupt indications.

Refer to Section 13 Interrupt Channels

0x208 INTERRUPT_ENABLE RW Interrupt enable mask. Only an enabled interrupt will cause the physical interrupt pin to assert.

Refer to Section 13 Interrupt Channels

Default: 0 (ALL disabled)

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0x20C INTERRUPT_PENDING RW Interrupts pending and acknowledge.

The pending register will show the currently enabled and active interrupts.

A write to the register with the corresponding bit set to 1 is used to acknowledge and clear a pending interrupt indication.

Refer to Section 13 Interrupt Channels

0x210 INTERRUPT_EXT_CONFIG RW Extended Interrupt Line Configuration.

Bits 31:16 represent the polarity of the 16 extended inputs. If each corresponding bit set to ‘1’ then the IRQ will be generated to the CPU sub-system if the extended input is asserted to logic HIGH (positive edge). If a bit is set to ‘0’, then its corresponding extended input will only forward an IRQ if at logic LOW (negative edge).

Bits 15:0 represent the settings of the AUTO acknowledgement. Each bit represents one of the 16 extended Interrupt ACK lines back to the connected hardware such as a MAC, PHY or SWITCH.

If set to ‘1’, then the ACK line corresponding to the activated input, is asserted for 3 AHB-Lite memory bus clock cycles to acknowledge the IRQ automatically. This does not require any intervention from the INTERRUPT_PENDING register.

If set to ‘0’, then the ACK line corresponding to the activated input, is ONLY asserted for 3 AHB-Lite memory bus clock cycles to acknowledge the IRQ when the corresponding pending bit in the INTERRUPT_PENDING register is written with a ‘1’ by the device driver or user software through UIO.

Default: 0xFFFF0000

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0x214 AXIMASTER_MAXBURST

Bit range [4:0]

Bits[31:5] set to zero

RW Master AXI Maximum Burst Size

Value in bus width transactions to be able to configure a Read or Write AXI Burst. The DMA Master controls this to the connected sub-system AXI Slave.

A bust of 16 is the maximum allowed by the AMBA AXI Specification. However, this can be set from 1 – 16 as allowed values to cater for differing hardware capabilities.

Default: 0x01

0x218 AXIMASTER_TIMEOUT

Bit range [15:0]

Bits[31:16] set to zero

RW [Bits 7:0] Master AXI Response Timeout

Value in bus clock cycles to wait for <arready>, <rvalid>, <bvalid>, <awready> and <wready> to be asserted to indicate an AXI bus response from the connected Slave module.

If this value does cause a timeout due to a lack of AXI response, then an error for the TX or RX descriptor is announced.

Note: This value is multiplied by 256 internally with-in the hardware. Thus a value of 255 represents 65280 clock cycles from the memory bus.

[Bits 15:8] Master AXI Burst Hold-off

Value in clock cycles to wait between AXI burst events. This is zero normally but in crowded processor sub-systems, this is useful to allow for bus hold off where only basic round-robin arbitration occurs.

Note: Zero to disable

Default: 0x0080 (overall 16-bits)

0x21C – 0xFFFF

Reserved (NOT USED) N/A N/A

Note: A full list of the Interrupt sources is in the previous Section 13 Interrupt Channels.

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14.3 TX_GLOBAL_CONTROL Register

Table 15: TX_GLOBAL_CONTROL Register (Offset 0x00)

Bit# Bit Name Description

0 Global TX DMA enable When set to ‘0’ (Reset value) the TX DMA Core is disabled, when set to ‘1’ the TX DMA Core is functional and can be controlled and interfaces to the connected FIFO. Register IO changes and configuration can be made when set to ‘0’ LOW.

1 Global TX DMA reset Write a ‘1’ to reset the TX DMA core. This is valid whether core is enabled or disabled. It is advised to reset then configure settings followed by enabling the cores and the decriptors lastly. (Global TX DMA enable).

This is a self-clearing bit. If this bit is asserted during an operation, a DMA operation will try to complete or timeout first so that the AXI burst process does not halt mid-way through.

After reset, this bit reads ‘0’.

2 Global TX CH0 Descriptor enable

When set to ‘0’ (Reset value) the TX DMA CH0 Descriptor table is disabled and does not interpret and acknowledge software stored TX frame. When set to ‘1’ the TX DMA CH0 Descriptor table is enabled and functional.

3 Global TX CH1 Descriptor enable

When set to ‘0’ (Reset value) the TX DMA CH1 Descriptor table is disabled and does not interpret and acknowledge software stored TX frame. When set to ‘1’ the TX DMA CH1 Descriptor table is enabled and functional.

4 Global AXI RMW enable AXI Slave DDR bridge - Read-Modify-Write enable. When set to ‘1’, this forces any interconnected external hardware that is connected on the AXI bus to write to the destination device storing the memory to use Read-Modify-Write mechanism. This is advised and documented with the specific vendor and processor sub-system. When set to ‘0’ (Reset value) this feature is disabled and conventional writing occurs.

6:5 Slave AXI access Sets the mode of the AXI in the DMA Controller to behave according to the requirements of the Slave AXI interconnected sub-system.

00 = Normal Access

01 = Exclusive Access

10 = Locked Access

11 = Reserved

After reset, this field reads 00.

31:7 Reserved (set to zero) N/A

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14.4 TX_STATUS Register

Table 16: TX_STATUS Register (Offset 0x04)

Bit# Bit Name Description

0 TX DMA CH0 start This bit is asserted to ‘1’ (if the origin of the request from a current TX Descriptor entry is CH0) and the TX DMA core is preparing the transfer list. The bit is cleared once the TX DMA transfer has actually started.

1 TX DMA CH1 start This bit is asserted to ‘1’ (if the origin of the request from a current TX Descriptor entry is CH1) and the TX DMA core is preparing the transfer list. The bit is cleared once the TX DMA transfer has actually started.

2 TX DMA CH0 completed This bit is asserted to ‘1’ (if the origin of the request from a current TX Descriptor entry is CH0) and the TX DMA core has reached transfer completion OR failure. The bit is cleared once the TX DMA starts a next transaction. If necessary a failure breakdown of reasons why not successful are placed in the status bits of the associated descriptor entry.

3 TX DMA CH1 completed This bit is asserted to ‘1’ (if the origin of the request from a current TX Descriptor entry is CH1) and the TX DMA core has reached transfer completion OR failure. The bit is cleared once the TX DMA starts a next transaction. If necessary a failure breakdown of reasons why not successful are placed in the status bits of the associated descriptor entry.

4 TX DMA CH0 busy Set to ‘1’ for the entire duration of the DMA sequence if the origin of the request is CH0. This bit is only cleared after the descriptor entry has been written back and any IRQ has been generated if necessary. This can be used to track a TX transmission exhaustively when not using IRQ signals as a preferred method of software control.

5 TX DMA CH1 busy Set to ‘1’ for the entire duration of the DMA sequence if the origin of the request is CH1. This bit is only cleared after the descriptor entry has been written back and any IRQ has been generated if necessary. This can be used to track a TX transmission exhaustively when not using IRQ signals as a preferred method of software control.

6 ff_tx_rdy state The live real-time state of the ff_tx_rdy pin from the connected MAC/SWITCH FIFO to the DMA TX core.

Note: Useful for debuginig purposes.

7 ff_tx_septy state The live real-time state of the ff_tx_septy pin from the connected MAC/SWITCH FIFO to the DMA TX core.

Note: Useful for debuginig purposes.

31:8 Reserved (read as zero) N/A

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14.5 RX_GLOBAL_CONTROL Register

Table 17: RX_GLOBAL_CONTROL Register (Offset 0x100)

Bit# Bit Name Description

0 Global RX DMA enable When set to ‘0’ (Reset value) the RX DMA Core is disabled, when set to ‘1’ the RX DMA Core is functional and can be controlled and interfaces to the connected FIFO. Register IO changes and configuration can be made when set to ‘0’ LOW.

1 Global RX DMA reset Write a ‘1’ to reset the RX DMA core. This is valid whether core is enabled or disabled. It is advised to reset then configure settings followed by enabling the cores and the decriptors lastly. (Global RX DMA enable).

This is a self-clearing bit.

If this bit is asserted during an operation, a DMA operation will try to complete or timeout first so that the AXI burst process does not halt mid-way through.

After reset, this bit reads ‘0’.

2 Global RX CH0 Descriptor enable

When set to ‘0’ (Reset value) the RX DMA CH0 Descriptor table is disabled and does not insert Ethernet frame references when the FIFO receives data. Infact it is discarded if the destined Descriptor table is disabled. When set to ‘1’ the RX DMA CH0 Descriptor table is enabled and functional.

3 Global RX CH1 Descriptor enable

When set to ‘0’ (Reset value) the RX DMA CH1 Descriptor table is disabled and does not insert Ethernet frame references when the FIFO receives data. Infact it is discarded if the destined Descriptor table is disabled. When set to ‘1’ the RX DMA CH1 Descriptor table is enabled and functional.

4 RX Descriptor FULL policy When set to ‘1’, if either of CH0 or CH1 RX descriptor tables are FULL to receive new ethernet packet frames, the RX DMA core will use the entries in the free table to store the incomming data. This is irrespective of whether the data was meant for that Channel priority or not. Only when BOTH tables are full will the ff_rx_rdy signal to the MAC/SWITCH be de-asserted to prevent further packets being recevied.

However, when set to ‘0’ (Reset value) if either of CH0 or CH1 RX descriptor tables are FULL to receive new ethernet packet frames, the ff_rx_rdy signal to the MAC/SWITCH be de-asserted to prevent further packets being recevied. This is irrespetive of whether the other table still has some space or not.

Note: for either setting, once the FULL condition ceases, ff_rx_rdy is asserted once again.

31:4 Reserved (set to zero) N/A

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14.6 RX_STATUS Register

Table 18: RX_STATUS Register (Offset 0x104)

Bit# Bit Name Description

0 RX DMA CH0 start This bit is asserted to ‘1’ (if the origin of the request from the MAC/SWITCH FIFO is CH0) and the RX DMA core is preparing the transfer of the FIFO receving packet frame. The bit is cleared once the RX DMA transfer has actually started.

1 RX DMA CH1 start This bit is asserted to ‘1’ (if the origin of the request from the MAC/SWITCH FIFO is CH1) and the RX DMA core is preparing the transfer of the FIFO receving packet frame. The bit is cleared once the RX DMA transfer has actually started.

2 RX DMA CH0 completed This bit is asserted to ‘1’ (if the origin of the request from the MAC/SWITCH FIFO is CH0) and the RX DMA core has reached transfer completion OR failure. The bit is cleared once the RX DMA transfer has started to process a next DMA transfer. If necessary a failure breakdown of reasons why not successful are placed in the status bits of the associated descriptor entry.

3 RX DMA CH1 completed This bit is asserted to ‘1’ (if the origin of the request from the MAC/SWITCH FIFO is CH1) and the RX DMA core has reached transfer completion OR failure. The bit is cleared once the RX DMA transfer has started to process a next DMA transfer. If necessary a failure breakdown of reasons why not successful are placed in the status bits of the associated descriptor entry.

4 RX DMA CH0 busy Set to ‘1’ for the entire duration of the DMA sequence if the origin of the request from the MAC/SWITCH FIFO is CH0. This bit is only cleared after the RX descriptor entry has been written and any IRQ has been generated if necessary. This can be used to track an RX receive exhaustively when not using IRQ signals as a preferred method of software control.

5 RX DMA CH1 busy Set to ‘1’ for the entire duration of the DMA sequence if the origin of the request from the MAC/SWITCH FIFO is CH1. This bit is only cleared after the RX descriptor entry has been written and any IRQ has been generated if necessary. This can be used to track an RX receive exhaustively when not using IRQ signals as a preferred method of software control.

6 ff_rx_dsav state The live real-time state of the ff_rx_dsav pin from the connected MAC/SWITCH FIFO to the DMA RX core.

Note: Useful for debuginig purposes.

31:7 Reserved (read as zero) N/A

14.7 Additional Information

The registers are independently split into RX and TX functionality. Even where there is an abundance of bit space in control/status and field registers, temptation to condense the number of registers to a smaller amount has been resisted.

The large amount of spare unused register I/O space is deliberate for future functionality. The spare bits in most of the registers are for future use also.

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15 References

1. IEEE 802.3 2008 Edition

2. IEEE 802.3ae

3. RFC2665, Definitions of Managed Objects for the Ethernet-like Interface Type, www.ietf.org

4. RFC2863, The interfaces Group MIB, June 2000, www.ietf.org

6. RFC2819, Remote Network Monitoring (RMON) MIB, May 2000, www.ietf.org

7. IEEE 802.3az, MAC Amendment: Energy Efficient Ethernet (EEE)

Also additionally:

A. Actel SmartFusion2 MSS User Guide

B. Actel SmartFusion2 CortexM3 User Guide

C. AMBA AXI Protocol Specification Document

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16 Contact

MorethanIP GmbH

E-Mail : [email protected]

Internet : www.morethanip.com

Europe

Muenchner Str. 199

D-85757 Karlsfeld

Germany

Tel : +49 (0) 8131 333939 0

FAX : +49 (0) 8131 333939 1

Nine Ways Research & Development Ltd

E-Mail : [email protected]

Internet : www.nineways.co.uk

UK

Unit A.3, iDCentre, Lathkill House, rtc Business Park

London Road, Derby. DE24 8UP

United Kingdom

Tel : +44 (0) 1332 258847

FAX : +44 (0) 1332 258823

Table 19: Contact Information

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17 Document History

Document Change Notices (DCO)

Version Description Created/Changed By Date

Version 1.0 Initial Release according to

Version .0 Paul Bates: Nine Ways 31st October 2013

Version 1.1 Updated text and section

pertaining to PTP-1588

functionality

Paul Bates: Nine Ways 20th January 2015

Copyright © MorethanIP GmbH 2013. All Rights Reserved.

Table 20: Document History Entry Log