DK4000-C167 User Manual - Digikey
Transcript of DK4000-C167 User Manual - Digikey
1/27October 2001
DK4000-C167USER MANUAL
Development Kit for PSD4000 and C167
CONTENTS
■ A COUPLE OF DEFINITIONS
■ HARDWARE
■ SOFTWARE
■ DETAILED DESCRIPTIONS
■ OTHER BOARD FEATURES
– Step-By-Step Instruc-tions for ISP Program-ming
■ USING DK4000 AS A DEVELOPMENT PLATFORM FOR C167CR USERS
– Concept
– Downloading to the De-velopment Board
– JTAG - ISP
■ 167 DESIGN OVERVIEW
– Memory Swapping in thePSD
– What really happens
– Creating your own IAPcode bundle
■ REFERENCES
■ APPENDIX
Congratulations on purchasing ST's DK4000 Development kit.The DK4000 (110 or 220 volt version) is a low cost kit for eval-uating the PSD4000 series of Flash Programmable SystemDevices called PSDs. The DK4000 kit is extremely versatile,and can be used in several different modes. It can be used todemonstrate the PSD4000's capability of JTAG In-System Pro-grammability (ISP). Once initial code is resident in the PSD, theprogram code can be updated while the MCU is running, calledIn-Application Programming (IAP). Also, Infineon C167CRfamily users can utilize the DK4000 as an evaluation platformfor code development.
The DK4000 – C167 Development Board is specific to the Infi-neon C167CR micro-controller family. However, other prolifer-ation boards will be available. Check the website atwww.st.com/psd as to availability.
A COUPLE OF DEFINITIONS
In-System Programming (ISP) - A JTAG interface (IEEE 1149.1compliant) is included on the PSD enabling the entire device tobe rapidly programmed while soldered to the circuit board(Main Flash memory, Secondary Boot Flash memory, the PLDand all configuration areas). This requires no MCU participa-tion, so the PSD can be programmed or reprogrammed any-time, anywhere, even while completely blank. The MCU iscompletely bypassed.
In-Application Programming (IAP) – Since two independentFlash memory arrays are included in the PSD, the MCU can ex-ecute code from one memory while erasing and programmingthe other. Robust product firmware updates in the field are pos-sible over any communication channel (a few examples areCAN, Ethernet, UART, J1850) using this unique architecture.For IAP, all code is updated through the MCU.
HARDWARE
■ PSD4000 Flash PSD (Programmable System Device) - see www.st.com/psd for data sheet. PSD4135G2 - 4Mbit Main Flash memory (512Kx8), 256Kbit Boot Flash memory (32Kx8), 64Kbit SRAM (8Kx8)
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■ Eval/Demo Board with C167CR or other MCU, LCD Display, JTAG and UART ports for ISP/IAP
■ FlashLINK JTAG ISP Programmer (uses PC’s parallel port)
■ Straight through serial cable (Male-Female)
■ Power Supply
SOFTWARE
To ensure you have the latest versions, check the website often.
■ PSDsoft Express - Point and Click Windows programming development software. This will install to it’s own directory.
– MCU Selection by manufacturer and part number
– Graphical definition of pin functions
– Easy creation of memory map
– JTAG ISP Programming.
■ Downloadable demonstration software
– Visit the development tools section of ST PSM product division website at www.st.com/psd to down-load the file 167_disk.zip.
The development boards ship with the hardware test (hwtest.obj) file already resident. A detailed descrip-tion of this software bundle is included in Appendix B.
The following table is a specific listing of the files contained in the 167_disk.zip file including the directoryto which the file automatically extracts them.
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Table 1. Listing of the files and destinations in 167_disk.zip
Note: 1. Hex file carries the extension *.h86 from the Keil tools.2. Infineon Dave 2.0 cd was used in these projects3. Keil compiler version is 4.03 or later. See readme file for particulars.
Directory Files Description
root demo10.h86 alternate firmware to load to demonstrate IAP
iap.mmf memory map file for PSDload
iap.obj object file to load directly into PSD
iap.psd configuration file for psdload
hwtest-167
166p_hwt_10s_.zip contains all PSDsource files
166c_hwt_10s_.zip contains all c level code files
readme.txt late breaking information
hwtest.obj object file to load directly into PSD
demo-167
u67eemop10_.zip contains all PSD source files
u67democ10_.zip contains all c level code filed
readme.txt late breaking information
a16xbhe.obj object file to load directly into PSD
iap_167
166p10iap.zip contains all PSD source files
166c10iap.zip contains all c level code files
readme.txt late breaking information
iap.mmf memory map file for PSDload
iap.obj object file to load directly into PSD
demo_iap_167
166c10demo.zip contains all c level code files
demo10.h86 alternate firmware to load to demonstrate IAP
readme.txt late breaking information
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DETAILED DESCRIPTIONS
Figure 1. DK4000 Development Board
The following features are included in the development board and shown graphically in the above figure.
■ Display - A two line by 16 character LCD display is included on the Development Board.
■ Power switch
■ UART Serial Port(female) - Connected to MCU serial port; used for In-Application Programming (IAP)
■ Infineon C167CR or other MCU
■ PSD4000 software - The PSD4000 is programmed with C167CR demonstration code. User can program alternative programs via JTAG ISP.
■ JTAG programming Port - Used in conjunction with FlashLINK programmer for ISP.
■ Reset Button - For resetting the MCU and PSD
■ Pads for additional SRAM - The resident PSD4000 contains 8KB SRAM. This site is for additional SRAM.
OTHER BOARD FEATURES
Other features of the DK4000 board are listed below. These elements unpopulated to provide lowest costto the user.
■ Provision for C167CR boot elements are provided with JP5, 6 and 7.
■ Provision for chaining JTAG connector is provided in P2 and JP2.
■ Provision for C167CR OWE control is provided in JP8
■ Provision for an analog Vref input is provided in JP9
Serial Port
JTAG Programming port
Provision for chaining port
PSD4135G2
SRAM provision
Power switch
LED’s
DC Power Input
Reset Button4 position
DIP switch
LCD contrast
adjustment
2x16 character
LCD display
Expansion
Ports
ST10 or
Infineon
C167CR
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■ Provision for off expansion is provided by board connectors suitable for 0.025 square posts
■ Provision for 9v battery input is provided near power connector (solder pads only).
Step-By-Step Instructions for ISP Programming
a) Install PSDsoft Express on your PC running Windows 95/98/NT/2000. Check web for latest version.
b) Plug the FlashLINK Programmer into your PC’s parallel port and plug in the ribbon cable to the JTAGport on the eval board (for help, see the Appendix C, FlashLINK manual).
c) Plug in power supply and turn on power. An LCD contrast control is provided as R11. The typical settingis near the counterclockwise stop.
d) Run PSDsoft Express. Here is the initial screen if no project was open.
Figure 2. Opening screen upon PSDsoft Express invocation
Use cancel at this point since all we need to do is program the PSD with an existing demonstration file(*.obj) and there is no need to create a new project. Later, in the “Using the DK4000 as a developmentplatform”, a further tutorial is given on using PSDsoft Express with the Eval Board for development.
Figure 3. Invocation reminder screen
e) In the Design Flow (shown below), click on the ST JTAG/ISP button. Bottom row of boxes left side.
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Figure 4. PSDsoft Express flow
The following screen appears inquiring if it’s desired to program a single device or multiple devices in theJTAG chain. Select “Only one” and then click OK.
Figure 5. JTAG-ISP Operations dialog
Clicking OK brings up the JTAG Operations - Single device dialog shown in the following figure.
Click here
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Figure 6. PSDsoft Express, JTAG Operations dialog
f) In Step 1, browse to find the *.obj file shown in the above figure
g) In “select device” box, choose the PSD4000 device you have installed on the board
h) In step 3, select the operation of “Program”. Click execute.
i) Observe in the lower pane the JTAG activities that occur while programming your device.
j) Watch the display. When the download is completed as indicated in the log window, push the reset but-ton on the Development Board. The displays below will sequence one time and then operation will stop.
Figure 7. Eval Board Displays for IAP.obj
AI05709
N o
n e e d
t o f e a r
E a s y F L A S H
i s
h e
r e
! ! ! !
* * * C O M P L E T E * * *
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If you cycle power to the board, you will see that the display will resequence, confirming that the programand all configuration information are stored in the PSD’s non-volatile Flash memory.
k) For better understanding of the program you may want to examine the following references:
1. System memory map in the “167 Design Overview” section of this document.
2. PSDsoft Express project (a16xbhe.ini)
3. The file source code (included) to see how the executing code was configured
Notice:
An additional code bundle will be posted on the web in the future to cover the IAP functionality. Please goto www.st.com/psd, and select “Development Tools” and scroll down to DK4000. Latest software andmanual can then be downloaded.
USING DK4000 AS A DEVELOPMENT PLATFORM FOR C167CR USERS
Concept
■ The ST DK4000 Development Board provides the following capabilities
■ Demonstrate design concepts early, optimizing “time to market”
■ Jump start user application with proven framework (hardware and software)
■ Substitute for user target system until target prototypes are available
■ Gives instant platform for testing ISP and IAP demonstration.
■ Allows programming the PSD using included Flashlink cable
Downloading to the Development Board
Executable code can be downloaded to the Development Board two different ways; via the JTAG (ISP) orvia the UART (IAP). This manual only describes the ISP capabilities at this time. The IAP capabilities willbe supported in the future using PSDload available on the website at www.st.com/psd.
JTAG - ISP
The PSD4000 series JTAG interface provides the capability of programming all memory areas within thePSD (PLD, configuration, MAIN and secondary Flash memories). This interface can also be used to pro-gram a completely blank component as JTAG is enabled as the default PSD state. See Application Note54 (AN054) for further description of the JTAG interface on our CD or our website at www.st.com/psd.
The LCD will be non operational during JTAG - ISP, since the MCU is not operating. During this interval,the PSD is not connected to the MCU bus. To restrain the MCU during this interval, the JTAG interfacecontains a signal,!RST, that is connected to the MCU reset pin.
ST provides a FlashLINK programmer to facilitate the JTAG programming operation. The FlashLINK pro-grammer connects the PC parallel port to the Eval Board JTAG header and is driven by PSDsoft Express,the PSD development tool.
167 DESIGN OVERVIEW
The following figure depicts how the memory is allocated in this project for the hwtest.obj. Hwtest.obj usesthe segmented mode of the C167CR. The demo1 project uses the non-segmented mode of the C167CR.
The C167CR contains a large addressable memory area that is partitioned into segments of 64k byteseach. Even though many memory segments exist in the C167CR, only segments 0 and 1 are used in this
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project.
The configuration of the C167CR is controlled by two registers that are written at system startup (sysconand buscon0). These registers handle the mechanism for different bus width peripherals in the C167CRas well as many other items. See the C167CR user manual for details. Additional areas can be controlledby the definition of pairs of buscon and addr registers for each discrete area. The project definitions ofthese registers are denoted in the memory map figure below.
The default configuration (syscon and buscon0) is 16 bit multiplexed for the following system resources;
■ C167 resources
■ PSD code memory (main and secondary Flash memory and boot areas)
■ PSD SRAM
Two additional areas are defined as 8 bit multiplexed as shown below for the following system resources.
■ LCD
■ CSIOP space (PSD registers).
The C167CR XRAM and CAN areas are not used.
Figure 8. Memory map of DK4000/167 Board
Note: Default x16 multiplex bus used (syscon and buscon0) unless otherwise noted
Memory Swapping in the PSD
For this test (hwtest.obj), the dip switch should be in the following position . As a component ofthis test, a copy of the executing code that resides in csboot0/1 is made. The destination of this copy is
Boot ConfigurationAI05706
0x0
0x04000
0x08000
0x0C000
0x0FFFF
CodePSD Boot area(csboot0,1)x16
PSD RAM 4Kx16
LCD, buscon1 0x0BE00CSIOP(PSD),buscon1 0x0BF00
167System Area
0x10000
0x1FFFF
FlashPSD, FS0
32Kx16
Segment 0 Segment 1
0x0A000
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the main Flash memory area FS0, as shown in the figure below. After the copy operation, the followingmap applies.
Figure 9. Memory map after running of hwtest.obj
Notice in the above figure the element denoted as message in each of the code areas. This element isdisplayed as the second LCD screen to show the source of execution. For normal boot, the second LCDscreen shows “executing from, BOOT area”. The message exists in a fixed location in the code and is readfrom this location and copied to the LCD at boot up.
When the code copy is performed, a different message is inserted into the same fixed location based onthe destination of the copy (as shown in FS0). When this version of the code is executed, the message isdisplayed “executing from MAIN FLASH”. This method yields a single unambiguous confirmation of theexecution source, which is very convenient for demonstrating memory swapping operations.
AI05707
0x0
0x04000
0x08000
0x0C000
0x0FFFF
PSD Boot area(csboot0,1)
PSD RAM 4Kx16
LCD, buscon1 0x0BE00CSIOP(PSD),buscon1 0x0BF00
167System Area
0x10000
0x1FFFF
FlashPSD, FS0
32Kx16
Copy of codefrom csboot0,1
message(main flash)
message(boot area)
0x0A000
Segment 0 Segment 1
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Now let’s boot from the other memory to demonstrate the swapping capability of the PSD. Place the dipswitch in the following position and press the reset button. You should see the execution sourceannunciated to the display “booting from MAIN FLASH”. The following memory map applies.
Figure 10. Memory map for alternate memory boot
The memory movement within the MCU memory map is accomplished via the logic contained in the PLDequations in the PSD. Each segment that moves must have dual ranged defined in these equations. Theselection is made based on a single logic bit (exe_src_a) that resides in the PSD PAGE register. Followingare the equations for the system. These can bee seen in the PSDsoft Express project included with thekit. Note that “#” indicates a logical OR and “&” indicates a logical ANDCsboot0 = (0x0 – 0x01FFF) & !exe_src_aCsboot1 = (0x02000 – 0x03FFF) & !exe_src_aFs0 = ( (0x10000 – 0x1FFFF) & !exe_src_a ) # ( ( 0x0 – 0x03FFF) & exe_src )
Note that the logic variable (bit) controlling the actual location of the memory is “exe_src_a”. When this bitis zero (0), the memory segments are as shown in figure 9. When exe_src_a is one (1), FS0 appears inthe execution location and the csboot areas are not in the map at all. The physical location of this logic bit,exe_src_a, is in the bit6 position of the PAGE register. Actually this bit can be anywhere, the only importantelement is that it is contained in the PLD equations as shown above and accessible by the MCU. Controlof this bit is via a board mounted dip switch.
The power up sequence is as follows:
1. Execute start167.a66
2. Read the dip switch
AI05708
0x0
0x04000
0x08000
0x0C000
0x0FFFF
PSD RAM 4Kx16
LCD, buscon1 0x0BE00CSIOP(PSD),buscon1 0x0BF00
167System Area
0x10000
0x1FFFF
Main Flashcode copy
from csboot0,1
message(main flash)
0x0A000
Segment 0 Segment 1
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3. Write the dip switch setting into the PSD PAGE register (some positioning is done prior to the write).
Once the PAGE register write operation has completed, the next instruction is fetched from the new mem-ory location (FS0).
This same sequence of events occurs every time power is applied to the board. Since the PAGE registeris always 00h at power up, the software always executes steps a) and b) from the boot area. Then, basedon the dip switch selection, the code will either stay in the boot area or jump to the main Flash memoryarea.
What really happens
There is a subtlety involved in the transfer of execution described above. This subtlety is because the MCUreally doesn’t know the source of the instruction bytes; boot area or main Flash memory. All the MCUknows is that valid instructions on valid address boundaries are presented on the bus when the MCUneeds them. Then the MCU executes the instruction and generates the next address. The key elementinvolved is the generation of the address by the MCU.
To understand this critical transfer of control, let’s examine the instruction by instruction transition fromone memory to the other. After the reset signal is deasserted, the MCU is executing from the csboot areanormally. This continues until the exe_src_a bit is written, moving FS0 into the execution location (0x0-0x3FFF). At this same time, csboot area is, for all practical purposes, gone from the system memory map.At this point, the MCU is generating the next address from the instruction received from the csboot area.However, the next instruction will come from the FS0 area. This next instruction fetch must be appropriateto maintain the program flow. That is, the next instruction must be received by the MCU on an instructionboundary and be appropriate for the program flow. In addition, any issues with the stack and stack pointermust be resolved so program flow can continue (subroutine return addresses, temporary variables, etc.).Pipelining operations can result in execution from the pipeline instead of the new memory, but the pipelinewill continue to be filled from the new memory.
The method we’ve used to ensure correct operation is to place identical code at identical locations in bothapplications through the point of the swap. After the point of the swap, the code bundles can diverge with-out problems. While this result is inherently ensured in a code copy scenario like hwtest.obj, it’s not soautomatic when the applications are different such as exists in a true IAP scenario.
Creating your own IAP code bundle
A few easy steps can ensure that program flow for this critical area is guaranteed to occur properly. Thesesteps involve the absolute location of certain modules within the base application and the new IAP appli-cation. Locating these modules is accomplished using linker controls. With this framework, booting fromone application to another is EASY.
REFERENCES
IEEE Std 1149.1-1990 IEEE Test Access Port and Boundary Scan Architecture
Flashlink User Manual (included in the Appendix of this document)
AN1153 Application note: JTAG Information
AN1426 Application note: Design Guide, PSDsoft Express and PSD4135G2
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APPENDIX
Appendix A - Jumper configuration on DK4000.
Figure 11. Assembly Drawing with default jumper positions
Appendix B Software functional description.
Hwtest. This code exercises all components of the development board; the display, PSD memory andchip selects, and the UART channel (single character only on receive and transmit). This confirms func-tionality and is used as a production test. The following list is a detailed description of the viewable LCDscreens.
■ Invocation banner, software version
■ Display execution source. (boot area or main Flash memory)
■ Motherboard LED test
■ PSD RAM test
Jumper DescriptionDefault position
(shown by dotted line)
Board position
JP1 Measure PSD current No measure Upper center
JP2 JTAG chaining No chain Upper right
JP3 Internal / external power supply Internal power supply Lower right
JP4 9v battery connector None (no jumper) Lower right
batteryconnection
MCU area
PSD
serial port
JTAG, P1
onof
f
LCDContrast
d7-14LCD Display
JP2
JP1
NO CHAIN
JP3
PS
D I
Mea
s
Power Supply Int Ext
Power onindicator
AI05339
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■ Code Copy. Executing boot code is copied to main Flash memory block FS0 (BOOT-> FLASH)
■ Displays Flash memory ID and does erase of FS0 prior to the copy operation.
■ UART test (waiting for host to send “0”, development board reply is a “1”, baud rate is19200 with 8 data bits, no parity and one stop bit)
This software also includes provision for external SRAM test in evaltest.c but this code is not utilized atthis time since the site is unpopulated. If this code is used, be aware that the appropriate buscon must beset for 8 bit demuxed bus.
After this code has run one time, a copy of the executing code exists in the Flash memory area (FSx). Thesystem can run from this code copy by placing the dip switch in the appropriate configuration as describedin the “Memory Swapping in the PSD” section of this document.
Demo1. This is a simple program that displays the following text on the LCD display.
No Need to fear, EASYflash is here!!!!.
The intent is to show a minimal level of functionality. No UART support is provided.
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Appendix C Development Board Schematic and parts list
Figure 12. Main SchematicA A
B B
C C
D D
E E
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AD
IO2
AD
IO2
AD
IO3
AD
IO3
AD
IO4
AD
IO4
AD
IO5
AD
IO5
AD
IO6
AD
IO6
AD
IO7
AD
IO7
AD
IO8
AD
IO8
AD
IO9
AD
IO9
AD
IO10
AD
IO10
AD
IO11
AD
IO11
AD
IO12
AD
IO12
AD
IO13
AD
IO13
AD
IO15
AD
IO15
!RD
CN
TL1
(_R
D)
!WR
/WR
L
CN
TL0
(_W
R)
A19
A18
A17
A16
A16
A17
A18
A19
AD
IO14
AD
IO14
CN
TL2
(_B
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)
!EA
!RE
SE
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TX
D0
AD
IO7
AD
IO6
AD
IO5
AD
IO4
AD
IO3
AD
IO2
AD
IO1
AD
IO0
A0
A1
A2
A3
A4
A5
A6
A7 A
8A
9A
10A
11A
12A
13A
14P
B2
PB
3 PB
4
CN
TL1
(_R
D)
PA
1P
A2
PA
3P
A4
PA
5P
A6
PA
7
PB
0P
B1
PB
2
PB
4P
B5
PB
6P
B7
CN
TL0
(_W
R)
A0
A1
A2
A3
A4
A5 A6
A7 A8
A9
A10
A11 A12
A13
A14
A15
P1L
0P
1L1
P1L
2P
1L3
P1L
4P
1L5
P1L
6P
1L7
P1H
1P
1H2
P1H
3P
1H4
P1H
5P
1H6
P1H
7
P1H
0
PD
1P
D2
PD
3
PE
0P
E1
PE
2P
E3
PE
4P
E5
PE
6P
E7
A20
A14
A15
A12
A13
A10
A11
A8
A9 A
7A
6A
5A
4A
3A
2A
1A
0
AD
IO15
AD
IO14
AD
IO13
AD
IO12
AD
IO11
AD
IO10
AD
IO9
AD
IO8
AD
IO7
AD
IO6
AD
IO5
AD
IO4
AD
IO2
AD
IO0
AD
IO1
AD
IO3
PB
7P
B6
PB
5P
B4
PB
3P
B2
PB
1P
B0 PA
7P
A6
PA
5P
A4
PA
3P
A2
PA
1P
A0
VC
CG
ND
GN
DV
CC
PB
3
A21
A22
VC
CG
ND
A23
A22
A21
A20
A19
A18
A17
A16
PD
0P
D1
PD
2P
D3
PD
0
!MR
RX
D0
P3.
0P
3.1
P3.
2P
3.3
P3.
4P
3.5
P3.
6P
3.7
P3.
8P
3.9
P3.
10P
3.11
P3.
12P
3.13
P3.
15
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A[1
5..8
]
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[7..0
]
PD
[3..0
]
PE
[7..0
]
P3.
11P
3.12
P8.
7P
8.6
P8.
5P
8.4
P8.
3P
8.2
P8.
1P
8.0
P7.
7P
7.6
P7.
5P
7.4
P7.
3P
7.2
P7.
1P
7.0
P6.
7P
6.6
P6.
0
P5.
15
P5.
0P3.
15
P3.
0
P5.
1P
3.[1
3..0
]
P3.
1P
3.2
P3.
3P
3.4
P3.
5P
3.6
P3.
7P
3.8
P3.
9
P3.
13
P5.
2P
5.3
P5.
4P
5.5
P5.
6P
5.7
P5.
8P
5.9
P5.
10P
5.11
P5.
12P
5.13
P5.
14
P6.
1 P6.
2P
6.3
P6.
4P
6.5
P5.
0P
5.1
P5.
2P
5.3
P5.
4P
5.5
P5.
6P
5.7
P5.
8P
5.9
P5.
10P
5.11
P5.
12P
5.13
P5.
14P
5.15
P8.
0P
8.1
P8.
2P
8.3
P8.
4P
8.5
P8.
6 P8.
7P
7.0
P7.
1P
7.2
P7.
3P
7.4
P7.
5P
7.6
P7.
7
P2.
0P
2.1
P2.
2P
2.3
P2.
4P
2.5
P2.
6P
2.7
P2.
8P
2.9
P2.
10P
2.11
P2.
12P
2.13
P2.
14P
2.15
A23
P6.
7P
6.6
P6.
5P
6.4
P6.
3P
6.2
P6.
1P
6.0
P1L
[7..0
]
P2.
0P
1H7
P2.
15P
1L0
P2.
[15.
.0]
P1H
6P
1H5
P1H
4P
1H3
P1H
2P
1H1
P1H
0P
1L7
P1L
6P
1L5
P1L
4P
1L3
P1L
2P
1L1
P2.
1P
2.2
P2.
3P
2.4
P2.
5P
2.6
P2.
7P
2.8
P2.
9P
2.10
P2.
11P
2.12
P2.
13P
2.14
VC
CG
ND
VC
CG
ND
VC
CG
ND
GN
DV
CC
P5.
[15.
.0]
P6.
[7..0
]
PB
4P
B5
PB
6P
B7
PA
[7..0
]
!RE
SE
T
P7.
[7..0
]
P8.
[7..0
]
A20
A21
A22
A23
PA
0
!NM
I
PB
0
!RE
AD
Y
P3.
10T
XD
0R
XD
0
PE
6P
E7
CN
TL0
(_W
R)
CN
TL1
(_R
D)
CN
TL2
(_B
HE
)!R
ES
ET
Vre
fA
gnd
Agn
d
PB
0P
B1
A0
PB
2
PE
[7..0
]
AD
IO[1
5..0
]A
[23.
.16]
A[1
5..8
]
A[7
..0]
P6.
[7..0
]
PD
[3..0
]
PA
[7..0
]
P8.
[7..0
]
CN
TL0
(_W
R)
CN
TL1
(_R
D)
CN
TL2
(_B
HE
)
!RE
SE
T
!NM
I
!MR
PB
0
P5.
[15.
.0]
GN
D
P6.
[7..0
]
TX
D0
RX
D0
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
VC
C
VC
CV
CC
R1
10M
C2
22pf
C1
22pf
U5
MS
6281
28
A0
12
A1
11
A2
10
A3
9
A4
8
A5
7
A6
6
A7
5
A8
27
A9
26
A10
23
A11
25
A12
4
A13
28
A14
3
A15
31
A16
2
CS
122
CS
230
OE
24
WE
29
D0
13
D1
14
D2
15
D3
17
D4
18
D5
19
D6
20
D7
21
U3
C1+
1
C2+
4
C2-
5
C1-
3V
+2
V-
6
VC
C16
T2i
n10
R2o
ut9
R1o
ut12
T1i
n11
T1o
ut14
T2o
ut7
R1i
n13
R2i
n8
R2
100
R3
100
C6
0.1
C5
0.1
C7
0.1
C3 0.
1
C4
0.1
R5
10k
J4 DB
9F
594837261
R4
100
P4
1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20
P12
1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20
P10
1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20
P11
1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20
R7
10K
typ
P9
1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20
P3
1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20
S1
RE
SE
T
R6
0805
R8
R9
R10
C8
0.1
C9
0.1
C18
0.1
C19 1
P5
1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20
S2
1234
8765
P6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
U2
AD
IO0
3
AD
IO1
4
AD
IO2
5
AD
IO3
6
AD
IO4
7
AD
IO5
10
AD
IO6
11
AD
IO7
12
AD
IO8
13
AD
IO9
14
AD
IO10
15
AD
IO11
16
AD
IO12
17
AD
IO13
18
AD
IO14
19
AD
IO15
20
CN
TL0
(!W
R)
59
CN
TL1
(!R
D)
60
CN
TL2
(!B
HE
)40
PF
031
Vcc_19
GND8
Vcc_129
Vcc_169
PD
0(A
LE)
79
PD
1(C
LKIN
)80
PD
2(!C
SI)
1
PD
3(!W
RH
)2
PE
0(T
MS
)71
PE
1(T
CK
/ST
)72
PE
2(T
DI)
73
PE
3(T
DO
)74
PE
4(T
ST
AT
/RD
Y)
75
PE
5(T
ER
R)
76
PE
6(V
ST
BY
)77
PE
7(V
BA
TO
N)
78
PF
132
PF
233
PF
334
PF
435
PF
536
PF
637
PF
738
PG
021
PG
122
PG
223
PG
324
PG
425
PG
526
PG
627
PG
728
PA
051
PA
152
PA
253
PA
354
PA
455
PA
556
PA
657
PA
758
PB
061
PB
162
PB
263
PB
364
PB
465
PB
566
PB
667
PB
768
PC
041
PC
142
PC
243
PC
344
PC
445
PC
546
PC
647
PC
748
GND30
GND49
GND50
GND70
!RE
SE
T39
12
3
JP1
13
2
R11
10K
13
2
R54
Y1
xx_M
Hz
12
34
C38
0.01
Y2
xx_M
Hz
12
3
C40
100p
f
U1
C16
7CR
AD
010
0
AD
110
1
Vcc109
AD
210
2
AD
310
3
AD
410
4
AD
510
5
AD
610
6
AD
710
7
AD
810
8
AD
911
1
AD
1011
2
AD
1111
3
AD
1211
4
AD
1311
5
AD
1411
6
AD
1511
7
!EA
99A
LE98
!RE
AD
Y97
!WR
/!W
RL
96!R
D95
Vcc93
XTA
L113
8
XTA
L213
7
!RS
TIN
140
!RS
TO
UT
141
!NM
I14
2
P4.
0/A
1685
A17
86
A18
87
A19
88
A20
89
A21
90
A22
91
P4.
7/A
2392
P3.
0/T
0IN
65
P3.
1/T
6OU
T66
P3.
2/C
AP
IN67
P3.
3/T
3OU
T68
P3.
4/T
3EU
D69
P3.
5/T
4IN
70
P3.
6/T
3IN
73
P3.
7/T
2IN
74
P3.
8/M
RS
T75
P3.
9/M
TS
R76
P3.
10/T
XD
077
P3.
11/R
XD
078
P3.
12/!
BH
E/!
WR
H79
P3.
13/S
CLK
80
P3.
15/C
LKO
UT
81
P1L
011
8P
1L1
119
P1L
212
0P
1L3
121
P1L
412
2P
1L5
123
P1L
612
4P
1L7
125
P1H
012
8P
1H1
129
P1H
213
0P
1H3
131
P1H
413
2P
1H5
133
P1H
613
4P
1H7
135
P2.
0/C
C0I
O47
P2.
1/C
C1I
O48
P2.
2/C
C2I
O49
P2.
3/C
C3I
O50
P2.
4/C
C4I
O51
P2.
5/C
C5I
O52
P2.
6/C
C6I
O53
P2.
7/C
C7I
O54
P2.
8/C
C8I
O/E
X0I
N57
P2.
9/C
C9I
O/E
X1I
N58
P2.
10/C
C10
IO/E
X2I
N59
P2.
11/C
C11
IO/E
X3I
N60
P2.
12/C
C12
IO/E
X4I
N61
P2.
13/C
C13
IO/E
X5I
N62
P2.
14/C
C14
IO/E
X6I
N63
P2.
15/C
C15
IO/E
X7I
N64
P5.
0/A
N0
27
P5.
1/A
N1
28
P5.
2/A
N2
29
P5.
3/A
N3
30
P5.
4/A
N4
31
P5.
5/A
N5
32
P5.
6/A
N6
33
P5.
7/A
N7
34
P5.
8/A
N8
35
P5.
9/A
N9
36
P5.
10/A
N10
/T6U
ED
39
P5.
11/A
N11
/T5U
ED
40
P5.
12/A
N12
/T6I
N41
P5.
13/A
N13
/T5I
N42
P5.
14/A
N14
/T4U
ED
43
P5.
15/A
N15
/T2U
ED
44
P6.
0/!C
S0
1
P6.
1/!C
S1
2
P6.
2/!C
S2
3
P6.
3/!C
S3
4
P6.
4/!C
S4
5
P6.
5/!H
OLD
6
P6.
6/!H
LDA
7
P6.
7/!B
RE
Q8
P7.
0/P
OU
T0
19
P7.
1/P
OU
T1
20
P7.
2/P
OU
T2
21
P7.
3/P
OU
T3
22
P7.
4/C
C28
IO23
P7.
5/C
C29
IO24
P7.
6/C
C30
IO25
P7.
7/C
C31
IO26
P8.
0/C
C16
IO9
P8.
1/C
C17
IO10
P8.
2/C
C18
IO11
P8.
3/C
C19
IO12
P8.
4/C
C20
IO13
P8.
5/C
C21
IO14
P8.
6/C
C22
IO15
P8.
7/C
C23
IO16
Vss143
Vss139
Vss127
Vss110
Vss94
Vss83
Vss71
Vss55
Vss45
Vss18
Agnd38
Vcc144
Vcc136
Vcc126
Vcc82
Vcc72
Vcc17
Vcc56
Vcc46
Vre
f37
OW
E84
123
JP8
13
2
123
JP9
13
2
U4
MA
X63
15
RE
SE
T2
MR
3
DS
1
HC
1620
1-A
D0
7D
18
D2
9D
310
D4
11D
512
D6
13D
714
E6
R/W
5
RS
4V
03
Vcc
2
GN
D1
R57
100
R55
12
3JP
101
3
2
DK4000-C167 - USER MANUAL
16/27
Figure 13. Power Supply Schematic
17/27
DK4000-C167 - USER MANUAL
Table 2. DK4000 Parts List
Ref Des Quantity
Generic Part Number Description Vendor Part Number
1 pcbevm0002 asian 21insq, us 25 in sq@
ds1 1 dis101-0001 display hantronix hdm16216h-b
y1 1 y101-0002 crystal, 16MHZ vfsmc-316pf11.0592
u1 1 umcu0002 microcontroller infineon C161V
u2 1 PSD42xxG ST PSD42xxG
psd socket Yamiachi IC149-080-030-S5
u3 1 u232-0001 232 driver analog devices adm202jrn
u4 1 usup0002 max 6315 maxim, 5v max6315leuk
u6 1 ureg-0001 regulator micrel mic5237-5.0bt
d1-4 4 cr101-0001 diode s1ab
d5 1 vr101-0001 zener diode, 15v motorola mmsz5254bt1
d6 1 cr101-0002 signal diode national fdLL4148
d7-15 9 led101-0002 led, t5(t1.75) lumex SLX-LX5093ID
c1-2 2 cap0805-2209 22 pf caps, cer murata grm40c0g22050ad
c10,c21,c23,c25 4 cap1206-1004 cap, 1uf tant murata grm42-6y5v105z016ad
c12,c19 2 cap1206-1004 cap, 1uf cer, 1206 AVX 1206zc105mat2a
c3-9,c11, c13-18,c20,c22, c24
18 cap0805-1003 0.1 cap, smt, cer murata grm40z5u104z016ad
C40 1 cap0805-1009
r1 1 res0805-1005 resistor, smt, 10M, 1/8 watt, 0805 samsung rm10j106ct
r2-4, R57 3 res0805-1000 resistor, smt, 100, 1/8 watt samsung rm12j101ct
r5-10, r12-r23, r32-47, R54, R55
35 res0805-1002 resistor, smt, 10k, 1/8 watt, 0805 samsung rm10f1002ct
r11 1 variable resistor, 10k digikey 3309P-103-ND
R24-31, R53 9 res0805-8200 resistor, smt. 820, 1/8 watt rm10f820ct
jp1, jp3 2 con225-1003 3 position header samtec tsw-103-23-L-s-LL
j1,j3 2 rec225-1002 shunt (use with jpx above) samtec snt-100-bk-g
jp2 1 con225-3003 post 3x3 samtec tsw-103-23-L-T-LL
j2 1 rec225-3002 triple shunt (use with jp3) samtec mnt-103-bk-g
j4 1 con232-0001rt angle rs232 connector(female, 9 pin)
amp 745988-4
s1 1 sw102-0001 reset switch, momentary bourns 7914g
s2 1 swdip0004 4 position dip switch,side actuated cts 195-4mst
s3 0 sw101-0002 on-off switch digikey EG1906-ND
t1 1 tr101-0001 class 2 transformer, 500ma,female digikey dpd090050-p-5
j7 1 con103-0001 connector for ps, male digikey pj-202a
DK4000-C167 - USER MANUAL
18/27
1 7x2 ribbon connector samtec
p1 1 con104-2007 jtag connectors samtec tst-107-01-L-D-LL
P13-P16 4
1 con225-101414 pin single in line connector/spacer (display)
samtec dw-14-17-T-S-250-LL
4 std102-0250 standoffs for board richco SRS4-5-01
2 std101-0250 standoffs for display, 0.250 richco dlcbsat-4-01
tp_ps,tp_gnd 2 tp101-0001 test points koa rcw
2 riv101-0281 rivet rivet king c-1 (std tubular rivet)
Ref Des Quantity
Generic Part Number Description Vendor Part Number
19/27
DK4000-C167 - USER MANUAL
Appendix D: FlashLINK Users Manual
Features.
■ Allows PC parallel port to communicate with PSD4000 via PSDsoft Express
■ Provides interface medium for JTAG communications
■ Supports basic IEEE 1149.1 JTAG signals (TCK, TMS, TDI, TDO)
■ Supports additional signals to enhance download speed (!TERR, TSTAT)
■ Can be used for programming and/or testing
■ Wide power supply range of 2.7 to 5.5V
■ Pinout independent with target side flying leads
■ Convenient desktop packaging allows varying applications (desk, lab or production)
■ Synchronous JTAG interface allows speeds as fast as pc can drive.
Overview. FlashLINK is a hardware interface from a standard PC parallel port to one or more PSD4000devices located within a target PC board as shown below. This interface cable allows the PSD to be ex-ercised for purposes of programming and/or testing. PSDsoft Express is the source for driving FlashLINK.
Figure 14. Typical FLASHlink application
Operating considerations. Operating power for FlashLINK is derived from the target system in therange of 2.7 to 5.5 V. Compatibility over this voltage range is ensured by the design of FlashLINK. No set-tings are involved.
On a cautionary note, it is recommended that the target system be powered with a well regulated and sta-ble source of power which is energized at the final value of VCC. It is not recommended that the input volt-age be varied using the verneer on a regulated power supply, as this may cause the internal FlashLINKICs (74VHC240) to misoperate toward the lower end of the supply range.
Each FlashLINK is packaged with a six-inch “flying lead” cable for maximum adaptability (a ribbon cablerequires the use a certain connector on the target assembly). This flying lead cable mates to the FlashLinkadapter on one end and has loose sockets on the other end to slide onto 0.025 square posts on the targetassembly.
Mates withPC parallel
port
FlashLinkadapter
6 feet
12 WIRES
6 inches
Targetdevice
Flying leadcable
AI05342
DK4000-C167 - USER MANUAL
20/27
Table 3. Pin descriptions for FlashLINK adapter assembly
Note: 1. Bold signals are required connections2. all signal grounds are connected inside FlashLink adapter3. OC = open collector, pulled-up to Vcc inside FlashLink adapter4. * = Not supported initially by PSDsoft.5. The target device must supply Vcc to the FlashLink Adapter (2.7 to 5.5 VDC, 15mA max @ 5.5V).
All 14 signals may not be needed for a given application. Here’s how they break down:
(6) Core signals that must be connected: TDI, TDO, TMS, TCK, Vcc and GND
(2) Optional signals for enhanced ISP: TSTAT, TERR\
(1) Optional signal to control multiplexing of the JTAG signals: JEN\
(1) Recommended signal to allow FlashLINK to reset target system during and
after ISP: RST\
(1) Optional IEEE-1149.1 signal for JTAG chain reset: TRST\
(1) Optional generic control signal from FlashLink to target system: CNTL
(2) Two additional ground lines to help reduce EMI if a ribbon cable is used.
These ground lines “sandwich” the TCK signal in the ribbon cable. These
lines are not needed for use with the flying lead cable. That is why the
flying lead cable has only 12 of 14 wires populated.
PIN # SIGNALNAME
DESCRIPTIONJTAG = IEEE 1149.1
EJTAG = ST EHANCED JTAGType Flashlink is Signal
1 JEN\ Enables JTAG pins on PSD8XXF (optional) OC,100K Source
2 TRST\ * JTAG reset on target (optional per 1149.1) OC,10K Source
3 GND Signal ground
4 CNTL * Generic control signal, (optional) OC,100K Source
5 TDI JTAG serial data input Source
6 TSTAT EJTAG programming status (optional) Destination
7 Vcc VDC Source from target (2.7 - 5.5 VDC)
8 RST\ Target system reset (recommended) OC,10K Source
9 TMS JTAG mode select Source
10 GND Signal ground
11 TCK JTAG clock Source
12 GND Signal ground
13 TDO JTAG serial data output Destination
14 TERR\ EJTAG programming error (optional) Destination
21/27
DK4000-C167 - USER MANUAL
FlashLINK pinouts. There is no “standard” JTAG connector. Each manufacturer differs. ST has a spe-cific connector and pinout for the FlashLINK programmer adapter. The connector scheme on theFlashLink adapter can accept a standard 14 pin ribbon connector (2 rows of 7 pins on 0.1" centers, stan-dard keying) or any other user specific connector that can slide onto 0.025" square posts. The pinout forthe FlashLINK adapter connector is shown in the following figure.
A standard ribbon cable is good way to quickly connect to the target circuit board. If a ribbon cable is used,then the receiving connector on the target system should be the same connector type with the same pinoutas the FlashLINK adapter shown in the following figure Keep in mind that the JTAG signal, TDI, is sourcedfrom the FlashLINK adapter and should be routed on the target circuit card so that it connects to the TDIinput pin of the PSD device. Although the name “TDI” infers “Data In” by convention, it is an output fromFlashLINK and an input to the PSD device. Also, keep in mind that the JTAG signal, TDO, is an input re-ceived by the FlashLINK adapter and is sourced by the PSD device on the TDO output pin.
Figure 15. Pinout for FlashLINK Adapter and Target System
TDO
TCK
TMS
VCC
TDI
GND
JEN
TERR
GND
GND
RST
TSTAT
CNTL
TRST
14
12
10
13
11
9
78
6 5
4 3
2 1
KEYWAY
VIEW: LOOKING INTO FACE OFSHROUDED MALE CONNECTOR.0.025" POSTS ON 0.1" CENTERS.
Connector reference: Molex 70247-1401
WSi ENHANCED JTAG ISP CONNECTOR DEFINITION
Recommended ribbon cable for quickconnection of FlashLink adapter to endproduct:Samtec: HCSD-07-D-06.00-01-S-N orDigikey: M3CCK-14065-ND
Note:TDI is a signal source on the Flashlinkand a signal destination on the targetboard.
TDO is a signal destination on theFlashLink and a signal source on thetarget board.
AI05343
DK4000-C167 - USER MANUAL
22/27
Figure 16. JTAG Chaining Example
Vcc
TMSTCK
TDI
TSTAT!TERR
TDO
!JEN!TRSTGND*CNTL!RST
GND*GND*
1
PSD4000
TMSTCK
TDITDO
TSTATTERR\
13
6
9
11
5
14
Target System, 3v or 5v
straight throughribbon cable
2 row, 7 position
Vcc
7
optionaloptional
optional
optional
optionalrecommended
12348
1012
* all ground pins areconnected together inside
FlashLINK assembly
PSD4000
TMSTCK
TDITDO
Any JTAGDevice in
ByPass Mode
2
n
FlashLinkAdapterConncetor
SystemReset
Circuitry
9
11
13
5
614
7
12
12348
10
JTAG Chaining Example,PSD4000 and other JTAGcompatible devices.
TMS
TCK
TDITDO
TSTATTERR\
AI05344
23/27
DK4000-C167 - USER MANUAL
Figure 17. Loop back connector schematic
A A
B B
C C
D D
E E
44
33
22
11
SO
LDE
RIN
G P
AD
PA
TTE
RN
(DR
AIN
WIR
E)
(FR
AM
E G
ND
)
(FO
R U
2)(F
OR
U3)
(FO
R U
1)
whi
te
red
org
pink
yello
wgr
een
lt gr
een
grey
blac
kor
gtbr
nt
Fla
shLi
nk P
CB
G
Fla
shLi
nk S
chem
atic
Waf
ersc
ale
Inte
grat
ion
4728
0 K
ato
Roa
dF
rem
ont,
CA
945
38
B
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4.7K
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R29
4.7K
C55
100pf
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100pf
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100pf
R6
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HC
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A1
2
A2
4
A3
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10 11 12 13 14
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R5
47
R3
47
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47
R7
47
R1
47
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47
D4
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CK
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DK4000-C167 - USER MANUAL
24/27
Figure 18. Loop Back Tester, Passive, FlashLINK
Appendix E Results codes and debug tree for 8031_f1.obj
Results codes.
Table 4. Hexadecimal to Binary Conversion
binary
Results = abcd
0 0000 Success Code
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
A 1010
B 1011
C 1100
D 1101
E 1110
F 1111
14 pin dual row 0.025 sq receptacle(polarized)
to FlashLINKassy VCC
GND
PC signaloutput
PC signalinput
TDI !TSTAT
!TERRTMS
TCK !TDO
connector
ACKN (8)
ERRN (10)
PAP (9)
!TSTAT
TMS
TDO
VCC
TCK
TDI
!TERR
GND
J1
CON1
1
J2
CON2
1
J1
CON14
123456789
1011121314
PC line
AI05346
25/27
DK4000-C167 - USER MANUAL
Table 5. Debug Tree
Note: X = don’t care
Appendix F: Board errata
Following is a brief list of issues with correlated on a revision level basis
Rev B. Center row of connections for U5 contain solder mask. This row is intended for a socket to accom-modate 0.3" wide SRAM. Also pin 16 is left out. These will be corrected at next board rev.
a b c d action
x x x 1 Page register test Replace PSD ( u1 on EVD) and retest
x x 1 x PSD ram error Replace PSD ( u1 on EVD) and retest
x 1 x x External Ram error Replace sram (u3 EVM) and retest
1 x x x Uart error Repair u4 or surrounding circuitry, EVM (this is under the EVD board)
DK4000-C167 - USER MANUAL
26/27
Table 6. Document Revision History
Date Rev. Description of Revision
1.0 Document written in the WSI format
19-Oct-2001 2.0 Document converted to the ST format
27/27
DK4000-C167 - USER MANUAL
For current information on PSD products, please consult our pages on the world wide web:www.st.com/psd
If you have any questions or suggestions concerning the matters raised in this document, please sendthem to the following electronic mail addresses:
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