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JMendiola

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Jameco Part Number 1491497

December 2006 Rev 4 1/30

30

TSA1203

Dual-channel 12-bit 40Msps 215mW A/D converter

Features■ Low power consumption: 215 mW@40 Msps

■ Single supply voltage: 2.5 V

■ Independent supply for CMOS output stage with 2.5 V/3.3 V capability

■ SFDR = -75 dBc @ Fin = 10 MHz

■ 1GHz analog bandwidth track-and-hold

■ Common clocking between channels

■ Dual simultaneous sample and hold inputs

■ Multiplexed binary word outputs

■ Built-in reference voltage with external bias capability

DescriptionThe TSA1203 is a new generation high-speed, dual-channel analog-to-digital converter implemented in a mainstream 0.25 µm CMOS technology that offers high performance and very low power consumption.

The TSA1203 is specifically designed for applications requiring a very low noise floor, high SFDR and good insulation between channels. It is based on a pipeline structure and digital error correction to provide high static linearity at FS = 40 Msps, and Fin = 10 MHz.

Each channel has an integrated voltage reference to simplify the design and minimize external components. It is nevertheless possible to use the circuit with external references.

The ADC binary word outputs are multiplexed in a common bus with a small number of pins.A tri-state capability is available for the outputs, allowing chip selection. The inputs of the ADC must be differentially driven.

The TSA1203 is available in extended temperature range (-40° C to +85° C), in a small 48-pin TQFP package.

Applications■ Medical imaging and ultrasound

■ 3G base station

■ I/Q signal processing applications

■ High-speed data acquisition systems

■ Portable instrumentation

D0(LSB

)

GN

DBE

D5

D6

D7

D8

D9

D10

D11(MSB)

AVCCB

indexcorner

1

2

3

4

5

6

7

8

9

10

11

32

31

30

29

28

27

26

13 14 15 16 17 18 19 20 21 22

47

25

33

12

23 24

35

34

36

48 44 43 42 41 40 39 38 3746 45

TSA1203

VCCBE

GNDBE

AGND

INI

AGND

AGND

IPOL

AGND

AGND

INBQ

INIB

AGND

INQ

D2

D3

REFM

I

OE

B

AVC

C

REFP

I

INC

MI

AVC

C

VCC

BI

VCC

BI D1

VCC

BE

SELEC

T

CLK

DG

ND

RE

FPQ

AGN

D

AVC

C

DG

ND

DV

CC

DV

CC

INC

MQ

RE

FMQ

GN

DBI

D4

7x7mm TQFP48

CLK

D

www.st.com

http://www.st.com

Contents TSA1203

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Contents

1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1 Additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1.1 Output enable mode (OEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1.2 Select mode (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.2 References and common mode connection . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.1 Internal reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.2 External reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.3 Driving the differential analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.5 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.6 Layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.7 EVAL1203/BA evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.7.1 Evaluation board operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.7.2 Consumption adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.7.3 Single and differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.7.4 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Practical application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.1 Digital interface applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.2 Medical imaging applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TSA1203 Contents

3/30

10 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

11.1 TQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Schematic diagram TSA1203

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1 Schematic diagram

Figure 1. TSA1203 block diagram

Figure 2. Timing diagram

Timing

BuffersIPOL

CLK+2.5V/3.3V

VINI

VINBI

OEB

VINCMI

GND

VINQ

VINBQ

VINCMQ

AD 12I channel

AD 12Q channel

12

12 12

12

MUX

REF I

REF Q

SELECT

VREFPI

VREFPQ

Polar.

VREFMI

VREFMQ

common mode

common mode

D0TOD11

VCCBE

GNDBE

N-1N

N+1

N+6

N+7N+2

N+5

N+3

N+4

N+8

CLK

Tpd I + Tod

N+9N+10

N+11

N+12N+13

DATAOUTPUT

sample N+1I channel

sample NQ channel

sample N+1Q channel

sample N+2I channel

sample N+2Q channel

sample N+3I channel

OEB

Simultaneous sampling on I/Q channels

SELECT

sample N-9I channel

sample N-8I channel

sample N-7Q channel

sample N-6Q channel

CLOCK AND SELECT CONNECTED TOGETHER

Tod

I

Q

TSA1203 Pin descriptions

5/30

2 Pin descriptions

Table 1. Pin descriptions (TQFP48 package)Pin nb

Name Description ObservationPin nb

Name Description Observation

1 AGND Analog ground 0 V 25 GNDBE Digital buffer ground 0 V

2 INII channel analog input

26 VCCBEDigital buffer power supply

2.5 V/3.3 V

3 AGND Analog ground 0 V 27D11(MS

B)Most significant bit output

CMOS output (2.5 V/3.3 V)

4 INBII channel inverted analog input

28 D10 Digital outputCMOS output (2.5 V/3.3 V)

5 AGND Analog ground 0 V 29 D9 Digital outputCMOS output (2.5 V/3.3 V)

6 IPOLAnalog bias current input


7 AVCC Analog power supply 2.5 V 31 D7 Digital outputCMOS output (2.5 V/3.3 V)


9 INQQ channel analog input



11 INBQQ channel inverted analog input



13 REFPQQ channel top reference voltage


14 REFMQQ channel bottom reference voltage

0 V 38 D0(LSB)Least significant bit output

CMOS output (2.5 V/3.3 V)

15 INCMQQ channel input common mode

39 VCCBEDigital buffer power supply

2.5 V/3.3 V - see Table 14.

16 AGND Analog ground 0 V 40 GNDBE Digital buffer ground 0 V

17 AVCC Analog power supply 2.5 V 41 VCCBIDigital buffer power supply

2.5 V

18 DVCC Digital power supply 2.5 V 42 CLKD Data clock inputIdle at high level2.5 V or 3.3 V

19 DGND Digital ground 0 V 43 OEB Output enable input2.5 V/3.3 V CMOS input

20 CLK Clock input2.5 V CMOS

input44 AVCC

Analog power supply

2.5 V

21 SELECT Channel selection2.5 V CMOS

input45 AVCC

Analog power supply

2.5 V

22 DGND Digital ground 0 V 46 INCMII channel input common mode

23 DVCC Digital power supply 2.5 V 47 REFMII channel bottom reference voltage

0 V

24 GNDBI Digital buffer ground 0 V 48 REFPII channel top reference voltage

Dynamic characteristics TSA1203

6/30

3 Dynamic characteristics

Dynamic characteristics are measured under the following conditions, unless otherwise specified: AVCC = DVCC = VCCB = 2.5 V, FS = 40 Msps, Fin=10.13 MHz, Vin@ -1 dBFS, VREFP=0.8 V, VREFM=0 V, Tamb = 25° C.

4 Timing characteristics

Timing characteristics are measured under the following conditions, unless otherwise specified: AVCC = DVCC = VCCB = 2.5 V, FS = 40 Msps, Fin=10.13 MHz, Vin@ -1 dBFS, VREFP=0.8 V, VREFM=0 V, Tamb = 25° C.

Table 2. Dynamic characteristics

Symbol Parameter Min Typ Max Unit

SFDR Spurious free dynamic range -75 -59.5 dBc

SNR Signal to noise ratio 60.7 67 dB

THD Total harmonics distortion -73 -58 dBc

SINAD Signal to noise and distortion ratio 56.5 66 dB

ENOB Effective number of bits 9.1 10.8 bits

Table 3. Timing characteristics

Symbol ParameterTest

conditionsMin Typ Max Unit

FS Sampling frequency 0.5 40 MHz

DC Clock duty cycle 45 50 55 %

TC1 Clock pulse width (high) 22.5 25 ns

TC2 Clock pulse width (low) 22.5 25 ns

TodData output delay (clock edge to data valid)

10 pF load capacitance

9 ns

Tpd I Data pipeline delay for I channel 7 cycles

Tpd Q Data pipeline delay for Q channel 7.5 cycles

TonFalling edge of OEB to digital output valid data

1 ns

ToffRising edge of OEB to digital output tri-state

1 ns

TSA1203 Absolute maximum ratings

7/30

5 Absolute maximum ratings

6 Operating conditions

Table 4. Absolute maximum ratings

Symbol Parameter Values Unit

AVCC Analog supply voltage (1)

1. All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3 V or VCC.

0 to 3.3 V

DVCC Digital supply voltage (1) 0 to 3.3 V

VCCBE Digital buffer supply voltage (1) 0 to 3.6 V

VCCBI Digital buffer supply voltage (1) 0 to 3.3 V

IDout Digital output current -100 to 100 mA

Tstg Storage temperature -65 to +150 °C

ESDHBM: human body model(2)

2. Electrostatic discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5 kΩ..

2kV

CDM: charged device model(3)

3. Discharge to ground of a device that has been previously charged.

1.5

Latch-up Class(4)

4. ST Microelectronics corporate procedure number 0018695.

A

Table 5. Operating conditions


AVCC Analog supply voltage 2.25 2.5 2.7 V

DVCC Digital supply voltage 2.25 2.5 2.7 V

VCCBE External digital buffer supply voltage 2.25 2.5 3.5 V

VCCBI Internal digital buffer supply voltage 2.25 2.5 2.7 V

VREFP I VREFP Q

Forced top voltage reference 0.94 1.5 V

VREFM I VREFM Q

Forced bottom reference voltage 0 0.4 V

VINCM IVINCM Q

Forced input common mode voltage 0.2 1 V

Electrical characteristics TSA1203

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7 Electrical characteristics

Electrical characteristics, unless otherwise specified, are measured at AVCC = DVCC = VCCB = 2.5 V, FS = 40 Msps, Rpol = 18 kΩ, Fin = 2 MHz, Vin@ -1 dBFS, VREFP=0.8 V, VREFM=0 V, and Tamb = 25° C.

Table 6. Analog inputs



VIN-VINB Full scale reference voltageDifferential inputs mandatory

1.1 2.0 2.8 Vpp

Cin Input capacitance 7.0 pF

Req Equivalent input resistor 10 kΩ

BW Analog input bandwidthVin@full scale, Fs=40 Msps

1000 MHz

ERB Effective resolution bandwidth 70 MHz

Table 7. Digital inputs and outputs



Clock and Select inputs

VIL Logic "0" voltage 0 0.8 V

VIH Logic "1" voltage 2.0 2.5 V

OEB input

VIL Logic "0" voltage 0 0.25 x VCCBE V

VIH Logic "1" voltage 0.75 x VCCBE VCCBE V

Digital outputs

VOL Logic "0" voltage IOL=10 µA 0 0.1 x VCCBE V

VOH Logic "1" voltage IOH=10 µA 0.9 x VCCBE VCCBE V

IOZHigh impedance leakage current

OEB set to VIH

-1.67 0 1.67 µA

CLOutput load capacitance

15 pF

Table 8. Reference voltage


VREFP I

VREFP QTop internal reference voltage 0.81 0.88 0.94 V

VINCM I

VINCM QInput common mode voltage 0.41 0.46 0.50 V

TSA1203 Electrical characteristics

9/30

Table 9. Power consumption


ICCA Analog supply current 76 96.5 mA

ICCD Digital supply current 3.5 4.9 mA

ICCBE Digital buffer supply current (10 pF load) 6 9.4 mA

ICCBI Digital buffer supply current 100 440 µA

Pd Power consumption in normal operation mode 215 271 mW

Rthja Thermal resistance (TQFP48) 80 °C/W

Table 10. Accuracy


OE Offset error 2.97 LSB

GE Gain error 0.1 %

DNL Differential non linearity ±0.52 LSB

INL Integral non linearity ±3 LSB

- Monotonicity and no missing codes Guaranteed

Table 11. Matching between channels


GM Gain match 0.04 1 %

OM Offset match 0.88 LSB

PHM Phase match 1 dg

XTLK Crosstalk rejection 85 dB


10/30

Figure 3. Static parameter: integral non linearity(a)

FS = 40 Msps, ICCA = 60 mA, Fin = 2 MHz

Figure 4. Static parameter: differential non linearity(a)

Fs = 40 Msps, ICCA = 60 mA, Fin = 2 MH

a. For parameter definitions, see Section 10: Definitions of specified parameters on page 25.

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

0 500 1000 1500 2000 2500 3000 3500 4000

Output Code

INL

(L

SB

s)

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0 500 1000 1500 2000 2500 3000 3500 4000

Output Code

DN

L (

LS

Bs)


11/30

Figure 5. Linearity vs. FSFin = 5MHz

Figure 6. Distortion vs. FSFin = 5MHz

55

60

65

70

75

80

35 40 45 50

Fs (MHz)

Dyn

amic

par

amet

ers

(dB

)

7

7.5

8

8.5

9

9.5

10

10.5

11

11.5

12

EN

OB

(b

its)

ENOB_I

SINAD_I

ENOB_Q

SNR_Q

SINAD_Q

SNR_I

-100

-90

-80

-70

-60

-50

-40

35 40 45 50

Fs (MHz)

Dyn

amic

par

amet

ers

(dB

c)

THD_ISFDR_I

THD_QSFDR_Q

Figure 7. Linearity vs. FinFS= 40MHz, ICCA = 60mA

Figure 8. Distortion vs. FinFS= 40MHz, ICCA = 60mA

50

55

60

65

70

75

80

85

90

0 20 40 60 80

Fin (MHz)

Dyn

amic

par

amet

ers

(dB

)

6

7

8

9

10

11

12

EN

OB

(b

its)

ENOB_Q

SINAD_QSINAD_I

SNR_QSNR_I

ENOB_I

-100

-90

-80

-70

-60

-50

-40

0 20 40 60 80

Fin (MHz)

Dyn

amic

par

amet

ers

(dB

c)

SFDR_I

SFDR_Q

THD_I

THD_Q

Figure 9. Linearity vs. temperatureFS=40MHz, ICCA=60mA, Fin=2MHz

Figure 10. Distortion vs. temperatureFS=40Msps, ICCA=60mA, Fin=2MHz

50

55

60

65

70

75

80

85

90

-40 10 60 110

Temperature (°C)

Dyn

amic

par

amet

ers

(dB

)

4

5

6

7

8

9

10

11

12

EN

OB

(b

its)

SINAD_QSNR_Q

ENOB_Q

ENOB_I

SNR_ISINAD_I

50

55

60

65

70

75

80

85

90

95

100

-40 10 60 110

Temperature (°C)

Dyn

amic

par

amet

ers

(dB

c)

THD_Q

SFDR_Q

THD_ISFDR_I


12/30

Figure 11. Linearity vs. AVCCFS=40Msps, ICCA=60mA, Fin=10MHz

Figure 12. Distortion vs. AVCCFS=40Msps, ICCA=60mA, Fin=10MHz

50

52

54

56

58

60

62

64

66

68

70

2.25 2.35 2.45 2.55 2.65

AVCC (V)

Dyn

amic

par

amet

ers

(dB

)

9

9.5

10

10.5

11

11.5

12

EN

OB

(b

its)

SINAD_I

ENOB_I

SNR_I

SNR_Q

ENOB_Q

SINAD_Q

-100

-95

-90

-85

-80

-75

-70

-65

-60

-55

-50

2.25 2.35 2.45 2.55 2.65

AVCC (V)

Dyn

amic

Par

amet

ers

(dB

c)

SFDR_QSFDR_I

THD_Q

THD_I

Figure 13. Linearity vs. DVCCFS=40Msps, ICCA=60mA, Fin=10MHz

Figure 14. Distortion vs. DVCCFS=40Msps, ICCA=60mA, Fin=10MHz

50

52

54

56

58

60

62

64

66

68

70

2.25 2.35 2.45 2.55 2.65

DVCC (V)

Dyn

amic

par

amet

ers

(dB

)

9

9.5

10

10.5

11

11.5

12

EN

OB

(b

its)

SINAD_I

ENOB_I

SNR_I

SNR_Q

ENOB_Q

SINAD_Q

-90

-85

-80

-75

-70

-65

-60

-55

-50

2.25 2.35 2.45 2.55 2.65

DVCC (V)

Dyn

amic

Par

amet

ers

(dB

c)

SFDR_QSFDR_I

THD_QTHD_I

Figure 15. Linearity vs. VCCBIFS=40Msps, ICCA=60mA, Fin=10MHz

Figure 16. Distortion vs.VCCBIFS=40Msps, ICCA=60mA, Fin=10MHz

50

52

54

56

58

60

62

64

66

68

70

2.25 2.35 2.45 2.55 2.65

VCCBI (V)

Dyn

amic

par

amet

ers

(dB

)

9

9.5

10

10.5

11

11.5

12

EN

OB

(b

its)

SINAD_I

ENOB_I

SNR_I

SNR_Q

ENOB_Q

SINAD_Q

-90

-85

-80

-75

-70

-65

-60

-55

-50

2.25 2.35 2.45 2.55 2.65

VCCBI (V)

Dyn

amic

Par

amet

ers

(dB

c)

SFDR_QSFDR_I

THD_QTHD_I


13/30

Figure 17. Linearity vs. VCCBEFS=40Msps, ICCA=60mA, Fin=5MHz

Figure 18. Distortion vs. VCCBEFS=40Msps, ICCA=60mA, Fin=5MHz

60

61

62

63

64

65

66

67

68

69

70

2.25 2.75 3.25

VCCBE (V)

Dyn

amic

par

amet

ers

(dB

)

8

8.5

9

9.5

10

10.5

11

11.5

12

EN

OB

(b

its)

SINAD_I

ENOB_I

SNR_ISNR_Q

ENOB_Q

SINAD_Q

-110

-100

-90

-80

-70

-60

-50

-40

2.25 2.75 3.25

VCCBE (V)

Dyn

amic

Par

amet

ers

(dB

c)

SFDR_Q SFDR_I

THD_QTHD_I

Figure 19. Linearity vs. duty cycleFS=40MHz, ICCA=60mA, Fin=5MHz

Figure 20. Distortion vs. duty cycleFS=40MHz, ICCA=60mA, Fin=5MHz

40

50

60

70

80

90

100

48 49 50 51 52

Positive Duty Cycle (%)

Dyn

amic

par

amet

ers

(dB

)

4

5

6

7

8

9

10

11

12

EN

OB

(b

its)

SINAD_Q

SNR_Q

ENOB_Q

ENOB_I

SNR_I SINAD_I

-100

-90

-80

-70

-60

-50

-40

48 49 50 51 52

Positive Duty Cycle (%)

Dyn

amic

par

amet

ers

(dB

c)

THD_QSFDR_Q

THD_ISFDR_I


14/30

Figure 21. Single-tone 8K FFT at 40 Msps - Channel Q Fin = 5MHz, ICCA = 60mA, Vin@-1dBFS

Figure 22. Dual-tone 8K FFT at 40Msps - Channel Q Fin1 = 0.93MHz, Fin2 = 1.11MHz, ICCA = 70mA, Vin1@-7dBFS, Vin2@-7dBFS, IMD = -69dBc

2 4 6 8 12 14 16 18 2010

-20

-40

-60

-100

-80

-140

0

-120

Frequency (MHz)

Pow

er s

pect

rum

(dB

)

2.5 5 7.5 10 15 17.5 2012.5

-20

-40

-60

-100

-80

0

-120

Frequency (MHz)

Pow

er s

pect

rum

(dB

)

TSA1203 Application information

15/30

8 Application information

The TSA1203 is a dual-channel, 12-bit resolution high speed analog-to-digital converter based on a pipeline structure and deep sub-micron CMOS process to achieve the best performance in terms of linearity and power consumption.

Each channel achieves 12-bit resolution through the pipeline structure which consists of 12 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. A latency time of 7 clock periods is necessary to obtain the digitized data on the output bus.

The input signals are simultaneously sampled, for both channels, on the rising edge of the clock. The output data is delivered on the rising edge of the clock for channel I, and on the falling edge of the clock for channel Q, as shown in Figure 2: Timing diagram on page 4. The digital data produced at the various stages must be time-delayed according to the order of conversion. Finally, a digital data correction completes the processing and ensures the validity of the ending codes on the output bus.

The TSA1203 is pin-to-pin compatible with the dual 10 bits/20 Msps TSA1005-20, the dual 10 bits /40 Msps TSA1005-40 and the dual 12 bits/ 20 Msps TSA1204.

8.1 Additional functionsTo simplify the application board as much as possible, the following operating modes are provided:

● Output enable (OEB) mode

● Select mode

8.1.1 Output enable mode (OEB)

When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital output buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data arrives on the output with a very short Ton delay. This mechanism allows the chip select of the device.

Figure 2: Timing diagram on page 4 summarizes this functionality.

If you do not want to use OEB mode, the OEB pin should be grounded through a low value resistor.

8.1.2 Select mode (SELECT)

The digital data output from each of the ADC cores is multiplexed to share the same output bus. This prevents an increase in the number of pins and allows to use the same package as for a single-channel ADC like the TSA1201.

The information channel is selected with the "SELECT" pin. When set to high level (VIH), the channel I data is present on the D0-D11 output bus. When set to low level (VIL), the channel Q data is delivered on D0-D11.

By connecting SELECT to CLK, channel I and channel Q are simultaneously present on D0-D11, channel I on the rising edge of the clock and channel Q on the falling edge of the clock. (refer to Figure 2: Timing diagram on page 4).

Application information TSA1203

16/30

8.2 References and common mode connectionVREFM must always be connected directly to ground externally for most applications.

8.2.1 Internal reference and common mode

In the default configuration, the ADC operates with its own reference and common mode voltages generated by its internal bandgap. It is recommended to decouple the VREFP and INCM pins in order to minimize low and high frequency noise (see Figure 23).

Figure 23. Internal reference and common mode setting

8.2.2 External reference and common mode

Each of the voltages VREFP, VREFM and INCM can be fixed externally to better fit the application needs (refer to Table 5: Operating conditions on page 7 for min/max values). It is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior.

The VREFP and VREFM voltages set the analog dynamic range at the input of the converter that has a full scale amplitude of 2*(VREFP-VREFM).

The INCM voltage is half the value of VREFP-VREFM.

The best signal-to-noise performance is achieved with a dynamic range at its maximum value. To obtain this, VREFM can be connected to GND, and VREFP can be set up to 1.5 V maximum. However, signal to noise performance is a trade-off with the THD, with a possibility of degraded THD under these conditions.

To obtain the highest performance from the TSA1203 device, we recommend implementing the configuration shown in Figure 24 with the STMicroelectronics TS821 or TS4041-1.2 Vref.

TSA1203VIN

VINBVREFM

0.89V

VREFP330pF 4.7μF10nF

INCM330pF 4.7μF10nF

0.46V


17/30

Figure 24. External reference setting

8.3 Driving the differential analog inputsThe TSA1203 is designed to deliver optimum performance when driven on differential inputs. An RF transformer is an efficient way of achieving this high performance.

Figure 25 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46V. It determines the DC component of the analog signal. Being a high-impedance input, it acts as an I/O and can be externally driven to adjust this DC component. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Mini circuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog source.

Each analog input can drive a 1.4 Vpp amplitude input signal, so the resulting differential amplitude is 2.8 Vpp.

Figure 25. Differential input configuration with transformer

1kΩ

TSA1203VIN

VINBVREFM

VREFP

externalreference

VCCA

330pF 4.7μF10nF

TS821TS4041

1.2V

TSA1203VIN

VINBINCM

50Ω 33pF

330pF 470nF10nF

Analog source 1:1ADT1-1

channelsI or Q


18/30

Figure 26. AC-coupled differential input

Figure 26 represents the biasing of a differential input signal in an AC-coupled differential input configuration. Both inputs VIN and VINB are centered around the common mode voltage, which can be left internal, or fixed externally.

Figure 27. DC-coupled 2 Vpp differential analog input

Figure 27 shows a DC-coupled configuration with forced VREFP and INCM to the 1V DC analog input while VREFM is connected to ground; the differential amplitude obtained is 2 Vpp.

8.4 Clock inputThe quality of your TSA1203 converter is very dependent on your clock input accuracy, in terms of aperture jitter; the use of a low jitter crystal controlled oscillator is recommended.

Further points to consider in your implementation are:

● The duty cycle must be between 45% and 55%.

● The clock power supplies must be independent from the ADC output supplies to avoid digital noise modulation on the output.

● When powered-on, the circuit needs several clock periods to reach its normal operating conditions. Therefore, it is recommended to keep the circuit clocked to avoid random states before applying the supply voltages.

50Ω 10nF

TSA1203

VIN

VINB

INCM33pF100kΩ

100kΩ

50Ω 10nF

commonmode

TSA1203

VIN

VINBINCM

330pF 4.7µF10nF

analog

DC

AC+DC VREFP

VREFM

VREFP-VREFM = 1 V

DC

analog

VINCM = 0.5 V


19/30

8.5 Power consumption optimizationThe internal architecture of the TSA1203 makes it possible to optimize power consumption according to the sampling frequency of the application. For this purpose, an external resistor is placed between IPOL and the analog ground pins. Therefore, the total dissipation can be optimized over the full sampling range (0.5 Msps to 40 Msps).

The TSA1203 combines the highest performance with the lowest consumption at 40 Msps when Rpol is equal to 18 kΩ. This value is nevertheless dependent on the application and the environment.

In the lower sampling frequency range, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performance.

Table 12 gives some values to illustrate this.

8.6 Layout precautionsTo use the ADC circuits most efficiently at high frequencies, some precautions have to be taken for power supplies:

● The implementation of 4 proper separate supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is mandatory for high speed circuit applications to provide low inductance and low resistance common return.

The separation of the analog signal from the digital output part is essential to prevent noise from coupling onto the input signal. The best compromise is to connect AGND, DGND, GNDBI in a common point whereas GNDBE must be isolated. Similarly, the AVCC, DVCC and VCCBI power supplies must be separate from the VCCBE power supply.

● Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion.

● All inputs and outputs must be properly terminated with output termination resistors; thus, the amplifier load is resistive only and the stability of the amplifier is improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance.

● To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, use buffers or latches close to the output pins.

● Choose component sizes as small as possible (SMD).

Table 12. Total power consumption optimization depending on Rpol value

FS (Msps) 30 35 40

Rpol (kΩ) 38 28 18

Optimized power (mW) 145 180 215


20/30

8.7 EVAL1203/BA evaluation boardThe EVAL1203/BA is a 4-layer board with high decoupling and grounding level. The schematic of the board is shown in Figure 30 and its top overlay view in Figure 29. The board has been characterized with a fully devoted ADC test bench as shown in Figure 28.

All characterization measurements are made with:

■ SFSR=1 dB for static parameters,

■ SFSR=-1 dB for dynamic parameters.

Figure 28. Analog to digital converter characterization bench

Note: The analog input signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573.

Figure 29. Evaluation board printed circuit

Sine Wave Generator

HP8644

ADC evaluation

board

Pulse Generator

Logic Analyzer

Sine Wave GeneratorHP8644

HP8133

Vin

Clk

Data

Clk

PC


21/30

Figure 30. TSA1203 evaluation board schematic

RI1

50

R2 1K

R3

50

CI1

33pF

C2 330p

F

C3 470n

F

C4 10nF

CI8

330p

F

CI9

10nF

CI10

470n

FCI

11

330p

F

CI12

10nF

CI13

470n

F

C14

330p

F

C15

10nF

C16

470n

F

Raj1

47K

C17

330p

F

C18

10nF

C19

470n

F

J4 CLK

OEB

1

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7

D6

8

D7

9

GN

D10

LE11

Q0

19

Q1

18

Q2

17

Q3

16

Q4

15

Q5

14

Q6

13

Q7

12

VCC

20

U2

74LC

X57

3

OEB

1

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7

D6

8

D7

9

GN

D10

LE11

Q0

19

Q1

18

Q2

17

Q3

16

Q4

15

Q5

14

Q6

13

Q7

12

VCC

20

U3

74LC

X57

3

R11

47K

C25

330p

F

C27

10nF

C28

470n

F

+

C29

10µF

DO D7

D8

D9

D10

D11

CI30

330p

F

CI31

10nF

CI32

470n

F

+

C34

47µF

+

C35

47µF

AV

CC

VCC

B2

VCC

B1

C26

330p

F

C39

10nF

C37

470n

F

VCC

B3

C33

330p

F

C40

10nF

C38

470n

F

C41

10µF

+C4

247

µF

CLK

D1

D2

D3

D4

D5

D6

C20

330p

F

C21

10nF

C22

470n

F

C23

10µF

+

C36

47µF

1

43

26TI

2

T2-A

T1-1

WT

JI1B

InIB

R5 50

J25

CKD

ATA

12

J27

CON

2

RI19

50

S4SW

-SPS

TVCC

B1

GndB1VccB1GndB2VccB2GndB3VccB3

J17

BUFP

OW

D0

GN

D

D1

GN

D

D2

GN

D

D3

GN

D

D4

GN

D

D5

GN

D

D6

GN

D

D7

GN

D

D8

GN

D

D9

GN

D

D10

GN

D

D11

GN

D

CLK

GN

D

AV

CC

C5

100n

F

CI6

NM

VCC

B2

C51

330p

F

C52

10nF

C53

470n

FRS

I5 0 N

CRS

I6 0

RSI7

0

RSI8

0 RSI9

0 N

C

NM

: non

soud

éan

alog

inpu

tw

ith tr

ansf

orm

er (d

efau

lt)RS

5 R

S6 R

S7 R

S8 R

S9

C

C

C

C

C

C

C

sin

gle

inpu

tdi

ffer

entia

l inp

ut

12

J26

CON

2

AG

ND

1

INI

2

AG

ND

3

INBI

4

AG

ND

5

IPO

L6

AV

CC7

AG

ND

8

INQ

9

AG

ND

10

INBQ

11

AG

ND

12

REFPQ 13

REFMQ 14

INCMQ 15

AGND 16

AVCC 17

DVCC 18

DGND 19

CLK 20

SELECT 21

DGND 22

DVCC 23

GNDBI 24

GN

DBE

25V

CCBE

26D

11(M

SB)

27D

1028

D9

29D

830

D7

31D

632

D5

33D

434

D3

35D

236

D137 D0(LSB)38 VCCBE39 GNDBE40 VCCBI41 VCCBI42 OEB43 AVCC44 AVCC45 INCMI46 REFMI47 REFPI48

8-14

bits

AD

C

J9

AD

C D

UA

L12B CD

333

0pF

CD2

10nF

CD1

470n

F

1 Q

RQ1

50

CQ1

33pF

CQ8

330p

F

CQ9

10nF

CQ10

470n

F

CQ11

330p

F

CQ12

10nF

CQ13

470n

FCQ

30

330p

F

CQ31

10nF

CQ32

470n

F

1

43

26TQ

2

T2-A

T1-1

WT

JQ1B

InQ

B

RQ19

50

CQ6

NM

RSQ

5

0 N

CRS

Q6

0

RSQ

7

0 RSQ

8

0

RSQ

9

0 N

C

AV

CC

C10

330p

F

C11

10nF

C13

470n

F

C31

10µF

+

C32

47µF

DV

CC

DV

CCDV

cc

R21

0NM

R22

0NM

R23

0NM

R24

0NM

REFPREFMINCM

JI2

VRE

FI

REFPREFMINCM

JQ2

VRE

FQ

GN

DV

CCJA AN

ALO

GIC

GNDVCC

JDDIG

ITA

L

VCC

B1

SW1

S5 SW-S

PST

IN Vcc

GN

DS1S2 D

U1

STG

719

VCC

B2

VCC

B2

R12

47K

C43

10µF

+

C44

47µF

VCC

B3

VCC

B2Sw

itch

S4

O

EB M

ode

Ope

n

N

orm

al m

ode

Shor

t

H

igh

Impe

danc

e ou

tput

mod

e

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

J6

Switc

h S5

O

pen

Nor

mal

mod

e

Sh

ort

Test

mod

e

CLKD


22/30

Table 13. Printed circuit board — list of components

8.7.1 Evaluation board operating conditions

Name Footprint Name Footprint Name Footprint Name Part FootprintType

RSQ6 0 805 CD2 10nF 603 C26 330pF 603 CQ6 NC 805RSQ7 0 805 C40 10nF 603 C20 330pF 603 CI6 NC 805RSQ8 0 805 C39 10nF 603 C33 330pF 603 U2 74LCX573 TSSOP20RSI6 0 805 CQ12 10nF 603 C25 330pF 603 U3 74LCX573 TSSOP20RSI7 0 805 CQ9 10nF 603 CI1 33pF 603 U1 STG719 SOT23-6RSI8 0 805 C52 10nF 603 CQ1 33pF 603 JA ANALOGIC connectorR3 47 603 C18 10nF 603 C34 47µF RB.1 J17 BUFPOW connectorR5 47 603 C21 10nF 603 C42 47µF RB.1 J25 CKDATA SMARQ19 47 603 C4 10nF 603 C35 47µF RB.1 J4 CLK SMARI1 47 603 C15 10nF 603 C44 47µF RB.1 J27 CON2 SIP2RQ1 47 603 C27 10nF 603 C36 47µF RB.1 J26 CON2 SIP2 RI19 47 603 C11 10nF 603 C32 47µF RB.1 JD DIGITAL connectorRSI9 0NC 805 CI9 10nF 603 C37 470nF 805 JI1 InI SMARSQ5 0NC 805 CI12 10nF 603 CQ10 470nF 805 JI1B InIB SMARSQ9 0NC 805 CI31 10nF 603 C28 470nF 805 JQ1 InQ SMARSI5 0NC 805 CQ31 10nF 603 CI10 470nF 805 JQ1B InQB SMAR24 0NC 805 CQ30 330pF 603 CQ32 470nF 805 SW1 SWITCH connectorR23 0NC 805 CI11 330pF 603 CQ13 470nF 805 S5 SW-SPST connectorR21 0NC 805 C51 330pF 603 CI32 470nF 805 S4 SW-SPST connectorR22 0NC 805 C2 330pF 603 C13 470nF 805 TI2 T2-AT1-1WT ADTR2 1K 603 C17 330pF 603 C53 470nF 805 TQ2 T2-AT1-1WT ADTR12 47K 603 CD3 330pF 603 C16 470nF 805 JI2 VREFI connectorR11 47K 603 C10 330pF 603 C3 470nF 805 JQ2 VREFQ connectorRaj1 200K CQ8 330pF 603 C22 470nF 805 J6 32Pin

CQ11 330pF 603 CI13 470nF 805C23 10µF 1210 CI8 330pF 603 C38 470nF 805C41 10µF 1210 C14 330pF 603 CD1 470nF 805 NC: non solderedC29 10µF 1210 CI30 330pF 603 C19 470nF 805

VR5 trimmer

IDC-32 connector

Part Type

Part Type

Part Type

Table 14. Board connections for power supplies and other pins

Board marking Connection Internal voltage (V) External voltage (V)

AV AVCC 2.5

AG AGND 0

RPI REFPI 0.89 <1.4

RMI REFMI <0.4

CMI INCMI 0.46 <1

RPQ REFPQ 0.89 <1.4

RMQ REFMQ <0.4

CMQ INCMQ 0.46 <1

DV DVCC 2.5

DG DGND 0

GB1 GNDBI 0

VB1 VCCBI 2.5

GB2 GNDBE 0


23/30

Caution: Do not use the VB3 power supply (5 V) dedicated to the 74LCX573 external buffers to supply the VB2 of the TSA1203 which cannot exceed 3.3 V.

8.7.2 Consumption adjustment

Before beginning characterization tests, make sure to adjust the Rpol (Raj1), and therefore Ipol value, according to your sampling frequency.

8.7.3 Single and differential inputs

The test board can be driven on a single analog input, or on differential inputs. With a single analog input, you must use the ADT1-1WT transformer to generate a differential signal. In this configuration, the resistors RSI6, RSI7, RSI8 for channel I (respectively RSQ6, RSQ7, RSQ8 for channel Q) are connected as short-circuits whereas RSI5, RSI9 (respectively RSQ5, RSQ9 for channel Q) are open circuits.

Alternatively, you can use the JI1 and JI1B differential inputs. In this case, the resistances RSI5, RSI9 for channel I (respectively RSQ5, RSQ9 for channel Q) are connected as short-circuits whereas RSI6, RSI7, RSI8 (respectively RSQ6, RSQ7, RSQ8 for channel Q) are open circuits.

8.7.4 Mode selection

In order to select the channel you want to evaluate, you must set a jumper on the board in the relevant position for the SELECT pin (see Figure 31).

The channels selected depend on the position of the jumper:

● With the jumper connected to the upper connectors, channel I at the output is selected.

● With the jumper connected horizontally, channel Q at the output is selected.

● With the jumper connected to the lower connectors, both channels are selected, relative to the clock edge.

Figure 31. Mode selection

VB2 VCCBE 2.5/3.3

GB3 GNDB3 0

VB3 VCCB3 2.5

Table 14. Board connections for power supplies and other pins (continued)

Board marking Connection Internal voltage (V) External voltage (V)

SELECT

DVCCDGNDCLK

I channel

Q channel

I/Q channels

SELECT

Practical application examples TSA1203

24/30

9 Practical application examples

9.1 Digital interface applicationsThe wide external buffer power supply range of the TSA1203 makes it a perfect choice for plugging into 2.5 V or 3.3 V low voltage DSPs or digital interfaces.

9.2 Medical imaging applicationsDriven by the increasing demand for applications requiring either portability or a high degree of parallelism (or both), this product satisfies the requirements of medical imaging and telecom infrastructures.

The typical system diagram in Figure 32, shows how a narrow input beam of acoustic energy is sent into a living body via the transducer, and how the energy reflected back is analyzed.

Figure 32. Medical imaging application

The transducer is a piezoelectric ceramic such as zirconium titanate. The whole array can reach up to 512 channels. The TX beam former, amplified by the HV TX amps, delivers up to 100 V amplitude excitation pulses with phase and amplitude shifts. The mux and T/R switch is a two way input signal transmitter/ output receiver.

To compensate for skin and tissues attenuation effects, the time gain compensation (TGC) amplifier is an exponential amplifier that amplifies low voltage signals to the ADC input range. A differential output structure with low noise and very high linearity are essential factors.

These applications need high speed, low power and high performance ADCs. 10-12 bit resolution is necessary to lower the quantification noise. As multiple channels are used, a dual converter is a must for room saving issues.

The input signal is in the range of 2 to 20 MHz (mainly 2 to 7 MHz) and the application uses mostly a 4 over-sampling ratio for spurious free dynamic range (SFDR) optimization.

The next RX beam former and processing blocks enable the analysis of the output channels versus the input beam.

Mux andT/R switches

TX beam former

Processingand display

RX beam former

ADC

TGC amplifier

HV TX amps

TSA1203 Definitions of specified parameters

25/30

10 Definitions of specified parameters

Static parameters

Static measurements are performed using the histograms method on a 2 MHz input signal, sampled at 50 Msps, which is high enough to fully characterize the test frequency response. The input level is +1 dBFS to saturate the signal.

Differential non linearity (DNL)

The average deviation of any output code width from the ideal code width of 1 LSB.

Integral non linearity (INL)

An ideal converter exhibits a transfer function which is a straight line from the starting code to the ending code. The INL is the deviation from this ideal line for each transition.

Dynamic parameters

Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies sampled at 40 Msps.

The input level is -1dBFS to measure the linear behavior of the converter. All the parameters are given without correction for the full scale amplitude performance except the calculated ENOB parameter.

Spurious free dynamic range (SFDR)

The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc.

Total harmonic distortion (THD)

The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB.

Signal to noise ratio (SNR)

The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/ 2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB.

Signal to noise and distortion ratio (SINAD)

Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB.

The effective number of bits (ENOB) is easily deduced from the SINAD, using the formula:

SINAD= 6.02 × ENOB + 1.76 dB.

When the applied signal is not full scale (FS), but has an A0 amplitude, the SINAD expression becomes:

SINAD2Ao=SINADFull Scale+ 20 log (2A0/FS)

Definitions of specified parameters TSA1203

26/30

SINAD2Ao=6.02 × ENOB + 1.76 dB + 20 log (2A0/FS)

The ENOB is expressed in bits.

Analog input bandwidth

The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3 dB. Higher values can be achieved with smaller input levels.

Effective resolution bandwidth (ERB)

The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit.

Pipeline delay

Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles.

TSA1203 Package mechanical data

27/30

11 Package mechanical data

In order to meet environmental requirements, STMicroelectronics offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics trademark. ECOPACK specifications are available at: www.st.com.

11.1 TQFP48 package

DIM.mm. inch

MIN. TYP MAX. MIN. TYP. MAX.

A 1.6 0.063

A1 0.05 0.15 0.002 0.006

A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.17 0.22 0.27 0.007 0.009 0.011

C 0.09 0.20 0.0035 0.0079

D 9.00 0.354

D1 7.00 0.276

D3 5.50 0.216

e 0.50 0.020

E 9.00 0.354

E1 7.00 0.276

E3 5.50 0.216

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

K 0˚ 3.5˚ 7˚ 0˚ 3.5˚ 7˚

TQFP48 MECHANICAL DATA

0110596/C

Ordering information TSA1203

28/30

12 Ordering information

Part number Temperature range Package Packing Marking

TSA1203IFT-E -40° C to +85° C TQFP48 Tape & reel SA1203I

TSA1203IF -40° C to +85° C TQFP48 Tray SA1203I

EVAL1203/BA Evaluation board

TSA1203 Revision history

29/30

13 Revision history

Date Revision Changes

1-Feb-2003 1 Initial release.

2-Jan-2006 2Update of dynamic performance measurements in Table 2 on page 6.

26-Sep-2006 3Editorial updates. Reorganized document structure. No technical changes.

12-Dec-2006 4 Pin 42 renamed to CLKD.

TSA1203

30/30

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