Dislocations as native nanostructures – electronic properties

Manfred Reiche1),Martin Kittler2,3), Hartmut Uebensee4), Eckhard Pippel1) and Sigrid Hopfe1)

1) Max Planck Institute of Microstructure Physics, Weinberg 2, D-06120 Halle, Germany

2) ihp microelectronics, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany 3) IHP/BTU Joint Lab, K.-Wachsmann-Allee 1, D-03046 Cottbus, Germany

4) CIS Research Institute of Microsensorics and Photovoltaics, K.-Zuse-Str. 14, D-99099 Erfurt, Germany

(Received keep as blank , Revised keep as blank , Accepted keep as blank )

Abstract. Dislocations are basic crystal defects and represent one-dimensional native nanostructures embedded in a perfect crystalline matrix. Their structure is predefined by crystal symmetry. Two-dimensional, self-organized arrays of such nanostructures are realized reproducibly using specific preparation conditions (semiconductor wafer direct bonding). This technique allows separating dislocations up to a few hundred nanometers which enables electrical measurements of only a few, or, in the ideal case, of an individual dislocation. Electrical properties of dislocations in silicon were measured using MOSFETs as test structures. It is shown that an increase of the drain current results for nMOSFETs which is caused by a high concentration of electrons on dislocations in p-type material. The number of electrons on a dislocation is estimated from device simulations. This leads to the conclusion that metallic-like conduction exist along dislocations in this material caused by a one-dimensional carrier confinement. On the other hand, measurements of pMOSFETs prepared in n-type silicon proved the dominant transport of holes along dislocations. The experimentally measured increase of the drain current, however, is here not only caused by an higher hole concentration on these defects but also by an increasing hole mobility along dislocations. All the data proved for the first time the ambipolar behavior of dislocations in silicon. Dislocations in p-type Si form efficient one-dimensional channels for electrons, while dislocations in n-type material cause one-dimensional channels for holes.

Keywords: dislocations; one-dimensional nanostructures; electronic properties; MOSFETs;

semiconductor wafer bonding

1. Introduction

Dislocations are elementary crystal defects. The structure and electronic properties of

dislocations in silicon have been studied for more than five decades (Alexander and Teichler 1991;

Reiche and Kittler 2011). A large number of models of the structure of dislocation cores were

proposed by computer simulations. An experimental verification, however, is missing up to now.

Moreover, most of the techniques applied to characterize electronic properties require high

densities of dislocations. Analyzing such large numbers of these defects implies that interactions

between individual defects and interactions with other defects (point defects) are simultaneously

recorded. Therefore the optimum conditions to characterize electronic properties of these defects

Corresponding author, E-mail: reiche@mpi-halle.de

512

are measurements on individual dislocations. A way to realize defined arrangements of

dislocations and experimental measurements of only a few dislocations are demonstrated in the

present paper.

It is generally believed that dislocations result in significant effects on device parameters of

electronic circuits. A detrimental effect was proved if dislocations are generated in an uncontrolled

manner by high-temperature treatments during processing (Ravi 1981). Therefore they are avoided.

A beneficial effect, however, is obtained if dislocations are generated far from device active areas.

This effect is used, for instance, as internal gettering of impurities. Furthermore, dislocations may

be also considered as one-dimensional native nanostructures with extraordinary optical and

electronic properties (Kittler et al. 2007). For instance an increase of the electrical conductivity of

about four orders of magnitude compared to that of bulk silicon was measured along dislocations

(Reiche et al. 2010). If these distinguished properties are usable, devices (MOSFETs) with

dimensions below 10 nm and high on currents (ION) are feasible. Their realization, however,

requires the defined and reproducible generation of dislocation arrays.

2. Dislocations in Si

Silicon crystallizes in the cubic diamond structure (space group Fd3m). The lattice constant is a

= 0.543 nm. The glide plane is {111} and perfect dislocations have Burgers vectors of the type b =

a/2<110>. Two types of perfect dislocations are known in the diamond lattice: pure screw

dislocations and the so-called 60° dislocations, where the Burgers vectors are inclined at an angle

of 60° to the dislocation line (Hornstra 1958). Caused by the diamond structure, which

corresponds to two face-centered cubic (fcc) lattices displaced by (¼, ¼, ¼), two distinct sets of

{111} lattice planes exist, the closely spaced glide subset and the widely spaced shuffle subset

(Hirth and Lothe 1982). There was a long controversial discussion about the dominant dislocation

type in the diamond structure. Early investigations suggest the presence of dislocations in the

shuffle set because movement through one repeat distance on a shuffle plane breaks one covalent

bond per atomic length of dislocation (Seitz 1952), while an equivalent step on a glide plane

involves the breaking of three bonds (Amelinckx 1982). On the other hand, applications of

electron microscopy, especially of the weak-beam technique, have particularly shown that

dislocations in silicon are in general dissociated and glide in this extended configuration (Gomez

and Hirsch 1977; Ray and Cockayne 1971). Today, it is generally assumed that most of the

dislocations in silicon, especially after plastic deformation, belong to the glide set (Alexander

1986; Duesbery and Joós 1996).

The dissociation of a 60° dislocation results in a 30° partial and a 90° partial dislocation, while

a screw dislocation dissociates into two 30° partials. The dissociation follows the reaction

(Marklund 1979)

b b1 +b2 , (1)

where in the case of a 60° dislocation

0112

ab 121

6

a1b 111

6

a

2b (2a)

and for a screw dislocation

513

Fig. 1 Cross-section image ({110} plane) of two screw dislocations in silicon. The diameter of the

dislocation cores is about 1 nm. High-resolution electron microscope (HREM) image.

0112

ab 121

6

a1b 211

6

a

2b (2b)

holds.

Numerous models have been proposed about the structure of dislocations (Reiche and Kittler

2011). Because dislocations are line defects, a structural disorder exist only in one dimension. This

so-called dislocation core may be a few micrometers in length but has a diameter of only 1 nm

(Fig. 1). First models of perfect dislocations assumed dangling bonds in their core (Hornstra 1958).

Experimental data, however, obtained mainly by electron paramagnetic resonance (EPR)

spectroscopy refer to a low density of such dangling bonds (Alexander and Teichler 1991).

Therefore different models of the reconstruction of perfect and partial dislocations have been

proposed by computer simulation (Bulatov and Cai 2006).

3. Fabrication of defined dislocation arrangements

Most of the studies of optical and electronic properties of dislocations used plastically

deformed silicon in order to achieve defined dislocation arrangements and a high density of

dislocations to attain the detection limit of the methods applied (Alexander and Teichler 1991;

Kveder et al. 2001; Schröter and Cerva 2002). Plastic deformation, however, result also in a large

number of point defects and defect reactions making it sometimes difficult to interpret

experimental data (Alexander and Teichler 1991). In order to avoid interactions between

dislocations or between dislocations and other defects, methods are required allowing the

realization and analyses of only a few dislocations or, in the ideal case, of an individual

dislocation. A method to realize defined dislocation arrangements in a reproducible way is

semiconductor wafer direct bonding (SWDB) originally developed to produce silicon on insulator

(SOI) substrates and three-dimensional micro-electromechanical systems (MEMS) (Tong and

Gösele 1999). If two wafers are joined together without any interface layers, a two-dimensional

dislocation network is obtained analogous to early experiments on bicrystals (Thibault-Desseaux

514

et al. 1989). For bicrystals a Czochralski growth process is required allowing only the formation of

specific grain boundaries such as = 9 (rotation 38°56´17´´, boundary plane (122), common [011]

axis), = 13 (rotation 26°37´12´´, boundary plane (510), common [001] axis), and = 25 large

angle grain boundaries (rotation 16°15´36´´, boundary plane (710), common [001] axis) (Aubert

and Bacmann 1987). Semiconductor wafer direct bonding, on the other hand, uses commercially

available wafers making it possible to realize any grain boundary. Especially small angle grain

boundaries having rotational angles << 1° are of interest allowing dislocation distances of a few

hundred nanometers. Applying state of the art techniques for preparation and analyses individual

or a small number of dislocations can be characterized.

Semiconductor wafer direct bonding (SWDB), or fusion bonding, describes a method to join

two or more mirror-polished semiconductor wafers at room temperature without the addition of

any glue or external forces. The most common technique is the bonding of oxidized (hydrophilic)

wafers. When, as in the case of silicon, the oxide layer is removed with HF, a hydrophobic surface

with unique properties is obtained, i.e., having a good resistance to chemical attacks and a low

surface recombination velocity. This means a surface with a very low density of surface states. The

removing of the oxide results that two silicon crystal lattices are in contact and Si-Si bonds are

formed via the interface. Crystal defects (dislocations) are generated forming a two-dimensional

network in order to match both crystal lattices. The structure of the dislocation network depends

on the surface orientation of both wafers. Bonding of Si(100) wafers, for instance, cause a = 1

(100) small angle grain boundary characterized by a square-like mesh of screw dislocations

expected from theory (Bollmann 1970). An example is shown in Fig. 2a. These dislocations are

formed by the rotational misfit (twist) between both crystal lattices. There is, however, an

additional tilt component caused by the deviation on the [001] axis of real wafers (cut-off). The tilt

component is compensated by a periodic array of 60° dislocations. The spacings between

dislocations S in both networks are indirectly proportional to the misalignment angle and are given

by

(3)

for the screw dislocation network. On the other hand, the relation between dislocation distance and

tilt angle of the network formed by 60°-dislocations follows as

(4)

In both equations a means the lattice constant and twist and tilt are the angles of misorientation of

the twist and tilt component, respectively.

Reactions between screw and 60° dislocations are occurred during additional annealing treatments

after the initial bonding. Depending on the temperature, mixed dislocations may be formed having

different Burger vector components. Besides this reaction, also dissociation reactions of screw

dislocations are dominant processes even at annealing above 1100°C. Fig. 2b shows one set of

screw dislocations of the network in Fig. 2a under weak-beam conditions. A splitting of the

2 2 sin2

twisttwist

aS

tilttilt

aS

tan2

515

Fig. 2 Scanning transmission electron microscope (STEM) plan-view image of a screw dislocation network

formed by wafer bonding of Si(100) wafers (a). Weak beam image of one set of dislocations (b). HAADF-

STEM image of a dissociated screw dislocation (c). The image was color coded for clearness. A part of the

defect is shown at higher magnification in (d). Red dots characterize dumbbells of the (undisturbed) Si

matrix, while blue and yellow dots characterize dumbbells at the partial dislocation and stacking fault,

respectively. Samples with <100> orientation were used for Figures (a) and (b), while Figures (c) and (d)

were produced from <110> oriented cross sections of the same dislocation network.

dislocation lines can be seen indicating the dissociation of perfect screw dislocation. The

dissociation follows Eq. (1) and result in the formation of two 30° partial dislocations according to

a) b)

c) d)

516

Eq. (2b). The distance between both partial dislocations is about 2 nm. More details of these

defects are obtained by high-resolution electron microscopy (HREM) and high-angle annular dark

field (HAADF) imaging. Fig. 2c shows a color coded HAADF image of a dissociated screw

dislocation with the stacking fault between both 30° partial dislocations. The size of the stacking

fault is 2 nm which corresponds to the data of weak-beam analysis. At higher magnification silicon

dumbbells are clearly resolved in the HAADF images of Si[110], in which two Si columns

areseparated by 0.136 nm (Fig. 2d). The changes of the symmetry of the dumbbells are cleary seen

at the partial dislocation and stacking fault. The different colors in the figure characterize these

changes. Further investigations in combination with computer simulations are required to explain

the structure of the partial dislocations and stacking fault.

4. Electronic properties of dislocations 4.1 Properties of dislocations in bonded interfaces

Dislocations in the interface of bonded wafers possess numerous remarkable properties which

may be used for different applications (Kittler and Reiche 2009; Kittler et al. 2007). The electrical

properties of bonded hydrophobic silicon wafers were studied for the first time by Bengtsson et al.

(Bengtsson et al. 1992). The measurement of the capacitance-voltage (CV) characteristics on

bonded unipolar wafers were interpreted on the assumption of two distributions of interface states,

one of acceptors and one of donors, causing a potential barrier at the bonded interface. The origin

of the interface states was assumed to be impurities and crystal defects. More recent analyses by

electron beam induced current (EBIC) technique proved barrier heights generally smaller than 100

meV for different types of bonded hydrophobic wafers (Yu et al. 2006). The concentration of deep

levels along the interface was determined to be a few 105 per cm. Low concentrations of deep

levels at the interface are also the reason for low dark currents, an improved CV-characteristics,

and fast rise times of pin-diodes prepared on bonded hydrophobic wafers (Reiche et al. 2002).

One-dimensional conductive channels formed by defects in solar silicon have already been

demonstrated (Kittler et al. 2008). An analysis of dislocation networks in Si revealed a similar

feature. The EBIC micrograph in Fig. 3a shows a horizontal bright line extending from the

Schottky contact on the upper right corner over a large distance. This demonstrates the transport of

minority carriers along the dislocation network towards the collecting Schottky barrier. The

transport of minority carriers over distances of more than 10 mm has been observed (Kittler et al.

2008).

4.2 Analyses of individual dislocations

The study of individual dislocations or only of a small number of dislocations is an im

portant issue because all of the interactions between defects can be eliminated. This result

in more precise data about the electronic structure of dislocations and, combining these in-

vestigations with microscopic observations, conclusions about the correlation between the struc-

ture and properties of dislocations can be derived. A combination of bonded wafer pairs with

preparation methods to separate individual dislocations or a small number of dislocations allow

such experiments. Twist angles between two bonded Si wafers below 0.1° results in dislocation

517

Fig. 3 Formation of a conducting channel along the dislocation network in the interface of a bonded Si wafer

pair (a). EBIC micrograph. Sketch of the experimental setup (b).

distances of more than 100 nm (Eqs. 3,4). Using photolithography and etching techniques,

individual dislocations can be separated and measured.

Diodes and metal-oxide-semiconductor field-effect transistors (MOSFETs) were prepared on such

bonded wafers. In order to avoid the effect of bulk material, dislocation networks were realized in

SOI wafers having only a thin device layer. The substrates were prepared by hydrophobic wafer

bonding of commercially available SOI wafers. After dipping in diluted HF the wafers were

immediately bonded under hydrophobic conditions in an atmospheric environment. Various twist

angles in the range of 0.01° < twist < 0.65° were realized. The bonded wafer pairs were annealed at

temperatures between 1000°C and 1100°C for 4 hours in nitrogen. Finally one of the handle

wafers was removed by a combination of mechanical grinding and chemical etching (spin etching)

followed by chemical etching of the oxide layer. This process results in SOI wafers having 2-

dimensional dislocation networks in their thin device layers (Fig. 4a). SOI MOSFETs were

prepared on such substrates using lithographic techniques and reactive ion etching (RIE).

The channel region was defined first. Because dislocations are parallel to <110>- directions in

Fig. 4 TEM cross-section image of a SOI substrate with a dislocation network in the device layer (a). The

dislocation distance is about 15 nm corresponding to a twist angle of about 0.7°. Scheme of a MOSFET

having a dislocation in the channel (b). Because dislocations are parallel to <110>-directions in Si, they are

parallel to the channel and source and drain form electrical contacts. The gate electrode is not shown in the

scheme.

a) b)

a) b)

518

Fig. 5 Output and transfer characteristics of nMOSFETS without dislocations (a,b) and with a dislocation

network (c,d). The device layer thickness was 80 nm. The channel length and width, respectively, for both

devices are 1 µm. Caused by the different threshold voltages (VT) of both devices, the gate voltage (VG) is

represented for clarity as VG – VT.

Si, they are parallel to the channel (Fig. 4b). In order to study the effect of the dislocation density,

channel width and length, respectively, are varied between 1 µm and 10 µm. Source and drain

contacts were formed by As+ implantation (5 keV, 1∙1015cm-2) combined with a RTA step (950°C,

60 sec.). A thin gate oxide of about 6 nm was formed by thermal oxidation. The device gates were

prepared by low-pressure chemical vapor deposition (LP-CVD) of polycrystalline silicon (100 nm

thick) followed by As+ implantation (30 keV, 1∙1015cm-2) and a RTA step (950°C, 60 sec). Finally,

contacts were formed by Al deposition and annealing at 420°C for 30 minutes in hydrogen.

The I-V characteristics of nMOSFETs with and without dislocation networks in the channel are

shown in Fig. 5. The thickness of the device layer was about 80 nm. The channel length is 1µm.

Typical output and transfer characteristics are obtained for the reference sample without a

dislocation (Figs. 5 a,b). The devices are characterized by a subthreshold slope S =100 mV/dec.

and a threshold voltage VT = -150 mV. The output and transfer characteristics of a device with a

dislocation network in the channel are shown in Figs. 5c and 5d. It can be seen that higher drain

currents (ID) are measured at the same gate (VG) and drain (VD) voltages, compared to devices

-1,0 -0,5 0,0 0,5 1,0 1,5 2,0

0

1

2

3

VSD

(V)

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

I D (A

)

VG-V

T (V)

0,0 0,5 1,0 1,5 2,0

0

1

2

3

VG (V)

0

0.33

0.66

1.00

1.33

1.66

2.00

I D (A

)

VD (V)

0.0 0.5 1.0 1.5 2.0

10

20

30

40

50

I D (A

)

VD (V)

VG (V)

0

0.1

0.2

0.3

0.4

0.5

-0,4 -0,2 0,0 0,2 0,4 0,6 0,80

10

20

30

40

50

VD (V)

0.0

0.1

0.2

0.3

0.4

I D (A

)

VG-V

T (V)

b) a)

c) d)

519

without a dislocation network. The increase of the drain current even at very low gate voltages is

about one order of magnitude. Similar results were also obtained by other authors (Ishikawa et al.

2006) and are ascribed to the presence of dislocations. The relatively high source-drain current

even at VG = 0V, in contrast to the reference sample, indicates the presence of charged carriers on

the dislocations.

Analyses of the device data clearly proved that the number of dislocations in the channel

characteristically affects the device parameter. Indications are found by measurements on devices

prepared on wafers having dislocation networks with different dislocation density. Such networks

are realized by varying the twist angle during the wafer bonding process. Besides devices prepared

on a dislocation network with twist = 0.31° (resulting in a dislocation spacing of about 35 nm)

analogous samples were prepared on a wafer having a dislocation network characterized by twist

= 0.035°. Here, the dislocation spacing is about 150 nm. Using channel widths W between 1 µm

and 10 µm, devices having about 660 dislocations (at a dislocation spacing of 15 nm and W = 10

µm) up to 6 dislocations per channel at a dislocation spacing of 150 nm and W = 1 µm were

prepared. The ID – VD curves of these devices show that the drain current depends on the number

of dislocations in the channel. At VD = 2 V, a drain current of 310-3 A is obtained if there are only

6 dislocations in the channel. On the other hand, a value of ID = 210-6 A is measured under the

same conditions if the channel includes about 660 dislocations. If the drain current is plotted as a

function of the number of dislocations, a linear relation is obtained (Reiche et al. 2011). It is

shown that the drain current decreases as the number of dislocations in the channel increases.

Fitting the data allows to extrapolate the current given by one dislocation of more than 10-2 A,

which corresponds to a current density of more than 100 A/cm.

The application of MOSFETs allows not only the advantageous measurement of electronic

properties of a few dislocations but also a more detailed interpretation of the data by means of

device physical principles. For instance, commercially available device simulation programs make

it possible to calculate the current-voltage characteristics of MOSFETs enabling conclusions about

the physical reasons behind. The ATHENA/ATLAS simulation package (Silvaco) was used

(Reiche et al. 2013). Because dislocations represent conductive channels, they are assumed as thin

n-type layers embedded in the 80 nm thick channel. The ID-VD- and ID-VG characteristics are

calculated and compared with the experimentally measured ones by fitting the donor concentration

in this thin layer. It was shown that a donor concentration of 31018 cm-3 in the thin layer results in

an increase of ID by one order of magnitude as proved by experimental measurements. This is

caused by the formation of a conductive channel along the thin (dislocation) layer already at very

low drain and gate voltages. The reference transistor without dislocations, however, is charac-

terized by an electron concentration more than one order of magnitude lower. A conductive

channel is not formed under these conditions. Since the donor concentration is equal the electron

concentration, the number of electrons in the 2 nm thick layer is estimated to be 6000 for W = L =

1 µm. Furthermore, the behavior of the subtreshold slope refers to an inhomogeneous electron con-

centration (Reiche et al. 2011) which suggests that all electrons are bounded to dislocations. TEM

investigations revealed that there are 30 dislocations in the channel for this specific case, which

means about 200 electrons per micrometer dislocation length. This corresponds to the maximum

number of electrons on a dislocation (Kveder and Kittler 2008). Assuming a homogeneous

distribution along the dislocation line, the distance between free electrons on the dislocation core

is about 5 nm. There is no evidence up to now about the locations of electrons on the dislocation

core. The distance of about 5 nm is significantly smaller than the distance of dislocation nodes in

the network (about 30 nm in this case) and means that electrons are located on straight dislocation

520

segments. Moreover, kinks on dislocations could be a promising candidate. But only narrow kink-

kink distances of about d 2b 1.6 nm are stable. Here b is the length of the Burgers vector.

Larger kink-kink distances up to d 10b were calculated but it was shown that such wide kinks

are intermediate states only. Therefore metallic conduction along dislocation lines in the p-type

material is assumed in accordance with other authors (Labusch and Schröter 1980). It is caused by

a two-dimensional carrier confinement along dislocations. The assumption of a metallic-like

behaviour may explain also the occurrence of Coulomb blockades proved by low-temperature

measurements at T = 5 K. These investigations showed a staircase-like behavior of the con-

ductance G as a function of VG if screw dislocations are present, while periodic oscillations of G

are obtained for mixed dislocations resulting from the reaction of screw with 60° dislocations

(Reiche and Kittler 2012). The distances of the Coulomb islands were calculated to be about 4 nm

for screw dislocations and about 8 nm for mixed dislocations. These values are in good agreement

with distances of electrons of 5 nm estimated from simulations.

4.3 Carriers on dislocations

As shown above, MOSFETs are an excellent tool to analyze electronic properties of

dislocations. An excess concentration of electrons was proved for dislocations introduced in the

channel of nMOSFETs. Such devices are typically produced in p-type silicon. A completely

different behavior is obtained, if pMOSFETs are prepared in the same p-type material. Then the

drain current measured for such devices without dislocations (reference) is about one order of

magnitude lower as for equivalent nMOSFETs. This is mainly due to the lower mobility of holes

compared to that of electrons in silicon. A further reduction of ID by a factor of 100 or more is

observed if dislocations are present in the channel (Figs. 6a,b). The measured values of ID are also

lower by a factor of about 105 compared to data of equivalent nMOSFETs. In addition, also higher

drain and gate voltages are required for measurements of pMOSFETs. This suggests the suppres-

sion of the transport of holes via dislocations in p-type material. It can be assumed that electrons

existing on dislocations (resulting in the increase of ID for nMOSFETs) lead to a compensation of

injected holes in the case of pMOSFETs. Furthermore, measurements on numerous devices refer to

a different behavior of pMOSFETs prepared on varying p-type substrates containing dislocation

networks of different dislocation types. Assuming the same conditions (VG = -3.5V, VD = -3V) a

drain current of ID = -2 nA is measured if only 60° dislocations are present, while only ID = -0.5 nA

is determined if screw dislocations are dominantly present in the channel.

Drain currents comparable to nMOSFETs are obtained if pMOSFETs without dislocations are

realized in n-type material. A typical value of ID is about 2 µA at VG = VD = -1V (Fig. 6c). The

introduction of dislocations into the channel of such pMOSFETs results in a further increase of ID.

The drain current reaches about 16 µA at VG = VD = -1V, i.e. an increase by a factor of 8, which,

however, is significantly smaller than for nMOSFETs. This means that there is an extra transport

of holes via dislocations in p-type material. Because the mobility of holes in silicon is lower than

for electrons, the increase of the drain current in n-type material is lower than in p-type material.

This interpretation is confirmed by device simulations of pMOSFETs showing that not only the

concentration of carriers is important (as in the case of the nMOSFETs). Instead, a simultaneous

increase of the hole mobility is also required to interpret the measured data of pMOSFETs. All

these experimental data refer to different electronic properties of dislocations in n-type material

521

-4 -3 -2 -1 0

0,0

-0,1

-0,2

-0,3

-0,4

-0,5

-0,6

VD (V)

-4

-3.5

-3

-2.5

-2

-1.5

-1

0.5

I D (

nA

)

VG (V)

-4 -3 -2 -1 0

0

-20

-40

-60

-80

-100

-120

VD (V)

-1.2

-1

-0.8

-0.6

-0.4

I D (

nA

)

VG (V)

Fig. 6 Drain current (ID) vs. gate voltage (VG) for pMOSFETs prepared in p-type silicon (a,b) and n-type

silicon (c,d). Figs. (a) and (c) are from measurements on reference devices without dislocations, while Figs.

(b) and (c) are obtained from devices with dislocations in the channel. Note the different scale.

compared to such defects in p-type material. It can be stated that a dislocation in p-type silicon

forms an efficient one-dimensional channel for electrons, while a dislocation in n-type material

causes a one-dimensional channel for holes. A more detailed discussion on the base of the band

structure is given elsewhere (Kittler et al. 2013).

5. Conclusions

The embedding of two-dimensional configurations of well-defined numbers and types of dislo-

cations into channels of MOSFETs is eminently suited to analyse the electrical properties of only a

few or individual dislocations.

A method to realize defined arrangements in a reproducible way is hydrophobic wafer bonding.

Two-dimensional dislocation networks are produced if two wafers are bonded. The length and

distance of the dislocations in a network is defined by the mesh size and can be up to several

micrometers. Combining wafer bonding with pattern formation techniques (photolithography and

-2 -1 0 1 2

0

-4

-8

-12

-16

VD (V) -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1

I D (

µA

)

VG (V)

-1 0 1 2

0

-1

-2

I D (

µA

)

VG (V)

VD (V) -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 -0

b) a)

c) d)

522

dry etching) devices were realized allowing the measurement of the electrical properties of only a

few dislocations.

Measurements of the characteristics of MOSFETs refer to an ambipolar character of

dislocations in silicon. Devices prepared in p-type material show an increase of the drain current

by more than one order of magnitude for nMOSFETs while a decrease of ID is found for

pMOSFETs. This indicates that electrons are present on the core of dislocations in p-type material.

Device simulations revealed about 200 electrons per micrometer dislocation length corresponding

to a distance between free electrons of about 5 nm. The investigations refer to a metallic-like

conductance along the dislocations caused by a two-dimensional carrier confinement.

An increase of the drain current was proved also for pMOSFETs fabricated in n-type material.

This means that holes are transported via dislocations under these conditions. The increase of ID,

however, is smaller than for nMOSFETs in p-type material.

Acknowledgments

This work was financially supported by the German Federal Ministry of Education and

Research in the framework of the SiGe-TE project (contract no. 03X3541B).

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